[ARM] Implement TARGET_SCHED_MACRO_FUSION_PAIR_P
* config/arm/arm-protos.h (tune_params): Add fuseable_ops field. * config/arm/arm.c (arm_macro_fusion_p): New function. (arm_macro_fusion_pair_p): Likewise. (TARGET_SCHED_MACRO_FUSION_P): Define. (TARGET_SCHED_MACRO_FUSION_PAIR_P): Likewise. (ARM_FUSE_NOTHING): Likewise. (ARM_FUSE_MOVW_MOVT): Likewise. (arm_slowmul_tune, arm_fastmul_tune, arm_strongarm_tune, arm_xscale_tune, arm_9e_tune, arm_v6t2_tune, arm_cortex_tune, arm_cortex_a8_tune, arm_cortex_a7_tune, arm_cortex_a15_tune, arm_cortex_a53_tune, arm_cortex_a57_tune, arm_cortex_a9_tune, arm_cortex_a12_tune, arm_v7m_tune, arm_v6m_tune, arm_fa726te_tune arm_cortex_a5_tune): Specify fuseable_ops value. From-SVN: r219470
This commit is contained in:
Kyrylo Tkachov
Kyrylo Tkachov
parent
49c8bc0c77
commit
8b898d4cbd
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@ -1,3 +1,19 @@
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2015-01-12 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/arm-protos.h (tune_params): Add fuseable_ops field.
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* config/arm/arm.c (arm_macro_fusion_p): New function.
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(arm_macro_fusion_pair_p): Likewise.
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(TARGET_SCHED_MACRO_FUSION_P): Define.
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(TARGET_SCHED_MACRO_FUSION_PAIR_P): Likewise.
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(ARM_FUSE_NOTHING): Likewise.
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(ARM_FUSE_MOVW_MOVT): Likewise.
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(arm_slowmul_tune, arm_fastmul_tune, arm_strongarm_tune,
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arm_xscale_tune, arm_9e_tune, arm_v6t2_tune, arm_cortex_tune,
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arm_cortex_a8_tune, arm_cortex_a7_tune, arm_cortex_a15_tune,
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arm_cortex_a53_tune, arm_cortex_a57_tune, arm_cortex_a9_tune,
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arm_cortex_a12_tune, arm_v7m_tune, arm_v6m_tune, arm_fa726te_tune
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arm_cortex_a5_tune): Specify fuseable_ops value.
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2015-01-12 H.J. Lu <hongjiu.lu@intel.com>
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PR bootstrap/64561
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@ -289,6 +289,8 @@ struct tune_params
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bool string_ops_prefer_neon;
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/* Maximum number of instructions to inline calls to memset. */
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int max_insns_inline_memset;
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/* Bitfield encoding the fuseable pairs of instructions. */
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unsigned int fuseable_ops;
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};
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extern const struct tune_params *current_tune;
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@ -257,6 +257,7 @@ static void arm_expand_builtin_va_start (tree, rtx);
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static tree arm_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
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static void arm_option_override (void);
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static unsigned HOST_WIDE_INT arm_shift_truncation_mask (machine_mode);
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static bool arm_macro_fusion_p (void);
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static bool arm_cannot_copy_insn_p (rtx_insn *);
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static int arm_issue_rate (void);
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static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
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@ -297,6 +298,8 @@ static int arm_cortex_m_branch_cost (bool, bool);
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static bool arm_vectorize_vec_perm_const_ok (machine_mode vmode,
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const unsigned char *sel);
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static bool aarch_macro_fusion_pair_p (rtx_insn*, rtx_insn*);
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static int arm_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
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tree vectype,
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int misalign ATTRIBUTE_UNUSED);
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@ -404,6 +407,12 @@ static const struct attribute_spec arm_attribute_table[] =
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#undef TARGET_COMP_TYPE_ATTRIBUTES
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#define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
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#undef TARGET_SCHED_MACRO_FUSION_P
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#define TARGET_SCHED_MACRO_FUSION_P arm_macro_fusion_p
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#undef TARGET_SCHED_MACRO_FUSION_PAIR_P
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#define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
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#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
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#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
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@ -1647,6 +1656,9 @@ const struct cpu_cost_table v7m_extra_costs =
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}
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};
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#define ARM_FUSE_NOTHING (0)
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#define ARM_FUSE_MOVW_MOVT (1 << 0)
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const struct tune_params arm_slowmul_tune =
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{
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arm_slowmul_rtx_costs,
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@ -1663,7 +1675,8 @@ const struct tune_params arm_slowmul_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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false, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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const struct tune_params arm_fastmul_tune =
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@ -1682,7 +1695,8 @@ const struct tune_params arm_fastmul_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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false, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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/* StrongARM has early execution of branches, so a sequence that is worth
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@ -1704,7 +1718,8 @@ const struct tune_params arm_strongarm_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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false, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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const struct tune_params arm_xscale_tune =
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@ -1723,7 +1738,8 @@ const struct tune_params arm_xscale_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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false, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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const struct tune_params arm_9e_tune =
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@ -1742,7 +1758,8 @@ const struct tune_params arm_9e_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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false, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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const struct tune_params arm_v6t2_tune =
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@ -1761,7 +1778,8 @@ const struct tune_params arm_v6t2_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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false, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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/* Generic Cortex tuning. Use more specific tunings if appropriate. */
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@ -1781,7 +1799,8 @@ const struct tune_params arm_cortex_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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false, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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const struct tune_params arm_cortex_a8_tune =
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@ -1800,7 +1819,8 @@ const struct tune_params arm_cortex_a8_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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true, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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const struct tune_params arm_cortex_a7_tune =
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@ -1819,7 +1839,8 @@ const struct tune_params arm_cortex_a7_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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true, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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const struct tune_params arm_cortex_a15_tune =
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@ -1838,7 +1859,8 @@ const struct tune_params arm_cortex_a15_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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true, true, /* Prefer 32-bit encodings. */
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true, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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const struct tune_params arm_cortex_a53_tune =
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@ -1857,7 +1879,8 @@ const struct tune_params arm_cortex_a53_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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false, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_MOVW_MOVT /* Fuseable pairs of instructions. */
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};
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const struct tune_params arm_cortex_a57_tune =
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@ -1876,7 +1899,8 @@ const struct tune_params arm_cortex_a57_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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true, true, /* Prefer 32-bit encodings. */
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false, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_MOVW_MOVT /* Fuseable pairs of instructions. */
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};
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/* Branches can be dual-issued on Cortex-A5, so conditional execution is
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@ -1898,7 +1922,8 @@ const struct tune_params arm_cortex_a5_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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true, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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const struct tune_params arm_cortex_a9_tune =
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@ -1917,7 +1942,8 @@ const struct tune_params arm_cortex_a9_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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false, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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const struct tune_params arm_cortex_a12_tune =
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@ -1936,7 +1962,8 @@ const struct tune_params arm_cortex_a12_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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true, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_MOVW_MOVT /* Fuseable pairs of instructions. */
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};
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/* armv7m tuning. On Cortex-M4 cores for example, MOVW/MOVT take a single
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@ -1962,7 +1989,8 @@ const struct tune_params arm_v7m_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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false, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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/* Cortex-M7 tuning. */
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@ -1983,7 +2011,8 @@ const struct tune_params arm_cortex_m7_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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false, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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/* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than
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@ -2004,7 +2033,8 @@ const struct tune_params arm_v6m_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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false, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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const struct tune_params arm_fa726te_tune =
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@ -2023,7 +2053,8 @@ const struct tune_params arm_fa726te_tune =
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false, /* Prefer Neon for 64-bits bitops. */
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false, false, /* Prefer 32-bit encodings. */
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false, /* Prefer Neon for stringops. */
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8 /* Maximum insns to inline memset. */
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8, /* Maximum insns to inline memset. */
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ARM_FUSE_NOTHING /* Fuseable pairs of instructions. */
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};
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@ -29157,6 +29188,73 @@ arm_gen_setmem (rtx *operands)
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return arm_block_set_aligned_non_vect (dstbase, length, value, align);
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}
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static bool
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arm_macro_fusion_p (void)
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{
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return current_tune->fuseable_ops != ARM_FUSE_NOTHING;
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}
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static bool
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aarch_macro_fusion_pair_p (rtx_insn* prev, rtx_insn* curr)
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{
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rtx set_dest;
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rtx prev_set = single_set (prev);
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rtx curr_set = single_set (curr);
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if (!prev_set
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|| !curr_set)
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return false;
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if (any_condjump_p (curr))
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return false;
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if (!arm_macro_fusion_p ())
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return false;
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if (current_tune->fuseable_ops & ARM_FUSE_MOVW_MOVT)
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{
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/* We are trying to fuse
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movw imm / movt imm
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instructions as a group that gets scheduled together. */
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set_dest = SET_DEST (curr_set);
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if (GET_MODE (set_dest) != SImode)
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return false;
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/* We are trying to match:
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prev (movw) == (set (reg r0) (const_int imm16))
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curr (movt) == (set (zero_extract (reg r0)
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(const_int 16)
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(const_int 16))
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(const_int imm16_1))
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or
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prev (movw) == (set (reg r1)
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(high (symbol_ref ("SYM"))))
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curr (movt) == (set (reg r0)
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(lo_sum (reg r1)
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(symbol_ref ("SYM")))) */
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if (GET_CODE (set_dest) == ZERO_EXTRACT)
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{
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if (CONST_INT_P (SET_SRC (curr_set))
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&& CONST_INT_P (SET_SRC (prev_set))
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&& REG_P (XEXP (set_dest, 0))
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&& REG_P (SET_DEST (prev_set))
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&& REGNO (XEXP (set_dest, 0)) == REGNO (SET_DEST (prev_set)))
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return true;
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}
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else if (GET_CODE (SET_SRC (curr_set)) == LO_SUM
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&& REG_P (SET_DEST (curr_set))
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&& REG_P (SET_DEST (prev_set))
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&& GET_CODE (SET_SRC (prev_set)) == HIGH
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&& REGNO (SET_DEST (curr_set)) == REGNO (SET_DEST (prev_set)))
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return true;
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}
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return false;
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}
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/* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
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static unsigned HOST_WIDE_INT
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