[AArch64] Cleanup logic around aarch64_final_prescan
* config/aarch64/aarch64.h (ADJUST_INSN_LENGTH): Wrap definition in do while (0). * config/aarch64/aarch64.c (is_mem_p): Delete. (is_memory_op): Rename to... (has_memory_op): ... This. Use FOR_EACH_SUBRTX. (dep_between_memop_and_curr): Assert that the input is a SET. (aarch64_madd_needs_nop): Add comment. Do not call dep_between_memop_and_curr on NULL body. (aarch64_final_prescan_insn): Add comment. Include rtl-iter.h. From-SVN: r216637
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Kyrylo Tkachov
Kyrylo Tkachov
parent
1f59b31508
commit
8baff86e56
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@ -1,3 +1,16 @@
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2014-10-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/aarch64/aarch64.h (ADJUST_INSN_LENGTH): Wrap definition in
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do while (0).
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* config/aarch64/aarch64.c (is_mem_p): Delete.
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(is_memory_op): Rename to...
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(has_memory_op): ... This. Use FOR_EACH_SUBRTX.
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(dep_between_memop_and_curr): Assert that the input is a SET.
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(aarch64_madd_needs_nop): Add comment. Do not call
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dep_between_memop_and_curr on NULL body.
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(aarch64_final_prescan_insn): Add comment.
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Include rtl-iter.h.
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2014-10-24 Richard Biener <rguenther@suse.de>
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* Makefile.in (BUILD_CPPLIB): Move $(LIBINTL) $(LIBICONV)
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@ -68,6 +68,7 @@
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#include "aarch64-cost-tables.h"
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#include "dumpfile.h"
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#include "builtins.h"
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#include "rtl-iter.h"
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/* Defined for convenience. */
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#define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
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@ -7658,17 +7659,19 @@ aarch64_mangle_type (const_tree type)
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return NULL;
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}
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static int
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is_mem_p (rtx *x, void *data ATTRIBUTE_UNUSED)
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{
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return MEM_P (*x);
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}
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/* Return true if the rtx_insn contains a MEM RTX somewhere
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in it. */
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static bool
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is_memory_op (rtx_insn *mem_insn)
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has_memory_op (rtx_insn *mem_insn)
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{
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rtx pattern = PATTERN (mem_insn);
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return for_each_rtx (&pattern, is_mem_p, NULL);
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subrtx_iterator::array_type array;
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FOR_EACH_SUBRTX (iter, array, PATTERN (mem_insn), ALL)
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if (MEM_P (*iter))
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return true;
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return false;
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}
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/* Find the first rtx_insn before insn that will generate an assembly
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@ -7718,14 +7721,13 @@ dep_between_memop_and_curr (rtx memop)
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rtx load_reg;
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int opno;
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if (!memop)
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return false;
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gcc_assert (GET_CODE (memop) == SET);
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if (!REG_P (SET_DEST (memop)))
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return false;
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load_reg = SET_DEST (memop);
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for (opno = 0; opno < recog_data.n_operands; opno++)
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for (opno = 1; opno < recog_data.n_operands; opno++)
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{
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rtx operand = recog_data.operand[opno];
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if (REG_P (operand)
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@ -7736,6 +7738,12 @@ dep_between_memop_and_curr (rtx memop)
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return false;
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}
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/* When working around the Cortex-A53 erratum 835769,
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given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
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instruction and has a preceding memory instruction such that a NOP
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should be inserted between them. */
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bool
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aarch64_madd_needs_nop (rtx_insn* insn)
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{
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@ -7754,24 +7762,26 @@ aarch64_madd_needs_nop (rtx_insn* insn)
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return false;
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prev = aarch64_prev_real_insn (insn);
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if (!prev)
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if (!prev || !has_memory_op (prev))
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return false;
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body = single_set (prev);
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/* If the previous insn is a memory op and there is no dependency between
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it and the madd, emit a nop between them. If we know the previous insn is
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a memory op but body is NULL, emit the nop to be safe, it's probably a
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load/store pair insn. */
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if (is_memory_op (prev)
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&& GET_MODE (recog_data.operand[0]) == DImode
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&& (!dep_between_memop_and_curr (body)))
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it and the DImode madd, emit a NOP between them. If body is NULL then we
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have a complex memory operation, probably a load/store pair.
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Be conservative for now and emit a NOP. */
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if (GET_MODE (recog_data.operand[0]) == DImode
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&& (!body || !dep_between_memop_and_curr (body)))
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return true;
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return false;
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}
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/* Implement FINAL_PRESCAN_INSN. */
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void
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aarch64_final_prescan_insn (rtx_insn *insn)
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{
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@ -503,8 +503,11 @@ enum target_cpus
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/* If inserting NOP before a mult-accumulate insn remember to adjust the
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length so that conditional branching code is updated appropriately. */
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#define ADJUST_INSN_LENGTH(insn, length) \
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if (aarch64_madd_needs_nop (insn)) \
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length += 4;
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do \
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{ \
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if (aarch64_madd_needs_nop (insn)) \
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length += 4; \
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} while (0)
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#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
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aarch64_final_prescan_insn (INSN); \
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