diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 279e92e4829..8101d827d5b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2004-06-21 Steven Bosscher + + * config/i386/i386.c: Include insn-codes.h + * config/i386/i386.h (FLAGS_REG, FPSR_REG, DIRFLAG_REG): Don't + define here. + * config/i386/i386.md (BP_REG, SP_REG, FLAGS_REG, FPSR_REG, + DIRFLAG_REG): New define_constants. Use them everywhere. + 2004-06-21 Kaz Kojima * config/sh/t-linux (MULTILIB_OPTIONS): Remove. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 83dcc9e0ee7..8313e0a5f39 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -32,6 +32,7 @@ Boston, MA 02111-1307, USA. */ #include "insn-config.h" #include "conditions.h" #include "output.h" +#include "insn-codes.h" #include "insn-attr.h" #include "flags.h" #include "except.h" diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 61a1f9e1dc4..b49fa7d9e4c 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1163,10 +1163,6 @@ do { \ #define FIRST_STACK_REG FIRST_FLOAT_REG #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) -#define FLAGS_REG 17 -#define FPSR_REG 18 -#define DIRFLAG_REG 19 - #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) #define LAST_SSE_REG (FIRST_SSE_REG + 7) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index bb6aebfb047..54d327e5727 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -153,6 +153,15 @@ (UNSPECV_MWAIT 70) ]) +;; Registers by name. +(define_constants + [(BP_REG 6) + (SP_REG 7) + (FLAGS_REG 17) + (FPSR_REG 18) + (DIRFLAG_REG 19) + ]) + ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls ;; from i386.c. @@ -428,7 +437,7 @@ ;; after the cmp) will actually emit the cmpM. (define_expand "cmpdi" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (compare:CC (match_operand:DI 0 "nonimmediate_operand" "") (match_operand:DI 1 "x86_64_general_operand" "")))] "" @@ -441,7 +450,7 @@ }) (define_expand "cmpsi" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (compare:CC (match_operand:SI 0 "cmpsi_operand" "") (match_operand:SI 1 "general_operand" "")))] "" @@ -454,7 +463,7 @@ }) (define_expand "cmphi" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (compare:CC (match_operand:HI 0 "nonimmediate_operand" "") (match_operand:HI 1 "general_operand" "")))] "" @@ -467,7 +476,7 @@ }) (define_expand "cmpqi" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (compare:CC (match_operand:QI 0 "nonimmediate_operand" "") (match_operand:QI 1 "general_operand" "")))] "TARGET_QIMODE_MATH" @@ -502,7 +511,7 @@ (set_attr "mode" "DI")]) (define_expand "cmpdi_1_rex64" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (compare:CC (match_operand:DI 0 "nonimmediate_operand" "") (match_operand:DI 1 "general_operand" "")))] "TARGET_64BIT" @@ -541,7 +550,7 @@ (set_attr "mode" "SI")]) (define_expand "cmpsi_1" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r") (match_operand:SI 1 "general_operand" "ri,mr")))] "" @@ -665,7 +674,7 @@ (set_attr "mode" "QI")]) (define_expand "cmpqi_ext_3" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (compare:CC (subreg:QI (zero_extract:SI @@ -728,7 +737,7 @@ ;; the old patterns did, but with many more of them. (define_expand "cmpxf" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "") (match_operand:XF 1 "cmp_fp_expander_operand" "")))] "TARGET_80387" @@ -739,7 +748,7 @@ }) (define_expand "cmpdf" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "") (match_operand:DF 1 "cmp_fp_expander_operand" "")))] "TARGET_80387 || TARGET_SSE2" @@ -750,7 +759,7 @@ }) (define_expand "cmpsf" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "") (match_operand:SF 1 "cmp_fp_expander_operand" "")))] "TARGET_80387 || TARGET_SSE" @@ -806,7 +815,7 @@ ;; used to manage the reg stack popping would not be preserved. (define_insn "*cmpfp_2_sf" - [(set (reg:CCFP 18) + [(set (reg:CCFP FPSR_REG) (compare:CCFP (match_operand:SF 0 "register_operand" "f") (match_operand:SF 1 "nonimmediate_operand" "fm")))] @@ -828,7 +837,7 @@ (set_attr "mode" "SF")]) (define_insn "*cmpfp_2_df" - [(set (reg:CCFP 18) + [(set (reg:CCFP FPSR_REG) (compare:CCFP (match_operand:DF 0 "register_operand" "f") (match_operand:DF 1 "nonimmediate_operand" "fm")))] @@ -850,7 +859,7 @@ (set_attr "mode" "DF")]) (define_insn "*cmpfp_2_xf" - [(set (reg:CCFP 18) + [(set (reg:CCFP FPSR_REG) (compare:CCFP (match_operand:XF 0 "register_operand" "f") (match_operand:XF 1 "register_operand" "f")))] @@ -872,7 +881,7 @@ (set_attr "mode" "XF")]) (define_insn "*cmpfp_2u" - [(set (reg:CCFPU 18) + [(set (reg:CCFPU FPSR_REG) (compare:CCFPU (match_operand 0 "register_operand" "f") (match_operand 1 "register_operand" "f")))] @@ -917,7 +926,7 @@ ;; via pushes. (define_insn "*ficom_1" - [(set (reg:CCFP 18) + [(set (reg:CCFP FPSR_REG) (compare:CCFP (match_operand 0 "register_operand" "f,f") (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))] @@ -932,15 +941,15 @@ ;; for separating cc0_setter and cc0_user? (define_split - [(set (reg:CCFP 18) + [(set (reg:CCFP FPSR_REG) (compare:CCFP (match_operand:SF 0 "register_operand" "") (float (match_operand:SI 1 "register_operand" ""))))] "0 && TARGET_80387 && reload_completed" - [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1)) - (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2))) - (parallel [(set (match_dup 1) (mem:SI (reg:SI 7))) - (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] + [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 1)) + (set (reg:CCFP FPSR_REG) (compare:CCFP (match_dup 0) (match_dup 2))) + (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG))) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])] "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx); operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);") @@ -949,7 +958,7 @@ (define_insn "x86_fnstsw_1" [(set (match_operand:HI 0 "register_operand" "=a") - (unspec:HI [(reg:CCFP 18)] UNSPEC_FNSTSW))] + (unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))] "TARGET_80387" "fnstsw\t%0" [(set_attr "length" "2") @@ -960,7 +969,7 @@ ;; Get ax into flags, general case. (define_insn "x86_sahf_1" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))] "!TARGET_64BIT" "sahf" @@ -971,7 +980,7 @@ ;; Pentium Pro can do steps 1 through 3 in one go. (define_insn "*cmpfp_i" - [(set (reg:CCFP 17) + [(set (reg:CCFP FLAGS_REG) (compare:CCFP (match_operand 0 "register_operand" "f") (match_operand 1 "register_operand" "f")))] "TARGET_80387 && TARGET_CMOVE @@ -990,7 +999,7 @@ (set_attr "athlon_decode" "vector")]) (define_insn "*cmpfp_i_sse" - [(set (reg:CCFP 17) + [(set (reg:CCFP FLAGS_REG) (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f") (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))] "TARGET_80387 @@ -1005,7 +1014,7 @@ (set_attr "athlon_decode" "vector")]) (define_insn "*cmpfp_i_sse_only" - [(set (reg:CCFP 17) + [(set (reg:CCFP FLAGS_REG) (compare:CCFP (match_operand 0 "register_operand" "x") (match_operand 1 "nonimmediate_operand" "xm")))] "SSE_FLOAT_MODE_P (GET_MODE (operands[0])) @@ -1019,7 +1028,7 @@ (set_attr "athlon_decode" "vector")]) (define_insn "*cmpfp_iu" - [(set (reg:CCFPU 17) + [(set (reg:CCFPU FLAGS_REG) (compare:CCFPU (match_operand 0 "register_operand" "f") (match_operand 1 "register_operand" "f")))] "TARGET_80387 && TARGET_CMOVE @@ -1038,7 +1047,7 @@ (set_attr "athlon_decode" "vector")]) (define_insn "*cmpfp_iu_sse" - [(set (reg:CCFPU 17) + [(set (reg:CCFPU FLAGS_REG) (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f") (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))] "TARGET_80387 @@ -1053,7 +1062,7 @@ (set_attr "athlon_decode" "vector")]) (define_insn "*cmpfp_iu_sse_only" - [(set (reg:CCFPU 17) + [(set (reg:CCFPU FLAGS_REG) (compare:CCFPU (match_operand 0 "register_operand" "x") (match_operand 1 "nonimmediate_operand" "xm")))] "SSE_FLOAT_MODE_P (GET_MODE (operands[0])) @@ -1113,9 +1122,9 @@ (define_insn "*popsi1_epilogue" [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m") - (mem:SI (reg:SI 7))) - (set (reg:SI 7) - (plus:SI (reg:SI 7) (const_int 4))) + (mem:SI (reg:SI SP_REG))) + (set (reg:SI SP_REG) + (plus:SI (reg:SI SP_REG) (const_int 4))) (clobber (mem:BLK (scratch)))] "!TARGET_64BIT" "pop{l}\t%0" @@ -1124,9 +1133,9 @@ (define_insn "popsi1" [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m") - (mem:SI (reg:SI 7))) - (set (reg:SI 7) - (plus:SI (reg:SI 7) (const_int 4)))] + (mem:SI (reg:SI SP_REG))) + (set (reg:SI SP_REG) + (plus:SI (reg:SI SP_REG) (const_int 4)))] "!TARGET_64BIT" "pop{l}\t%0" [(set_attr "type" "pop") @@ -1135,7 +1144,7 @@ (define_insn "*movsi_xor" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "const0_operand" "i")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && (!TARGET_USE_MOV0 || optimize_size)" "xor{l}\t{%0, %0|%0, %0}" [(set_attr "type" "alu1") @@ -1145,7 +1154,7 @@ (define_insn "*movsi_or" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "immediate_operand" "i")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && operands[1] == constm1_rtx && (TARGET_PENTIUM || optimize_size)" @@ -1432,7 +1441,7 @@ (define_insn "*movstricthi_xor" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) (match_operand:HI 1 "const0_operand" "i")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)" "xor{w}\t{%0, %0|%0, %0}" @@ -1591,7 +1600,7 @@ (define_insn "*movstrictqi_xor" [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q")) (match_operand:QI 1 "const0_operand" "i")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && (!TARGET_USE_MOV0 || optimize_size)" "xor{b}\t{%0, %0|%0, %0}" [(set_attr "type" "alu1") @@ -1873,9 +1882,9 @@ (define_insn "*popdi1_epilogue_rex64" [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m") - (mem:DI (reg:DI 7))) - (set (reg:DI 7) - (plus:DI (reg:DI 7) (const_int 8))) + (mem:DI (reg:DI SP_REG))) + (set (reg:DI SP_REG) + (plus:DI (reg:DI SP_REG) (const_int 8))) (clobber (mem:BLK (scratch)))] "TARGET_64BIT" "pop{q}\t%0" @@ -1884,9 +1893,9 @@ (define_insn "popdi1" [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m") - (mem:DI (reg:DI 7))) - (set (reg:DI 7) - (plus:DI (reg:DI 7) (const_int 8)))] + (mem:DI (reg:DI SP_REG))) + (set (reg:DI SP_REG) + (plus:DI (reg:DI SP_REG) (const_int 8)))] "TARGET_64BIT" "pop{q}\t%0" [(set_attr "type" "pop") @@ -1895,7 +1904,7 @@ (define_insn "*movdi_xor_rex64" [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "const0_operand" "i")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size) && reload_completed" "xor{l}\t{%k0, %k0|%k0, %k0}" @@ -1906,7 +1915,7 @@ (define_insn "*movdi_or_rex64" [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "const_int_operand" "i")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_PENTIUM || optimize_size) && reload_completed && operands[1] == constm1_rtx" @@ -2186,15 +2195,15 @@ [(set (match_operand:SF 0 "push_operand" "") (match_operand:SF 1 "any_fp_register_operand" ""))] "!TARGET_64BIT" - [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4))) - (set (mem:SF (reg:SI 7)) (match_dup 1))]) + [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4))) + (set (mem:SF (reg:SI SP_REG)) (match_dup 1))]) (define_split [(set (match_operand:SF 0 "push_operand" "") (match_operand:SF 1 "any_fp_register_operand" ""))] "TARGET_64BIT" - [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) - (set (mem:SF (reg:DI 7)) (match_dup 1))]) + [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8))) + (set (mem:SF (reg:DI SP_REG)) (match_dup 1))]) (define_insn "*movsf_1" [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y") @@ -2425,16 +2434,16 @@ [(set (match_operand:DF 0 "push_operand" "") (match_operand:DF 1 "any_fp_register_operand" ""))] "!TARGET_64BIT && reload_completed" - [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) - (set (mem:DF (reg:SI 7)) (match_dup 1))] + [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8))) + (set (mem:DF (reg:SI SP_REG)) (match_dup 1))] "") (define_split [(set (match_operand:DF 0 "push_operand" "") (match_operand:DF 1 "any_fp_register_operand" ""))] "TARGET_64BIT && reload_completed" - [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) - (set (mem:DF (reg:DI 7)) (match_dup 1))] + [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8))) + (set (mem:DF (reg:DI SP_REG)) (match_dup 1))] "") (define_split @@ -2729,16 +2738,16 @@ [(set (match_operand:XF 0 "push_operand" "") (match_operand:XF 1 "any_fp_register_operand" ""))] "!TARGET_64BIT" - [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2))) - (set (mem:XF (reg:SI 7)) (match_dup 1))] + [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2))) + (set (mem:XF (reg:SI SP_REG)) (match_dup 1))] "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);") (define_split [(set (match_operand:XF 0 "push_operand" "") (match_operand:XF 1 "any_fp_register_operand" ""))] "TARGET_64BIT" - [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2))) - (set (mem:XF (reg:DI 7)) (match_dup 1))] + [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2))) + (set (mem:XF (reg:DI SP_REG)) (match_dup 1))] "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);") ;; Do not use integer registers when optimizing for size @@ -2889,7 +2898,7 @@ (define_insn "zero_extendhisi2_and" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" "#" [(set_attr "type" "alu1") @@ -2898,10 +2907,10 @@ (define_split [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:HI 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") (define_insn "*zero_extendhisi2_movzwl" @@ -2916,14 +2925,14 @@ [(parallel [(set (match_operand:HI 0 "register_operand" "") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "") (define_insn "*zero_extendqihi2_and" [(set (match_operand:HI 0 "register_operand" "=r,?&q") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" "#" [(set_attr "type" "alu1") @@ -2932,7 +2941,7 @@ (define_insn "*zero_extendqihi2_movzbw_and" [(set (match_operand:HI 0 "register_operand" "=r,r") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size" "#" [(set_attr "type" "imovx,alu1") @@ -2950,7 +2959,7 @@ (define_split [(set (match_operand:HI 0 "register_operand" "") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))" @@ -2962,7 +2971,7 @@ (define_split [(set (match_operand:HI 0 "register_operand" "") (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && ANY_QI_REG_P (operands[0]) && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size) @@ -2975,25 +2984,25 @@ (define_split [(set (match_operand:HI 0 "register_operand" "") (zero_extend:HI (match_operand:QI 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])" [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") (define_expand "zero_extendqisi2" [(parallel [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "") (define_insn "*zero_extendqisi2_and" [(set (match_operand:SI 0 "register_operand" "=r,?&q") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" "#" [(set_attr "type" "alu1") @@ -3002,7 +3011,7 @@ (define_insn "*zero_extendqisi2_movzbw_and" [(set (match_operand:SI 0 "register_operand" "=r,r") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size" "#" [(set_attr "type" "imovx,alu1") @@ -3020,7 +3029,7 @@ (define_split [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))" @@ -3032,7 +3041,7 @@ (define_split [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && ANY_QI_REG_P (operands[0]) && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM) @@ -3046,11 +3055,11 @@ (define_split [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:QI 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])" [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") ;; %%% Kill me once multi-word ops are sane. @@ -3068,7 +3077,7 @@ (define_insn "zero_extendsidi2_32" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,m,m"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && !TARGET_INTER_UNIT_MOVES" "@ # @@ -3082,7 +3091,7 @@ (define_insn "*zero_extendsidi2_32_1" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,rm,rm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES" "@ # @@ -3127,7 +3136,7 @@ (define_split [(set (match_operand:DI 0 "register_operand" "") (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])" [(set (match_dup 4) (const_int 0))] @@ -3136,7 +3145,7 @@ (define_split [(set (match_operand:DI 0 "nonimmediate_operand" "") (zero_extend:DI (match_operand:SI 1 "general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && reload_completed && !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])" [(set (match_dup 3) (match_dup 1)) @@ -3168,7 +3177,7 @@ (define_expand "extendsidi2" [(parallel [(set (match_operand:DI 0 "register_operand" "") (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) - (clobber (reg:CC 17)) + (clobber (reg:CC FLAGS_REG)) (clobber (match_scratch:SI 2 ""))])] "" { @@ -3182,7 +3191,7 @@ (define_insn "*extendsidi2_1" [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o") (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r"))) - (clobber (reg:CC 17)) + (clobber (reg:CC FLAGS_REG)) (clobber (match_scratch:SI 2 "=X,X,X,&r"))] "!TARGET_64BIT" "#") @@ -3219,14 +3228,14 @@ (define_split [(set (match_operand:DI 0 "memory_operand" "") (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) - (clobber (reg:CC 17)) + (clobber (reg:CC FLAGS_REG)) (clobber (match_operand:SI 2 "register_operand" ""))] "(reload_completed && dead_or_set_p (insn, operands[1]) && !reg_mentioned_p (operands[1], operands[0]))" [(set (match_dup 3) (match_dup 1)) (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31))) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (set (match_dup 4) (match_dup 1))] "split_di (&operands[0], 1, &operands[3], &operands[4]);") @@ -3234,7 +3243,7 @@ (define_split [(set (match_operand:DI 0 "memory_operand" "") (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) - (clobber (reg:CC 17)) + (clobber (reg:CC FLAGS_REG)) (clobber (match_operand:SI 2 "register_operand" ""))] "reload_completed" [(const_int 0)] @@ -3264,7 +3273,7 @@ (define_split [(set (match_operand:DI 0 "register_operand" "") (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) - (clobber (reg:CC 17)) + (clobber (reg:CC FLAGS_REG)) (clobber (match_scratch:SI 2 ""))] "reload_completed" [(const_int 0)] @@ -3401,15 +3410,15 @@ [(set (match_operand:DF 0 "push_operand" "") (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))] "!TARGET_64BIT" - [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) - (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))]) + [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8))) + (set (mem:DF (reg:SI SP_REG)) (float_extend:DF (match_dup 1)))]) (define_split [(set (match_operand:DF 0 "push_operand" "") (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))] "TARGET_64BIT" - [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) - (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))]) + [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8))) + (set (mem:DF (reg:DI SP_REG)) (float_extend:DF (match_dup 1)))]) (define_insn "*dummy_extendsfxf2" [(set (match_operand:XF 0 "push_operand" "=<") @@ -3421,32 +3430,32 @@ [(set (match_operand:XF 0 "push_operand" "") (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))] "" - [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2))) - (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))] + [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2))) + (set (mem:XF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))] "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);") (define_split [(set (match_operand:XF 0 "push_operand" "") (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))] "TARGET_64BIT" - [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2))) - (set (mem:DF (reg:DI 7)) (float_extend:XF (match_dup 1)))] + [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2))) + (set (mem:DF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))] "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);") (define_split [(set (match_operand:XF 0 "push_operand" "") (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))] "" - [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 2))) - (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))] + [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2))) + (set (mem:DF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))] "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);") (define_split [(set (match_operand:XF 0 "push_operand" "") (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))] "TARGET_64BIT" - [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 2))) - (set (mem:XF (reg:DI 7)) (float_extend:XF (match_dup 1)))] + [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2))) + (set (mem:XF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))] "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);") (define_expand "extendsfdf2" @@ -4009,14 +4018,14 @@ (define_expand "fix_truncxfdi2" [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") (fix:DI (match_operand:XF 1 "register_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387" "") (define_expand "fix_truncdfdi2" [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") (fix:DI (match_operand:DF 1 "register_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)" { if (TARGET_64BIT && TARGET_SSE2) @@ -4032,7 +4041,7 @@ (define_expand "fix_truncsfdi2" [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") (fix:DI (match_operand:SF 1 "register_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)" { if (TARGET_SSE && TARGET_64BIT) @@ -4050,7 +4059,7 @@ (define_insn_and_split "*fix_truncdi_1" [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r") (fix:DI (match_operand 1 "register_operand" "f,f"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) && !reload_completed && !reload_in_progress && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)" @@ -4174,14 +4183,14 @@ (define_expand "fix_truncxfsi2" [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") (fix:SI (match_operand:XF 1 "register_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387" "") (define_expand "fix_truncdfsi2" [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") (fix:SI (match_operand:DF 1 "register_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387 || TARGET_SSE2" { if (TARGET_SSE2) @@ -4197,7 +4206,7 @@ (define_expand "fix_truncsfsi2" [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") (fix:SI (match_operand:SF 1 "register_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387 || TARGET_SSE" { if (TARGET_SSE) @@ -4215,7 +4224,7 @@ (define_insn_and_split "*fix_truncsi_1" [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r") (fix:SI (match_operand 1 "register_operand" "f,f"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) && !reload_completed && !reload_in_progress && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" @@ -4333,21 +4342,21 @@ (define_expand "fix_truncxfhi2" [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") (fix:HI (match_operand:XF 1 "register_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387" "") (define_expand "fix_truncdfhi2" [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") (fix:HI (match_operand:DF 1 "register_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387 && !TARGET_SSE2" "") (define_expand "fix_truncsfhi2" [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") (fix:HI (match_operand:SF 1 "register_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387 && !TARGET_SSE" "") @@ -4356,7 +4365,7 @@ (define_insn_and_split "*fix_trunchi_1" [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r") (fix:HI (match_operand 1 "register_operand" "f,f"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) && !reload_completed && !reload_in_progress && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))" @@ -4434,7 +4443,7 @@ ;; %% Not used yet. (define_insn "x86_fnstcw_1" [(set (match_operand:HI 0 "memory_operand" "=m") - (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))] + (unspec:HI [(reg:HI FPSR_REG)] UNSPEC_FSTCW))] "TARGET_80387" "fnstcw\t%0" [(set_attr "length" "2") @@ -4442,7 +4451,7 @@ (set_attr "unit" "i387")]) (define_insn "x86_fldcw_1" - [(set (reg:HI 18) + [(set (reg:HI FPSR_REG) (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))] "TARGET_80387" "fldcw\t%0" @@ -4919,7 +4928,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "x86_64_general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;") @@ -4927,7 +4936,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "roiF,riF"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" "#") @@ -4935,16 +4944,16 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && reload_completed" - [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] + [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)] UNSPEC_ADD_CARRY)) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]) (parallel [(set (match_dup 3) - (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) + (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0)) (match_dup 4)) (match_dup 5))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "split_di (operands+0, 1, operands+0, operands+3); split_di (operands+1, 1, operands+1, operands+4); split_di (operands+2, 1, operands+2, operands+5);") @@ -4954,7 +4963,7 @@ (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "") (match_operand:DI 1 "nonimmediate_operand" "%0,0")) (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" "adc{q}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -4962,7 +4971,7 @@ (set_attr "mode" "DI")]) (define_insn "*adddi3_cc_rex64" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "x86_64_general_operand" "re,rm")] UNSPEC_ADD_CARRY)) @@ -4978,7 +4987,7 @@ (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "") (match_operand:QI 1 "nonimmediate_operand" "%0,0")) (match_operand:QI 2 "general_operand" "qi,qm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (PLUS, QImode, operands)" "adc{b}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -4990,7 +4999,7 @@ (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "") (match_operand:HI 1 "nonimmediate_operand" "%0,0")) (match_operand:HI 2 "general_operand" "ri,rm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (PLUS, HImode, operands)" "adc{w}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -5002,7 +5011,7 @@ (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "") (match_operand:SI 1 "nonimmediate_operand" "%0,0")) (match_operand:SI 2 "general_operand" "ri,rm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (PLUS, SImode, operands)" "adc{l}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -5015,7 +5024,7 @@ (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "") (match_operand:SI 1 "nonimmediate_operand" "%0")) (match_operand:SI 2 "general_operand" "rim")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" "adc{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") @@ -5023,7 +5032,7 @@ (set_attr "mode" "SI")]) (define_insn "*addsi3_cc" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0") (match_operand:SI 2 "general_operand" "ri,rm")] UNSPEC_ADD_CARRY)) @@ -5035,7 +5044,7 @@ (set_attr "mode" "SI")]) (define_insn "addqi3_cc" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0") (match_operand:QI 2 "general_operand" "qi,qm")] UNSPEC_ADD_CARRY)) @@ -5050,7 +5059,7 @@ [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:SI 2 "general_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;") @@ -5251,7 +5260,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r") (match_operand:DI 2 "x86_64_general_operand" "rme,re,re"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" { switch (get_attr_type (insn)) @@ -5307,7 +5316,7 @@ [(set (match_operand:DI 0 "register_operand" "") (plus:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "x86_64_nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && reload_completed && true_regnum (operands[0]) != true_regnum (operands[1])" [(set (match_dup 0) @@ -5519,7 +5528,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r") (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r") (match_operand:SI 2 "general_operand" "rmni,rni,rni"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (PLUS, SImode, operands)" { switch (get_attr_type (insn)) @@ -5573,7 +5582,7 @@ [(set (match_operand 0 "register_operand" "") (plus (match_operand 1 "register_operand" "") (match_operand 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && true_regnum (operands[0]) != true_regnum (operands[1])" [(const_int 0)] @@ -5604,7 +5613,7 @@ (zero_extend:DI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r") (match_operand:SI 2 "general_operand" "rmni,rni")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" { switch (get_attr_type (insn)) @@ -5654,7 +5663,7 @@ (zero_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "nonmemory_operand" "")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && reload_completed && true_regnum (operands[0]) != true_regnum (operands[1])" [(set (match_dup 0) @@ -5941,7 +5950,7 @@ [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") (plus:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:HI 2 "general_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_HIMODE_MATH" "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;") @@ -5953,7 +5962,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r") (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r") (match_operand:HI 2 "general_operand" "ri,rm,rni"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_PARTIAL_REG_STALL && ix86_binary_operator_ok (PLUS, HImode, operands)" { @@ -5994,7 +6003,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") (match_operand:HI 2 "general_operand" "ri,rm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_PARTIAL_REG_STALL && ix86_binary_operator_ok (PLUS, HImode, operands)" { @@ -6186,7 +6195,7 @@ [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "") (plus:QI (match_operand:QI 1 "nonimmediate_operand" "") (match_operand:QI 2 "general_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH" "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;") @@ -6195,7 +6204,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r") (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r") (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_PARTIAL_REG_STALL && ix86_binary_operator_ok (PLUS, QImode, operands)" { @@ -6243,7 +6252,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r") (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") (match_operand:QI 2 "general_operand" "qn,qmn,rn"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_PARTIAL_REG_STALL && ix86_binary_operator_ok (PLUS, QImode, operands)" { @@ -6287,7 +6296,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) (plus:QI (match_dup 0) (match_operand:QI 1 "general_operand" "qn,qnm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { @@ -6480,7 +6489,7 @@ (const_int 8) (const_int 8)) (match_operand:QI 2 "general_operand" "Qmn"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT" { switch (get_attr_type (insn)) @@ -6514,7 +6523,7 @@ (const_int 8) (const_int 8)) (match_operand:QI 2 "nonmemory_operand" "Qn"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" { switch (get_attr_type (insn)) @@ -6551,7 +6560,7 @@ (match_operand 2 "ext_register_operand" "Q") (const_int 8) (const_int 8)))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "add{b}\t{%h2, %h0|%h0, %h2}" [(set_attr "type" "alu") @@ -6588,7 +6597,7 @@ [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") (minus:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "x86_64_general_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;") @@ -6596,7 +6605,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") (match_operand:DI 2 "general_operand" "roiF,riF"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)" "#") @@ -6604,15 +6613,15 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "") (minus:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && reload_completed" - [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2))) + [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2))) (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) (parallel [(set (match_dup 3) (minus:SI (match_dup 4) - (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) + (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0)) (match_dup 5)))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "split_di (operands+0, 1, operands+0, operands+3); split_di (operands+1, 1, operands+1, operands+4); split_di (operands+2, 1, operands+2, operands+5);") @@ -6622,7 +6631,7 @@ (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "") (match_operand:DI 2 "x86_64_general_operand" "re,rm")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)" "sbb{q}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -6633,7 +6642,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)" "sub{q}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -6670,7 +6679,7 @@ (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "") (match_operand:QI 2 "general_operand" "qi,qm")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (MINUS, QImode, operands)" "sbb{b}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -6682,7 +6691,7 @@ (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "") (match_operand:HI 2 "general_operand" "ri,rm")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (MINUS, HImode, operands)" "sbb{w}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -6694,7 +6703,7 @@ (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "") (match_operand:SI 2 "general_operand" "ri,rm")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (MINUS, SImode, operands)" "sbb{l}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -6707,7 +6716,7 @@ (minus:SI (match_operand:SI 1 "register_operand" "0,0") (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "") (match_operand:SI 2 "general_operand" "ri,rm"))))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)" "sbb{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") @@ -6718,7 +6727,7 @@ [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") (minus:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:SI 2 "general_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;") @@ -6726,7 +6735,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") (match_operand:SI 2 "general_operand" "ri,rm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (MINUS, SImode, operands)" "sub{l}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -6737,7 +6746,7 @@ (zero_extend:DI (minus:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "rim")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)" "sub{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") @@ -6803,7 +6812,7 @@ [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") (minus:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:HI 2 "general_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_HIMODE_MATH" "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;") @@ -6811,7 +6820,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") (match_operand:HI 2 "general_operand" "ri,rm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (MINUS, HImode, operands)" "sub{w}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -6847,7 +6856,7 @@ [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "") (minus:QI (match_operand:QI 1 "nonimmediate_operand" "") (match_operand:QI 2 "general_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH" "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;") @@ -6855,7 +6864,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q") (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "general_operand" "qn,qmn"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (MINUS, QImode, operands)" "sub{b}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -6865,7 +6874,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) (minus:QI (match_dup 0) (match_operand:QI 1 "general_operand" "qn,qmn"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "sub{b}\t{%1, %0|%0, %1}" @@ -6927,7 +6936,7 @@ [(parallel [(set (match_operand:DI 0 "register_operand" "") (mult:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "x86_64_general_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT" "") @@ -6935,7 +6944,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r,r") (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0") (match_operand:DI 2 "x86_64_general_operand" "K,e,mr"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "@ @@ -6959,7 +6968,7 @@ [(parallel [(set (match_operand:SI 0 "register_operand" "") (mult:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "general_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "") @@ -6967,7 +6976,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r,r") (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0") (match_operand:SI 2 "general_operand" "K,i,mr"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" "@ imul{l}\t{%2, %1, %0|%0, %1, %2} @@ -6991,7 +7000,7 @@ (zero_extend:DI (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0") (match_operand:SI 2 "general_operand" "K,i,mr")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "@ @@ -7015,7 +7024,7 @@ [(parallel [(set (match_operand:HI 0 "register_operand" "") (mult:HI (match_operand:HI 1 "register_operand" "") (match_operand:HI 2 "general_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_HIMODE_MATH" "") @@ -7023,7 +7032,7 @@ [(set (match_operand:HI 0 "register_operand" "=r,r,r") (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0") (match_operand:HI 2 "general_operand" "K,i,mr"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" "@ imul{w}\t{%2, %1, %0|%0, %1, %2} @@ -7043,7 +7052,7 @@ [(parallel [(set (match_operand:QI 0 "register_operand" "") (mult:QI (match_operand:QI 1 "nonimmediate_operand" "") (match_operand:QI 2 "register_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH" "") @@ -7051,7 +7060,7 @@ [(set (match_operand:QI 0 "register_operand" "=a") (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0") (match_operand:QI 2 "nonimmediate_operand" "qm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_QIMODE_MATH && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{b}\t%2" @@ -7069,7 +7078,7 @@ (match_operand:QI 1 "nonimmediate_operand" "")) (zero_extend:HI (match_operand:QI 2 "register_operand" "")))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH" "") @@ -7077,7 +7086,7 @@ [(set (match_operand:HI 0 "register_operand" "=a") (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_QIMODE_MATH && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{b}\t%2" @@ -7093,7 +7102,7 @@ [(parallel [(set (match_operand:HI 0 "register_operand" "") (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")) (sign_extend:HI (match_operand:QI 2 "register_operand" "")))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH" "") @@ -7101,7 +7110,7 @@ [(set (match_operand:HI 0 "register_operand" "=a") (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_QIMODE_MATH && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{b}\t%2" @@ -7119,7 +7128,7 @@ (match_operand:DI 1 "nonimmediate_operand" "")) (zero_extend:TI (match_operand:DI 2 "register_operand" "")))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT" "") @@ -7127,7 +7136,7 @@ [(set (match_operand:TI 0 "register_operand" "=A") (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0")) (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{q}\t%2" @@ -7146,7 +7155,7 @@ (match_operand:SI 1 "nonimmediate_operand" "")) (zero_extend:DI (match_operand:SI 2 "register_operand" "")))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "!TARGET_64BIT" "") @@ -7154,7 +7163,7 @@ [(set (match_operand:DI 0 "register_operand" "=A") (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0")) (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{l}\t%2" @@ -7172,7 +7181,7 @@ (match_operand:DI 1 "nonimmediate_operand" "")) (sign_extend:TI (match_operand:DI 2 "register_operand" "")))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT" "") @@ -7180,7 +7189,7 @@ [(set (match_operand:TI 0 "register_operand" "=A") (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0")) (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{q}\t%2" @@ -7198,7 +7207,7 @@ (match_operand:SI 1 "nonimmediate_operand" "")) (sign_extend:DI (match_operand:SI 2 "register_operand" "")))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "!TARGET_64BIT" "") @@ -7206,7 +7215,7 @@ [(set (match_operand:DI 0 "register_operand" "=A") (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0")) (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{l}\t%2" @@ -7228,7 +7237,7 @@ (match_operand:DI 2 "register_operand" ""))) (const_int 64)))) (clobber (match_scratch:DI 3 "")) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT" "") @@ -7242,7 +7251,7 @@ (match_operand:DI 2 "nonimmediate_operand" "rm"))) (const_int 64)))) (clobber (match_scratch:DI 3 "=1")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{q}\t%2" @@ -7264,7 +7273,7 @@ (match_operand:SI 2 "register_operand" ""))) (const_int 32)))) (clobber (match_scratch:SI 3 "")) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "") @@ -7278,7 +7287,7 @@ (match_operand:SI 2 "nonimmediate_operand" "rm"))) (const_int 32)))) (clobber (match_scratch:SI 3 "=1")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" "mul{l}\t%2" [(set_attr "type" "imul") @@ -7299,7 +7308,7 @@ (match_operand:SI 2 "nonimmediate_operand" "rm"))) (const_int 32))))) (clobber (match_scratch:SI 3 "=1")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{l}\t%2" @@ -7321,7 +7330,7 @@ (match_operand:DI 2 "register_operand" ""))) (const_int 64)))) (clobber (match_scratch:DI 3 "")) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT" "") @@ -7335,7 +7344,7 @@ (match_operand:DI 2 "nonimmediate_operand" "rm"))) (const_int 64)))) (clobber (match_scratch:DI 3 "=1")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{q}\t%2" @@ -7356,7 +7365,7 @@ (match_operand:SI 2 "register_operand" ""))) (const_int 32)))) (clobber (match_scratch:SI 3 "")) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "") @@ -7370,7 +7379,7 @@ (match_operand:SI 2 "nonimmediate_operand" "rm"))) (const_int 32)))) (clobber (match_scratch:SI 3 "=1")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" "imul{l}\t%2" [(set_attr "type" "imul") @@ -7390,7 +7399,7 @@ (match_operand:SI 2 "nonimmediate_operand" "rm"))) (const_int 32))))) (clobber (match_scratch:SI 3 "=1")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{l}\t%2" @@ -7430,7 +7439,7 @@ [(set (match_operand:QI 0 "register_operand" "=a") (div:QI (match_operand:HI 1 "register_operand" "0") (match_operand:QI 2 "nonimmediate_operand" "qm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_QIMODE_MATH" "idiv{b}\t%2" [(set_attr "type" "idiv") @@ -7440,7 +7449,7 @@ [(set (match_operand:QI 0 "register_operand" "=a") (udiv:QI (match_operand:HI 1 "register_operand" "0") (match_operand:QI 2 "nonimmediate_operand" "qm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_QIMODE_MATH" "div{b}\t%2" [(set_attr "type" "idiv") @@ -7477,7 +7486,7 @@ (match_operand:DI 2 "nonimmediate_operand" ""))) (set (match_operand:DI 3 "register_operand" "") (mod:DI (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT" "") @@ -7490,7 +7499,7 @@ (match_operand:DI 3 "nonimmediate_operand" "rm,rm"))) (set (match_operand:DI 1 "register_operand" "=&d,&d") (mod:DI (match_dup 2) (match_dup 3))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD" "#" [(set_attr "type" "multi")]) @@ -7501,7 +7510,7 @@ (match_operand:DI 3 "nonimmediate_operand" "rm"))) (set (match_operand:DI 1 "register_operand" "=&d") (mod:DI (match_dup 2) (match_dup 3))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)" "#" [(set_attr "type" "multi")]) @@ -7513,7 +7522,7 @@ (set (match_operand:DI 3 "register_operand" "=d") (mod:DI (match_dup 1) (match_dup 2))) (use (match_operand:DI 4 "register_operand" "3")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "idiv{q}\t%2" [(set_attr "type" "idiv") @@ -7525,17 +7534,17 @@ (match_operand:DI 2 "nonimmediate_operand" ""))) (set (match_operand:DI 3 "register_operand" "") (mod:DI (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && reload_completed" [(parallel [(set (match_dup 3) (ashiftrt:DI (match_dup 4) (const_int 63))) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (parallel [(set (match_dup 0) (div:DI (reg:DI 0) (match_dup 2))) (set (match_dup 3) (mod:DI (reg:DI 0) (match_dup 2))) (use (match_dup 3)) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] { /* Avoid use of cltd in favor of a mov+shift. */ if (!TARGET_USE_CLTD && !optimize_size) @@ -7561,7 +7570,7 @@ (match_operand:SI 2 "nonimmediate_operand" ""))) (set (match_operand:SI 3 "register_operand" "") (mod:SI (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "") @@ -7574,7 +7583,7 @@ (match_operand:SI 3 "nonimmediate_operand" "rm,rm"))) (set (match_operand:SI 1 "register_operand" "=&d,&d") (mod:SI (match_dup 2) (match_dup 3))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!optimize_size && !TARGET_USE_CLTD" "#" [(set_attr "type" "multi")]) @@ -7585,7 +7594,7 @@ (match_operand:SI 3 "nonimmediate_operand" "rm"))) (set (match_operand:SI 1 "register_operand" "=&d") (mod:SI (match_dup 2) (match_dup 3))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "optimize_size || TARGET_USE_CLTD" "#" [(set_attr "type" "multi")]) @@ -7597,7 +7606,7 @@ (set (match_operand:SI 3 "register_operand" "=d") (mod:SI (match_dup 1) (match_dup 2))) (use (match_operand:SI 4 "register_operand" "3")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "idiv{l}\t%2" [(set_attr "type" "idiv") @@ -7609,17 +7618,17 @@ (match_operand:SI 2 "nonimmediate_operand" ""))) (set (match_operand:SI 3 "register_operand" "") (mod:SI (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed" [(parallel [(set (match_dup 3) (ashiftrt:SI (match_dup 4) (const_int 31))) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (parallel [(set (match_dup 0) (div:SI (reg:SI 0) (match_dup 2))) (set (match_dup 3) (mod:SI (reg:SI 0) (match_dup 2))) (use (match_dup 3)) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] { /* Avoid use of cltd in favor of a mov+shift. */ if (!TARGET_USE_CLTD && !optimize_size) @@ -7644,7 +7653,7 @@ (match_operand:HI 2 "nonimmediate_operand" "rm"))) (set (match_operand:HI 3 "register_operand" "=&d") (mod:HI (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_HIMODE_MATH" "cwtd\;idiv{w}\t%2" [(set_attr "type" "multi") @@ -7657,7 +7666,7 @@ (match_operand:DI 2 "nonimmediate_operand" "rm"))) (set (match_operand:DI 3 "register_operand" "=&d") (umod:DI (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "xor{q}\t%3, %3\;div{q}\t%2" [(set_attr "type" "multi") @@ -7671,7 +7680,7 @@ (set (match_operand:DI 3 "register_operand" "=d") (umod:DI (match_dup 1) (match_dup 2))) (use (match_dup 3)) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "div{q}\t%2" [(set_attr "type" "idiv") @@ -7683,7 +7692,7 @@ (match_operand:DI 2 "nonimmediate_operand" ""))) (set (match_operand:DI 3 "register_operand" "") (umod:DI (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && reload_completed" [(set (match_dup 3) (const_int 0)) (parallel [(set (match_dup 0) @@ -7691,7 +7700,7 @@ (set (match_dup 3) (umod:DI (match_dup 1) (match_dup 2))) (use (match_dup 3)) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") (define_insn "udivmodsi4" @@ -7700,7 +7709,7 @@ (match_operand:SI 2 "nonimmediate_operand" "rm"))) (set (match_operand:SI 3 "register_operand" "=&d") (umod:SI (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "xor{l}\t%3, %3\;div{l}\t%2" [(set_attr "type" "multi") @@ -7714,7 +7723,7 @@ (set (match_operand:SI 3 "register_operand" "=d") (umod:SI (match_dup 1) (match_dup 2))) (use (match_dup 3)) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "div{l}\t%2" [(set_attr "type" "idiv") @@ -7726,7 +7735,7 @@ (match_operand:SI 2 "nonimmediate_operand" ""))) (set (match_operand:SI 3 "register_operand" "") (umod:SI (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed" [(set (match_dup 3) (const_int 0)) (parallel [(set (match_dup 0) @@ -7734,7 +7743,7 @@ (set (match_dup 3) (umod:SI (match_dup 1) (match_dup 2))) (use (match_dup 3)) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") (define_expand "udivmodhi4" @@ -7745,7 +7754,7 @@ (set (match_operand:HI 3 "register_operand" "") (umod:HI (match_dup 1) (match_dup 2))) (use (match_dup 4)) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_HIMODE_MATH" "operands[4] = gen_reg_rtx (HImode);") @@ -7756,7 +7765,7 @@ (set (match_operand:HI 3 "register_operand" "=d") (umod:HI (match_dup 1) (match_dup 2))) (use (match_operand:HI 4 "register_operand" "3")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "div{w}\t%2" [(set_attr "type" "idiv") @@ -7776,7 +7785,7 @@ ; (set (match_operand:SI 3 "register_operand" "=d") ; (truncate:SI ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2))))) -; (clobber (reg:CC 17))] +; (clobber (reg:CC FLAGS_REG))] ; "" ; "div{l}\t{%2, %0|%0, %2}" ; [(set_attr "type" "idiv")]) @@ -7820,7 +7829,7 @@ (set_attr "pent_pair" "uv,np,uv")]) (define_expand "testsi_ccno_1" - [(set (reg:CCNO 17) + [(set (reg:CCNO FLAGS_REG) (compare:CCNO (and:SI (match_operand:SI 0 "nonimmediate_operand" "") (match_operand:SI 1 "nonmemory_operand" "")) @@ -7842,7 +7851,7 @@ (set_attr "pent_pair" "uv,np,uv")]) (define_expand "testqi_ccz_1" - [(set (reg:CCZ 17) + [(set (reg:CCZ FLAGS_REG) (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "") (match_operand:QI 1 "nonmemory_operand" "")) (const_int 0)))] @@ -7872,7 +7881,7 @@ (set_attr "pent_pair" "uv,np,uv,np")]) (define_expand "testqi_ext_ccno_0" - [(set (reg:CCNO 17) + [(set (reg:CCNO FLAGS_REG) (compare:CCNO (and:SI (zero_extract:SI @@ -7996,7 +8005,7 @@ (match_operand 2 "const_int_operand" "")) (const_int 0)))] "ix86_match_ccmode (insn, CCNOmode)" - [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))] + [(set (reg:CCNO FLAGS_REG) (compare:CCNO (match_dup 3) (const_int 0)))] { HOST_WIDE_INT len = INTVAL (operands[1]); HOST_WIDE_INT pos = INTVAL (operands[2]); @@ -8054,7 +8063,7 @@ || (ix86_match_ccmode (insn, CCNOmode) && !(INTVAL (operands[1]) & ~(127 << 8)))) && GET_MODE (operands[0]) != QImode" - [(set (reg:CCNO 17) + [(set (reg:CCNO FLAGS_REG) (compare:CCNO (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8)) (match_dup 1)) @@ -8075,7 +8084,7 @@ || (ix86_match_ccmode (insn, CCNOmode) && !(INTVAL (operands[1]) & ~127))) && GET_MODE (operands[0]) != QImode" - [(set (reg:CCNO 17) + [(set (reg:CCNO FLAGS_REG) (compare:CCNO (and:QI (match_dup 0) (match_dup 1)) @@ -8092,7 +8101,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "") (and:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "x86_64_szext_general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "ix86_expand_binary_operator (AND, DImode, operands); DONE;") @@ -8100,7 +8109,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r") (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm") (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)" { switch (get_attr_type (insn)) @@ -8158,7 +8167,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "") (and:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:SI 2 "general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "ix86_expand_binary_operator (AND, SImode, operands); DONE;") @@ -8166,7 +8175,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r") (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm") (match_operand:SI 2 "general_operand" "ri,rm,L"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (AND, SImode, operands)" { switch (get_attr_type (insn)) @@ -8205,7 +8214,7 @@ [(set (match_operand 0 "register_operand" "") (and (match_dup 0) (const_int -65536))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)" [(set (strict_low_part (match_dup 1)) (const_int 0))] "operands[1] = gen_lowpart (HImode, operands[0]);") @@ -8214,7 +8223,7 @@ [(set (match_operand 0 "ext_register_operand" "") (and (match_dup 0) (const_int -256))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed" [(set (strict_low_part (match_dup 1)) (const_int 0))] "operands[1] = gen_lowpart (QImode, operands[0]);") @@ -8223,7 +8232,7 @@ [(set (match_operand 0 "ext_register_operand" "") (and (match_dup 0) (const_int -65281))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed" [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) @@ -8235,7 +8244,7 @@ (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8)))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[0] = gen_lowpart (SImode, operands[0]);") ;; See comment for addsi_1_zext why we do use nonimmediate_operand @@ -8244,7 +8253,7 @@ (zero_extend:DI (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0") (match_operand:SI 2 "general_operand" "rim")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)" "and{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") @@ -8281,7 +8290,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "") (and:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:HI 2 "general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_HIMODE_MATH" "ix86_expand_binary_operator (AND, HImode, operands); DONE;") @@ -8289,7 +8298,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r") (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm") (match_operand:HI 2 "general_operand" "ri,rm,L"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (AND, HImode, operands)" { switch (get_attr_type (insn)) @@ -8329,7 +8338,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "") (and:QI (match_operand:QI 1 "nonimmediate_operand" "") (match_operand:QI 2 "general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_QIMODE_MATH" "ix86_expand_binary_operator (AND, QImode, operands); DONE;") @@ -8338,7 +8347,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r") (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") (match_operand:QI 2 "general_operand" "qi,qmi,ri"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (AND, QImode, operands)" "@ and{b}\t{%2, %0|%0, %2} @@ -8351,7 +8360,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) (and:QI (match_dup 0) (match_operand:QI 1 "general_operand" "qi,qmi"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "and{b}\t{%1, %0|%0, %1}" @@ -8410,7 +8419,7 @@ (const_int 8) (const_int 8)) (match_operand 2 "const_int_operand" "n"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "and{b}\t{%2, %h0|%h0, %2}" [(set_attr "type" "alu") @@ -8456,7 +8465,7 @@ (const_int 8)) (zero_extend:SI (match_operand:QI 2 "general_operand" "Qm")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT" "and{b}\t{%2, %h0|%h0, %2}" [(set_attr "type" "alu") @@ -8474,7 +8483,7 @@ (const_int 8)) (zero_extend:SI (match_operand 2 "ext_register_operand" "Q")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "and{b}\t{%2, %h0|%h0, %2}" [(set_attr "type" "alu") @@ -8494,7 +8503,7 @@ (match_operand 2 "ext_register_operand" "Q") (const_int 8) (const_int 8)))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "and{b}\t{%h2, %h0|%h0, %h2}" [(set_attr "type" "alu") @@ -8510,7 +8519,7 @@ [(set (match_operand 0 "register_operand" "") (and (match_operand 1 "register_operand" "") (match_operand 2 "const_int_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && QI_REG_P (operands[0]) && (!TARGET_PARTIAL_REG_STALL || optimize_size) @@ -8520,7 +8529,7 @@ (and:SI (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8)) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[0] = gen_lowpart (SImode, operands[0]); operands[1] = gen_lowpart (SImode, operands[1]); operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);") @@ -8531,7 +8540,7 @@ [(set (match_operand 0 "register_operand" "") (and (match_operand 1 "general_operand" "") (match_operand 2 "const_int_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && ANY_QI_REG_P (operands[0]) && (!TARGET_PARTIAL_REG_STALL || optimize_size) @@ -8541,7 +8550,7 @@ [(parallel [(set (strict_low_part (match_dup 0)) (and:QI (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[0] = gen_lowpart (QImode, operands[0]); operands[1] = gen_lowpart (QImode, operands[1]); operands[2] = gen_lowpart (QImode, operands[2]);") @@ -8555,7 +8564,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "") (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "x86_64_general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "ix86_expand_binary_operator (IOR, DImode, operands); DONE;") @@ -8563,7 +8572,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "x86_64_general_operand" "re,rme"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (IOR, DImode, operands)" "or{q}\t{%2, %0|%0, %2}" @@ -8602,7 +8611,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "") (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:SI 2 "general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "ix86_expand_binary_operator (IOR, SImode, operands); DONE;") @@ -8610,7 +8619,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (match_operand:SI 2 "general_operand" "ri,rmi"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (IOR, SImode, operands)" "or{l}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -8622,7 +8631,7 @@ (zero_extend:DI (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") (match_operand:SI 2 "general_operand" "rim")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)" "or{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") @@ -8632,7 +8641,7 @@ [(set (match_operand:DI 0 "register_operand" "=rm") (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "or{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") @@ -8695,7 +8704,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "") (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:HI 2 "general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_HIMODE_MATH" "ix86_expand_binary_operator (IOR, HImode, operands); DONE;") @@ -8703,7 +8712,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m") (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") (match_operand:HI 2 "general_operand" "rmi,ri"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (IOR, HImode, operands)" "or{w}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -8738,7 +8747,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "") (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") (match_operand:QI 2 "general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_QIMODE_MATH" "ix86_expand_binary_operator (IOR, QImode, operands); DONE;") @@ -8747,7 +8756,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r") (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") (match_operand:QI 2 "general_operand" "qmi,qi,ri"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (IOR, QImode, operands)" "@ or{b}\t{%2, %0|%0, %2} @@ -8760,7 +8769,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m")) (ior:QI (match_dup 0) (match_operand:QI 1 "general_operand" "qmi,qi"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "or{b}\t{%1, %0|%0, %1}" @@ -8816,7 +8825,7 @@ (const_int 8) (const_int 8)) (match_operand 2 "const_int_operand" "n"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(!TARGET_PARTIAL_REG_STALL || optimize_size)" "or{b}\t{%2, %h0|%h0, %2}" [(set_attr "type" "alu") @@ -8834,7 +8843,7 @@ (const_int 8)) (zero_extend:SI (match_operand:QI 2 "general_operand" "Qm")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && (!TARGET_PARTIAL_REG_STALL || optimize_size)" "or{b}\t{%2, %h0|%h0, %2}" @@ -8853,7 +8862,7 @@ (const_int 8)) (zero_extend:SI (match_operand 2 "ext_register_operand" "Q")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (!TARGET_PARTIAL_REG_STALL || optimize_size)" "or{b}\t{%2, %h0|%h0, %2}" @@ -8872,7 +8881,7 @@ (zero_extract:SI (match_operand 2 "ext_register_operand" "Q") (const_int 8) (const_int 8)))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(!TARGET_PARTIAL_REG_STALL || optimize_size)" "ior{b}\t{%h2, %h0|%h0, %h2}" [(set_attr "type" "alu") @@ -8883,7 +8892,7 @@ [(set (match_operand 0 "register_operand" "") (ior (match_operand 1 "register_operand" "") (match_operand 2 "const_int_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && QI_REG_P (operands[0]) && (!TARGET_PARTIAL_REG_STALL || optimize_size) @@ -8893,7 +8902,7 @@ (ior:SI (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8)) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[0] = gen_lowpart (SImode, operands[0]); operands[1] = gen_lowpart (SImode, operands[1]); operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);") @@ -8904,7 +8913,7 @@ [(set (match_operand 0 "register_operand" "") (ior (match_operand 1 "general_operand" "") (match_operand 2 "const_int_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && ANY_QI_REG_P (operands[0]) && (!TARGET_PARTIAL_REG_STALL || optimize_size) @@ -8914,7 +8923,7 @@ [(parallel [(set (strict_low_part (match_dup 0)) (ior:QI (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[0] = gen_lowpart (QImode, operands[0]); operands[1] = gen_lowpart (QImode, operands[1]); operands[2] = gen_lowpart (QImode, operands[2]);") @@ -8928,7 +8937,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "") (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "x86_64_general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "ix86_expand_binary_operator (XOR, DImode, operands); DONE;") @@ -8936,7 +8945,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "x86_64_general_operand" "re,rm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (XOR, DImode, operands)" "@ @@ -8978,7 +8987,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "") (xor:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:SI 2 "general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "ix86_expand_binary_operator (XOR, SImode, operands); DONE;") @@ -8986,7 +8995,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") (match_operand:SI 2 "general_operand" "ri,rm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (XOR, SImode, operands)" "xor{l}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -8999,7 +9008,7 @@ (zero_extend:DI (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0") (match_operand:SI 2 "general_operand" "rim")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)" "xor{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") @@ -9009,7 +9018,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)" "xor{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") @@ -9072,7 +9081,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "") (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:HI 2 "general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_HIMODE_MATH" "ix86_expand_binary_operator (XOR, HImode, operands); DONE;") @@ -9080,7 +9089,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m") (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") (match_operand:HI 2 "general_operand" "rmi,ri"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (XOR, HImode, operands)" "xor{w}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") @@ -9115,7 +9124,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "") (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") (match_operand:QI 2 "general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_QIMODE_MATH" "ix86_expand_binary_operator (XOR, QImode, operands); DONE;") @@ -9124,7 +9133,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r") (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") (match_operand:QI 2 "general_operand" "qmi,qi,ri"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (XOR, QImode, operands)" "@ xor{b}\t{%2, %0|%0, %2} @@ -9137,7 +9146,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) (xor:QI (match_dup 0) (match_operand:QI 1 "general_operand" "qi,qmi"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "xor{b}\t{%1, %0|%0, %1}" @@ -9154,7 +9163,7 @@ (const_int 8) (const_int 8)) (match_operand 2 "const_int_operand" "n"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(!TARGET_PARTIAL_REG_STALL || optimize_size)" "xor{b}\t{%2, %h0|%h0, %2}" [(set_attr "type" "alu") @@ -9172,7 +9181,7 @@ (const_int 8)) (zero_extend:SI (match_operand:QI 2 "general_operand" "Qm")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && (!TARGET_PARTIAL_REG_STALL || optimize_size)" "xor{b}\t{%2, %h0|%h0, %2}" @@ -9191,7 +9200,7 @@ (const_int 8)) (zero_extend:SI (match_operand 2 "ext_register_operand" "Q")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (!TARGET_PARTIAL_REG_STALL || optimize_size)" "xor{b}\t{%2, %h0|%h0, %2}" @@ -9210,7 +9219,7 @@ (zero_extract:SI (match_operand 2 "ext_register_operand" "Q") (const_int 8) (const_int 8)))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(!TARGET_PARTIAL_REG_STALL || optimize_size)" "xor{b}\t{%h2, %h0|%h0, %h2}" [(set_attr "type" "alu") @@ -9302,7 +9311,7 @@ (define_expand "xorqi_cc_ext_1" [(parallel [ - (set (reg:CCNO 17) + (set (reg:CCNO FLAGS_REG) (compare:CCNO (xor:SI (zero_extract:SI @@ -9324,7 +9333,7 @@ [(set (match_operand 0 "register_operand" "") (xor (match_operand 1 "register_operand" "") (match_operand 2 "const_int_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && QI_REG_P (operands[0]) && (!TARGET_PARTIAL_REG_STALL || optimize_size) @@ -9334,7 +9343,7 @@ (xor:SI (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8)) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[0] = gen_lowpart (SImode, operands[0]); operands[1] = gen_lowpart (SImode, operands[1]); operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);") @@ -9345,7 +9354,7 @@ [(set (match_operand 0 "register_operand" "") (xor (match_operand 1 "general_operand" "") (match_operand 2 "const_int_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && ANY_QI_REG_P (operands[0]) && (!TARGET_PARTIAL_REG_STALL || optimize_size) @@ -9355,7 +9364,7 @@ [(parallel [(set (strict_low_part (match_dup 0)) (xor:QI (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[0] = gen_lowpart (QImode, operands[0]); operands[1] = gen_lowpart (QImode, operands[1]); operands[2] = gen_lowpart (QImode, operands[2]);") @@ -9365,14 +9374,14 @@ (define_expand "negdi2" [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") (neg:DI (match_operand:DI 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "ix86_expand_unary_operator (NEG, DImode, operands); DONE;") (define_insn "*negdi2_1" [(set (match_operand:DI 0 "nonimmediate_operand" "=ro") (neg:DI (match_operand:DI 1 "general_operand" "0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)" "#") @@ -9380,29 +9389,29 @@ (define_split [(set (match_operand:DI 0 "nonimmediate_operand" "") (neg:DI (match_operand:DI 1 "general_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && reload_completed" [(parallel - [(set (reg:CCZ 17) + [(set (reg:CCZ FLAGS_REG) (compare:CCZ (neg:SI (match_dup 2)) (const_int 0))) (set (match_dup 0) (neg:SI (match_dup 2)))]) (parallel [(set (match_dup 1) - (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0)) + (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0)) (match_dup 3)) (const_int 0))) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (parallel [(set (match_dup 1) (neg:SI (match_dup 1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "split_di (operands+1, 1, operands+2, operands+3); split_di (operands+0, 1, operands+0, operands+1);") (define_insn "*negdi2_1_rex64" [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)" "neg{q}\t%0" [(set_attr "type" "negnot") @@ -9413,7 +9422,7 @@ ;; flag being the only useful item. (define_insn "*negdi2_cmpz_rex64" - [(set (reg:CCZ 17) + [(set (reg:CCZ FLAGS_REG) (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")) (const_int 0))) (set (match_operand:DI 0 "nonimmediate_operand" "=rm") @@ -9427,14 +9436,14 @@ (define_expand "negsi2" [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") (neg:SI (match_operand:SI 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "ix86_expand_unary_operator (NEG, SImode, operands); DONE;") (define_insn "*negsi2_1" [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_unary_operator_ok (NEG, SImode, operands)" "neg{l}\t%0" [(set_attr "type" "negnot") @@ -9446,7 +9455,7 @@ (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0") (const_int 32))) (const_int 32))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)" "neg{l}\t%k0" [(set_attr "type" "negnot") @@ -9457,7 +9466,7 @@ ;; flag being the only useful item. (define_insn "*negsi2_cmpz" - [(set (reg:CCZ 17) + [(set (reg:CCZ FLAGS_REG) (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")) (const_int 0))) (set (match_operand:SI 0 "nonimmediate_operand" "=rm") @@ -9468,7 +9477,7 @@ (set_attr "mode" "SI")]) (define_insn "*negsi2_cmpz_zext" - [(set (reg:CCZ 17) + [(set (reg:CCZ FLAGS_REG) (compare:CCZ (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0") @@ -9487,21 +9496,21 @@ (define_expand "neghi2" [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") (neg:HI (match_operand:HI 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_HIMODE_MATH" "ix86_expand_unary_operator (NEG, HImode, operands); DONE;") (define_insn "*neghi2_1" [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_unary_operator_ok (NEG, HImode, operands)" "neg{w}\t%0" [(set_attr "type" "negnot") (set_attr "mode" "HI")]) (define_insn "*neghi2_cmpz" - [(set (reg:CCZ 17) + [(set (reg:CCZ FLAGS_REG) (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")) (const_int 0))) (set (match_operand:HI 0 "nonimmediate_operand" "=rm") @@ -9514,21 +9523,21 @@ (define_expand "negqi2" [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "") (neg:QI (match_operand:QI 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH" "ix86_expand_unary_operator (NEG, QImode, operands); DONE;") (define_insn "*negqi2_1" [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_unary_operator_ok (NEG, QImode, operands)" "neg{b}\t%0" [(set_attr "type" "negnot") (set_attr "mode" "QI")]) (define_insn "*negqi2_cmpz" - [(set (reg:CCZ 17) + [(set (reg:CCZ FLAGS_REG) (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")) (const_int 0))) (set (match_operand:QI 0 "nonimmediate_operand" "=qm") @@ -9543,7 +9552,7 @@ (define_expand "negsf2" [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") (neg:SF (match_operand:SF 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387" "if (TARGET_SSE) { @@ -9577,7 +9586,7 @@ (define_insn "negsf2_memory" [(set (match_operand:SF 0 "memory_operand" "=m") (neg:SF (match_operand:SF 1 "memory_operand" "0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_unary_operator_ok (NEG, SFmode, operands)" "#") @@ -9585,7 +9594,7 @@ [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf") (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0"))) (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_SSE && (reload_in_progress || reload_completed || (register_operand (operands[0], VOIDmode) @@ -9596,27 +9605,27 @@ [(set (match_operand:SF 0 "memory_operand" "") (neg:SF (match_operand:SF 1 "memory_operand" ""))) (use (match_operand:SF 2 "" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" [(parallel [(set (match_dup 0) (neg:SF (match_dup 1))) - (clobber (reg:CC 17))])]) + (clobber (reg:CC FLAGS_REG))])]) (define_split [(set (match_operand:SF 0 "register_operand" "") (neg:SF (match_operand:SF 1 "register_operand" ""))) (use (match_operand:V4SF 2 "" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && !SSE_REG_P (operands[0])" [(parallel [(set (match_dup 0) (neg:SF (match_dup 1))) - (clobber (reg:CC 17))])]) + (clobber (reg:CC FLAGS_REG))])]) (define_split [(set (match_operand:SF 0 "register_operand" "") (neg:SF (match_operand:SF 1 "register_operand" ""))) (use (match_operand:V4SF 2 "nonimmediate_operand" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && SSE_REG_P (operands[0])" [(set (match_dup 0) (xor:V4SF (match_dup 1) @@ -9640,7 +9649,7 @@ (define_insn "*negsf2_if" [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f") (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && !TARGET_SSE && ix86_unary_operator_ok (NEG, SFmode, operands)" "#") @@ -9648,7 +9657,7 @@ (define_split [(set (match_operand:SF 0 "fp_register_operand" "") (neg:SF (match_operand:SF 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && reload_completed" [(set (match_dup 0) (neg:SF (match_dup 1)))] @@ -9657,20 +9666,20 @@ (define_split [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "") (neg:SF (match_operand:SF 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && reload_completed" [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[1] = gen_int_mode (0x80000000, SImode); operands[0] = gen_lowpart (SImode, operands[0]);") (define_split [(set (match_operand 0 "memory_operand" "") (neg (match_operand 1 "memory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))" [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] { int size = GET_MODE_SIZE (GET_MODE (operands[1])); @@ -9683,7 +9692,7 @@ (define_expand "negdf2" [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") (neg:DF (match_operand:DF 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387" "if (TARGET_SSE2) { @@ -9720,7 +9729,7 @@ (define_insn "negdf2_memory" [(set (match_operand:DF 0 "memory_operand" "=m") (neg:DF (match_operand:DF 1 "memory_operand" "0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_unary_operator_ok (NEG, DFmode, operands)" "#") @@ -9728,7 +9737,7 @@ [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf") (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0"))) (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_SSE2 && (reload_in_progress || reload_completed || (register_operand (operands[0], VOIDmode) @@ -9739,7 +9748,7 @@ [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,fm#Y") (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0"))) (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_SSE2 && (reload_in_progress || reload_completed || (register_operand (operands[0], VOIDmode) @@ -9750,32 +9759,32 @@ [(set (match_operand:DF 0 "memory_operand" "") (neg:DF (match_operand:DF 1 "memory_operand" ""))) (use (match_operand:V2DF 2 "" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" [(parallel [(set (match_dup 0) (neg:DF (match_dup 1))) - (clobber (reg:CC 17))])]) + (clobber (reg:CC FLAGS_REG))])]) (define_split [(set (match_operand:DF 0 "register_operand" "") (neg:DF (match_operand:DF 1 "register_operand" ""))) (use (match_operand:V2DF 2 "" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && !SSE_REG_P (operands[0]) && (!TARGET_64BIT || FP_REG_P (operands[0]))" [(parallel [(set (match_dup 0) (neg:DF (match_dup 1))) - (clobber (reg:CC 17))])]) + (clobber (reg:CC FLAGS_REG))])]) (define_split [(set (match_operand:DF 0 "register_operand" "") (neg:DF (match_operand:DF 1 "register_operand" ""))) (use (match_operand:V2DF 2 "" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])" [(parallel [(set (match_dup 0) (xor:DI (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[0] = gen_lowpart (DImode, operands[0]); operands[1] = gen_lowpart (DImode, operands[1]); operands[2] = gen_lowpart (DImode, operands[2]);") @@ -9784,7 +9793,7 @@ [(set (match_operand:DF 0 "register_operand" "") (neg:DF (match_operand:DF 1 "register_operand" ""))) (use (match_operand:V2DF 2 "nonimmediate_operand" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && SSE_REG_P (operands[0])" [(set (match_dup 0) (xor:V2DF (match_dup 1) @@ -9810,7 +9819,7 @@ (define_insn "*negdf2_if" [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f") (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_80387 && ix86_unary_operator_ok (NEG, DFmode, operands)" "#") @@ -9822,7 +9831,7 @@ (define_insn "*negdf2_if_rex64" [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf") (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_80387 && ix86_unary_operator_ok (NEG, DFmode, operands)" "#") @@ -9830,7 +9839,7 @@ (define_split [(set (match_operand:DF 0 "fp_register_operand" "") (neg:DF (match_operand:DF 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && reload_completed" [(set (match_dup 0) (neg:DF (match_dup 1)))] @@ -9839,17 +9848,17 @@ (define_split [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "") (neg:DF (match_operand:DF 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_80387 && reload_completed" [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[4] = gen_int_mode (0x80000000, SImode); split_di (operands+0, 1, operands+2, operands+3);") (define_expand "negxf2" [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "") (neg:XF (match_operand:XF 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387" "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;") @@ -9859,7 +9868,7 @@ (define_insn "*negxf2_if" [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f") (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && ix86_unary_operator_ok (NEG, XFmode, operands)" "#") @@ -9867,7 +9876,7 @@ (define_split [(set (match_operand:XF 0 "fp_register_operand" "") (neg:XF (match_operand:XF 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && reload_completed" [(set (match_dup 0) (neg:XF (match_dup 1)))] @@ -9876,10 +9885,10 @@ (define_split [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "") (neg:XF (match_operand:XF 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && reload_completed" [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[1] = GEN_INT (0x8000); operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") @@ -9943,7 +9952,7 @@ (define_expand "abssf2" [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") (neg:SF (match_operand:SF 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387" "if (TARGET_SSE) { @@ -9978,7 +9987,7 @@ (define_insn "abssf2_memory" [(set (match_operand:SF 0 "memory_operand" "=m") (abs:SF (match_operand:SF 1 "memory_operand" "0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_unary_operator_ok (ABS, SFmode, operands)" "#") @@ -9986,7 +9995,7 @@ [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf") (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0"))) (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_SSE && (reload_in_progress || reload_completed || (register_operand (operands[0], VOIDmode) @@ -9997,27 +10006,27 @@ [(set (match_operand:SF 0 "memory_operand" "") (abs:SF (match_operand:SF 1 "memory_operand" ""))) (use (match_operand:V4SF 2 "" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" [(parallel [(set (match_dup 0) (abs:SF (match_dup 1))) - (clobber (reg:CC 17))])]) + (clobber (reg:CC FLAGS_REG))])]) (define_split [(set (match_operand:SF 0 "register_operand" "") (abs:SF (match_operand:SF 1 "register_operand" ""))) (use (match_operand:V4SF 2 "" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && !SSE_REG_P (operands[0])" [(parallel [(set (match_dup 0) (abs:SF (match_dup 1))) - (clobber (reg:CC 17))])]) + (clobber (reg:CC FLAGS_REG))])]) (define_split [(set (match_operand:SF 0 "register_operand" "") (abs:SF (match_operand:SF 1 "register_operand" ""))) (use (match_operand:V4SF 2 "nonimmediate_operand" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && SSE_REG_P (operands[0])" [(set (match_dup 0) (and:V4SF (match_dup 1) @@ -10040,14 +10049,14 @@ (define_insn "*abssf2_if" [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f") (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE" "#") (define_split [(set (match_operand:SF 0 "fp_register_operand" "") (abs:SF (match_operand:SF 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && reload_completed" [(set (match_dup 0) (abs:SF (match_dup 1)))] @@ -10056,20 +10065,20 @@ (define_split [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "") (abs:SF (match_operand:SF 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && reload_completed" [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[1] = gen_int_mode (~0x80000000, SImode); operands[0] = gen_lowpart (SImode, operands[0]);") (define_split [(set (match_operand 0 "memory_operand" "") (abs (match_operand 1 "memory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))" [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] { int size = GET_MODE_SIZE (GET_MODE (operands[1])); @@ -10082,7 +10091,7 @@ (define_expand "absdf2" [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") (neg:DF (match_operand:DF 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387" "if (TARGET_SSE2) { @@ -10121,7 +10130,7 @@ (define_insn "absdf2_memory" [(set (match_operand:DF 0 "memory_operand" "=m") (abs:DF (match_operand:DF 1 "memory_operand" "0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_unary_operator_ok (ABS, DFmode, operands)" "#") @@ -10129,7 +10138,7 @@ [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr,mr#Yf") (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0"))) (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_SSE2 && (reload_in_progress || reload_completed || (register_operand (operands[0], VOIDmode) @@ -10140,7 +10149,7 @@ [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr") (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0"))) (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_SSE2 && (reload_in_progress || reload_completed || (register_operand (operands[0], VOIDmode) @@ -10151,27 +10160,27 @@ [(set (match_operand:DF 0 "memory_operand" "") (abs:DF (match_operand:DF 1 "memory_operand" ""))) (use (match_operand:V2DF 2 "" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" [(parallel [(set (match_dup 0) (abs:DF (match_dup 1))) - (clobber (reg:CC 17))])]) + (clobber (reg:CC FLAGS_REG))])]) (define_split [(set (match_operand:DF 0 "register_operand" "") (abs:DF (match_operand:DF 1 "register_operand" ""))) (use (match_operand:V2DF 2 "" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && !SSE_REG_P (operands[0])" [(parallel [(set (match_dup 0) (abs:DF (match_dup 1))) - (clobber (reg:CC 17))])]) + (clobber (reg:CC FLAGS_REG))])]) (define_split [(set (match_operand:DF 0 "register_operand" "") (abs:DF (match_operand:DF 1 "register_operand" ""))) (use (match_operand:V2DF 2 "nonimmediate_operand" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && SSE_REG_P (operands[0])" [(set (match_dup 0) (and:V2DF (match_dup 1) @@ -10198,7 +10207,7 @@ (define_insn "*absdf2_if" [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f") (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_80387 && ix86_unary_operator_ok (ABS, DFmode, operands)" "#") @@ -10210,7 +10219,7 @@ (define_insn "*absdf2_if_rex64" [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf") (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_80387 && ix86_unary_operator_ok (ABS, DFmode, operands)" "#") @@ -10218,7 +10227,7 @@ (define_split [(set (match_operand:DF 0 "fp_register_operand" "") (abs:DF (match_operand:DF 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && reload_completed" [(set (match_dup 0) (abs:DF (match_dup 1)))] @@ -10227,17 +10236,17 @@ (define_split [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "") (abs:DF (match_operand:DF 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_80387 && reload_completed" [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[4] = gen_int_mode (~0x80000000, SImode); split_di (operands+0, 1, operands+2, operands+3);") (define_expand "absxf2" [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "") (neg:XF (match_operand:XF 1 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_80387" "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;") @@ -10247,7 +10256,7 @@ (define_insn "*absxf2_if" [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f") (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && ix86_unary_operator_ok (ABS, XFmode, operands)" "#") @@ -10255,7 +10264,7 @@ (define_split [(set (match_operand:XF 0 "fp_register_operand" "") (abs:XF (match_operand:XF 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && reload_completed" [(set (match_dup 0) (abs:XF (match_dup 1)))] @@ -10264,10 +10273,10 @@ (define_split [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "") (abs:XF (match_operand:XF 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && reload_completed" [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[1] = GEN_INT (~0x8000); operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));") @@ -10358,7 +10367,7 @@ (set (match_operand:DI 0 "nonimmediate_operand" "") (not:DI (match_dup 1)))] "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" - [(parallel [(set (reg:CCNO 17) + [(parallel [(set (reg:CCNO FLAGS_REG) (compare:CCNO (xor:DI (match_dup 1) (const_int -1)) (const_int 0))) (set (match_dup 0) @@ -10407,7 +10416,7 @@ (set (match_operand:SI 0 "nonimmediate_operand" "") (not:SI (match_dup 1)))] "ix86_match_ccmode (insn, CCNOmode)" - [(parallel [(set (reg:CCNO 17) + [(parallel [(set (reg:CCNO FLAGS_REG) (compare:CCNO (xor:SI (match_dup 1) (const_int -1)) (const_int 0))) (set (match_dup 0) @@ -10434,7 +10443,7 @@ (set (match_operand:DI 0 "register_operand" "") (zero_extend:DI (not:SI (match_dup 1))))] "ix86_match_ccmode (insn, CCNOmode)" - [(parallel [(set (reg:CCNO 17) + [(parallel [(set (reg:CCNO FLAGS_REG) (compare:CCNO (xor:SI (match_dup 1) (const_int -1)) (const_int 0))) (set (match_dup 0) @@ -10474,7 +10483,7 @@ (set (match_operand:HI 0 "nonimmediate_operand" "") (not:HI (match_dup 1)))] "ix86_match_ccmode (insn, CCNOmode)" - [(parallel [(set (reg:CCNO 17) + [(parallel [(set (reg:CCNO FLAGS_REG) (compare:CCNO (xor:HI (match_dup 1) (const_int -1)) (const_int 0))) (set (match_dup 0) @@ -10517,7 +10526,7 @@ (set (match_operand:QI 0 "nonimmediate_operand" "") (not:QI (match_dup 1)))] "ix86_match_ccmode (insn, CCNOmode)" - [(parallel [(set (reg:CCNO 17) + [(parallel [(set (reg:CCNO FLAGS_REG) (compare:CCNO (xor:QI (match_dup 1) (const_int -1)) (const_int 0))) (set (match_dup 0) @@ -10552,7 +10561,7 @@ [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "") (ashift:DI (match_operand:DI 1 "shiftdi_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" { if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode)) @@ -10568,7 +10577,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r") (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r") (match_operand:QI 2 "nonmemory_operand" "cJ,M"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)" { switch (get_attr_type (insn)) @@ -10615,7 +10624,7 @@ [(set (match_operand:DI 0 "register_operand" "") (ashift:DI (match_operand:DI 1 "register_operand" "") (match_operand:QI 2 "immediate_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && reload_completed && true_regnum (operands[0]) != true_regnum (operands[1])" [(set (match_dup 0) @@ -10669,7 +10678,7 @@ (ashift:DI (match_operand:DI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "Jc"))) (clobber (match_scratch:SI 3 "=&r")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_CMOVE" "#" [(set_attr "type" "multi")]) @@ -10678,7 +10687,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (match_operand:DI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "Jc"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT" "#" [(set_attr "type" "multi")]) @@ -10688,7 +10697,7 @@ (ashift:DI (match_operand:DI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) (clobber (match_scratch:SI 3 "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_CMOVE && reload_completed" [(const_int 0)] "ix86_split_ashldi (operands, operands[3]); DONE;") @@ -10697,7 +10706,7 @@ [(set (match_operand:DI 0 "register_operand" "") (ashift:DI (match_operand:DI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && reload_completed" [(const_int 0)] "ix86_split_ashldi (operands, NULL_RTX); DONE;") @@ -10708,7 +10717,7 @@ (match_operand:QI 2 "nonmemory_operand" "I,c")) (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r") (minus:QI (const_int 32) (match_dup 2))))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "@ shld{l}\t{%2, %1, %0|%0, %1, %2} @@ -10720,16 +10729,16 @@ (set_attr "athlon_decode" "vector")]) (define_expand "x86_shift_adj_1" - [(set (reg:CCZ 17) + [(set (reg:CCZ FLAGS_REG) (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "") (const_int 32)) (const_int 0))) (set (match_operand:SI 0 "register_operand" "") - (if_then_else:SI (ne (reg:CCZ 17) (const_int 0)) + (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0)) (match_operand:SI 1 "register_operand" "") (match_dup 0))) (set (match_dup 1) - (if_then_else:SI (ne (reg:CCZ 17) (const_int 0)) + (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0)) (match_operand:SI 3 "register_operand" "r") (match_dup 1)))] "TARGET_CMOVE" @@ -10767,7 +10776,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "") (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;") @@ -10775,7 +10784,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r") (match_operand:QI 2 "nonmemory_operand" "cI,M"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFT, SImode, operands)" { switch (get_attr_type (insn)) @@ -10817,7 +10826,7 @@ [(set (match_operand 0 "register_operand" "") (ashift (match_operand 1 "index_register_operand" "") (match_operand:QI 2 "const_int_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && true_regnum (operands[0]) != true_regnum (operands[1])" [(const_int 0)] @@ -10838,7 +10847,7 @@ [(set (match_operand 0 "register_operand" "") (ashift (match_operand 1 "register_operand" "") (match_operand:QI 2 "const_int_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && true_regnum (operands[0]) != true_regnum (operands[1])" [(const_int 0)] @@ -10857,7 +10866,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r") (match_operand:QI 2 "nonmemory_operand" "cI,M")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)" { switch (get_attr_type (insn)) @@ -10896,7 +10905,7 @@ [(set (match_operand:DI 0 "register_operand" "") (zero_extend:DI (ashift (match_operand 1 "register_operand" "") (match_operand:QI 2 "const_int_operand" "")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && reload_completed && true_regnum (operands[0]) != true_regnum (operands[1])" [(set (match_dup 0) (zero_extend:DI @@ -10989,7 +10998,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "") (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_HIMODE_MATH" "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;") @@ -10997,7 +11006,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r") (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r") (match_operand:QI 2 "nonmemory_operand" "cI,M"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_PARTIAL_REG_STALL && ix86_binary_operator_ok (ASHIFT, HImode, operands)" { @@ -11036,7 +11045,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "nonmemory_operand" "cI"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_PARTIAL_REG_STALL && ix86_binary_operator_ok (ASHIFT, HImode, operands)" { @@ -11112,7 +11121,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "") (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_QIMODE_MATH" "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;") @@ -11122,7 +11131,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r") (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r") (match_operand:QI 2 "nonmemory_operand" "cI,cI,M"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_PARTIAL_REG_STALL && ix86_binary_operator_ok (ASHIFT, QImode, operands)" { @@ -11179,7 +11188,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r") (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "cI,cI"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_PARTIAL_REG_STALL && ix86_binary_operator_ok (ASHIFT, QImode, operands)" { @@ -11275,7 +11284,7 @@ [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "") (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" { if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode)) @@ -11291,7 +11300,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm") (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0") (match_operand:DI 2 "const_int_operand" "i,i"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size) && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" "@ @@ -11307,7 +11316,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands) && (TARGET_SHIFT1 || optimize_size)" "sar{q}\t%0" @@ -11321,7 +11330,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "J,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)" "@ sar{q}\t{%2, %0|%0, %2} @@ -11373,7 +11382,7 @@ (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "Jc"))) (clobber (match_scratch:SI 3 "=&r")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_CMOVE" "#" [(set_attr "type" "multi")]) @@ -11382,7 +11391,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "Jc"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT" "#" [(set_attr "type" "multi")]) @@ -11392,7 +11401,7 @@ (ashiftrt:DI (match_operand:DI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) (clobber (match_scratch:SI 3 "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_CMOVE && reload_completed" [(const_int 0)] "ix86_split_ashrdi (operands, operands[3]); DONE;") @@ -11401,7 +11410,7 @@ [(set (match_operand:DI 0 "register_operand" "") (ashiftrt:DI (match_operand:DI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && reload_completed" [(const_int 0)] "ix86_split_ashrdi (operands, NULL_RTX); DONE;") @@ -11412,7 +11421,7 @@ (match_operand:QI 2 "nonmemory_operand" "I,c")) (ashift:SI (match_operand:SI 1 "register_operand" "r,r") (minus:QI (const_int 32) (match_dup 2))))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "@ shrd{l}\t{%2, %1, %0|%0, %1, %2} @@ -11454,7 +11463,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm") (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0") (match_operand:SI 2 "const_int_operand" "i,i"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size) && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" "@ @@ -11470,7 +11479,7 @@ [(set (match_operand:DI 0 "register_operand" "=*d,r") (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0") (match_operand:SI 2 "const_int_operand" "i,i")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size) && INTVAL (operands[2]) == 31 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" @@ -11487,7 +11496,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "") (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;") @@ -11495,7 +11504,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFTRT, SImode, operands) && (TARGET_SHIFT1 || optimize_size)" "sar{l}\t%0" @@ -11509,7 +11518,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:QI 2 "const1_operand" "")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands) && (TARGET_SHIFT1 || optimize_size)" "sar{l}\t%k0" @@ -11520,7 +11529,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" "@ sar{l}\t{%2, %0|%0, %2} @@ -11532,7 +11541,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)" "@ sar{l}\t{%2, %k0|%k0, %2} @@ -11611,7 +11620,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "") (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_HIMODE_MATH" "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;") @@ -11619,7 +11628,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFTRT, HImode, operands) && (TARGET_SHIFT1 || optimize_size)" "sar{w}\t%0" @@ -11633,7 +11642,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)" "@ sar{w}\t{%2, %0|%0, %2} @@ -11683,7 +11692,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "") (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_QIMODE_MATH" "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;") @@ -11691,7 +11700,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFTRT, QImode, operands) && (TARGET_SHIFT1 || optimize_size)" "sar{b}\t%0" @@ -11705,7 +11714,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) (ashiftrt:QI (match_dup 0) (match_operand:QI 1 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFTRT, QImode, operands) && (! TARGET_PARTIAL_REG_STALL || optimize_size) && (TARGET_SHIFT1 || optimize_size)" @@ -11720,7 +11729,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)" "@ sar{b}\t{%2, %0|%0, %2} @@ -11732,7 +11741,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) (ashiftrt:QI (match_dup 0) (match_operand:QI 1 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ @@ -11787,7 +11796,7 @@ [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "") (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" { if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode)) @@ -11803,7 +11812,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) && (TARGET_SHIFT1 || optimize_size)" "shr{q}\t%0" @@ -11817,7 +11826,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "J,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" "@ shr{q}\t{%2, %0|%0, %2} @@ -11868,7 +11877,7 @@ (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "Jc"))) (clobber (match_scratch:SI 3 "=&r")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_CMOVE" "#" [(set_attr "type" "multi")]) @@ -11877,7 +11886,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "Jc"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT" "#" [(set_attr "type" "multi")]) @@ -11887,7 +11896,7 @@ (lshiftrt:DI (match_operand:DI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) (clobber (match_scratch:SI 3 "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_CMOVE && reload_completed" [(const_int 0)] "ix86_split_lshrdi (operands, operands[3]); DONE;") @@ -11896,7 +11905,7 @@ [(set (match_operand:DI 0 "register_operand" "") (lshiftrt:DI (match_operand:DI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && reload_completed" [(const_int 0)] "ix86_split_lshrdi (operands, NULL_RTX); DONE;") @@ -11905,7 +11914,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "") (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;") @@ -11913,7 +11922,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (LSHIFTRT, HImode, operands) && (TARGET_SHIFT1 || optimize_size)" "shr{l}\t%0" @@ -11927,7 +11936,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0")) (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands) && (TARGET_SHIFT1 || optimize_size)" "shr{l}\t%k0" @@ -11938,7 +11947,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" "@ shr{l}\t{%2, %0|%0, %2} @@ -11951,7 +11960,7 @@ (zero_extend:DI (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" "@ shr{l}\t{%2, %k0|%k0, %2} @@ -12030,7 +12039,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "") (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_HIMODE_MATH" "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;") @@ -12038,7 +12047,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (LSHIFTRT, HImode, operands) && (TARGET_SHIFT1 || optimize_size)" "shr{w}\t%0" @@ -12052,7 +12061,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)" "@ shr{w}\t{%2, %0|%0, %2} @@ -12102,7 +12111,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "") (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_QIMODE_MATH" "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;") @@ -12110,7 +12119,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (LSHIFTRT, QImode, operands) && (TARGET_SHIFT1 || optimize_size)" "shr{b}\t%0" @@ -12124,7 +12133,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) (lshiftrt:QI (match_dup 0) (match_operand:QI 1 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) && (TARGET_SHIFT1 || optimize_size)" "shr{b}\t%0" @@ -12138,7 +12147,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)" "@ shr{b}\t{%2, %0|%0, %2} @@ -12150,7 +12159,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) (lshiftrt:QI (match_dup 0) (match_operand:QI 1 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ @@ -12203,7 +12212,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "") (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;") @@ -12211,7 +12220,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands) && (TARGET_SHIFT1 || optimize_size)" "rol{q}\t%0" @@ -12225,7 +12234,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "e,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)" "@ rol{q}\t{%2, %0|%0, %2} @@ -12237,7 +12246,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "") (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;") @@ -12245,7 +12254,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ROTATE, SImode, operands) && (TARGET_SHIFT1 || optimize_size)" "rol{l}\t%0" @@ -12260,7 +12269,7 @@ (zero_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "0") (match_operand:QI 2 "const1_operand" "")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands) && (TARGET_SHIFT1 || optimize_size)" "rol{l}\t%k0" @@ -12271,7 +12280,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ROTATE, SImode, operands)" "@ rol{l}\t{%2, %0|%0, %2} @@ -12284,7 +12293,7 @@ (zero_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)" "@ rol{l}\t{%2, %k0|%k0, %2} @@ -12296,7 +12305,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "") (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_HIMODE_MATH" "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;") @@ -12304,7 +12313,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ROTATE, HImode, operands) && (TARGET_SHIFT1 || optimize_size)" "rol{w}\t%0" @@ -12318,7 +12327,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ROTATE, HImode, operands)" "@ rol{w}\t{%2, %0|%0, %2} @@ -12330,7 +12339,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "") (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_QIMODE_MATH" "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;") @@ -12338,7 +12347,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) (rotate:QI (match_dup 0) (match_operand:QI 1 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) && (TARGET_SHIFT1 || optimize_size)" "rol{b}\t%0" @@ -12352,7 +12361,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ROTATE, QImode, operands) && (TARGET_SHIFT1 || optimize_size)" "rol{b}\t%0" @@ -12366,7 +12375,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) (rotate:QI (match_dup 0) (match_operand:QI 1 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ @@ -12379,7 +12388,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ROTATE, QImode, operands)" "@ rol{b}\t{%2, %0|%0, %2} @@ -12391,7 +12400,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "") (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;") @@ -12399,7 +12408,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands) && (TARGET_SHIFT1 || optimize_size)" "ror{q}\t%0" @@ -12413,7 +12422,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm") (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "J,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)" "@ ror{q}\t{%2, %0|%0, %2} @@ -12425,7 +12434,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "") (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;") @@ -12433,7 +12442,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ROTATERT, SImode, operands) && (TARGET_SHIFT1 || optimize_size)" "ror{l}\t%0" @@ -12448,7 +12457,7 @@ (zero_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "0") (match_operand:QI 2 "const1_operand" "")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands) && (TARGET_SHIFT1 || optimize_size)" "ror{l}\t%k0" @@ -12462,7 +12471,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm") (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ROTATERT, SImode, operands)" "@ ror{l}\t{%2, %0|%0, %2} @@ -12475,7 +12484,7 @@ (zero_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)" "@ ror{l}\t{%2, %k0|%k0, %2} @@ -12487,7 +12496,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "") (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_HIMODE_MATH" "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;") @@ -12495,7 +12504,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ROTATERT, HImode, operands) && (TARGET_SHIFT1 || optimize_size)" "ror{w}\t%0" @@ -12509,7 +12518,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm") (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ROTATERT, HImode, operands)" "@ ror{w}\t{%2, %0|%0, %2} @@ -12521,7 +12530,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "") (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "") (match_operand:QI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_QIMODE_MATH" "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;") @@ -12529,7 +12538,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm") (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0") (match_operand:QI 2 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ROTATERT, QImode, operands) && (TARGET_SHIFT1 || optimize_size)" "ror{b}\t%0" @@ -12543,7 +12552,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) (rotatert:QI (match_dup 0) (match_operand:QI 1 "const1_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) && (TARGET_SHIFT1 || optimize_size)" "ror{b}\t%0" @@ -12557,7 +12566,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm") (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0") (match_operand:QI 2 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ROTATERT, QImode, operands)" "@ ror{b}\t{%2, %0|%0, %2} @@ -12569,7 +12578,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm")) (rotatert:QI (match_dup 0) (match_operand:QI 1 "nonmemory_operand" "I,c"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_size) && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ @@ -12651,109 +12660,109 @@ (define_expand "seq" [(set (match_operand:QI 0 "register_operand" "") - (eq:QI (reg:CC 17) (const_int 0)))] + (eq:QI (reg:CC FLAGS_REG) (const_int 0)))] "" "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;") (define_expand "sne" [(set (match_operand:QI 0 "register_operand" "") - (ne:QI (reg:CC 17) (const_int 0)))] + (ne:QI (reg:CC FLAGS_REG) (const_int 0)))] "" "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;") (define_expand "sgt" [(set (match_operand:QI 0 "register_operand" "") - (gt:QI (reg:CC 17) (const_int 0)))] + (gt:QI (reg:CC FLAGS_REG) (const_int 0)))] "" "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;") (define_expand "sgtu" [(set (match_operand:QI 0 "register_operand" "") - (gtu:QI (reg:CC 17) (const_int 0)))] + (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))] "" "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;") (define_expand "slt" [(set (match_operand:QI 0 "register_operand" "") - (lt:QI (reg:CC 17) (const_int 0)))] + (lt:QI (reg:CC FLAGS_REG) (const_int 0)))] "" "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;") (define_expand "sltu" [(set (match_operand:QI 0 "register_operand" "") - (ltu:QI (reg:CC 17) (const_int 0)))] + (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))] "" "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;") (define_expand "sge" [(set (match_operand:QI 0 "register_operand" "") - (ge:QI (reg:CC 17) (const_int 0)))] + (ge:QI (reg:CC FLAGS_REG) (const_int 0)))] "" "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;") (define_expand "sgeu" [(set (match_operand:QI 0 "register_operand" "") - (geu:QI (reg:CC 17) (const_int 0)))] + (geu:QI (reg:CC FLAGS_REG) (const_int 0)))] "" "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;") (define_expand "sle" [(set (match_operand:QI 0 "register_operand" "") - (le:QI (reg:CC 17) (const_int 0)))] + (le:QI (reg:CC FLAGS_REG) (const_int 0)))] "" "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;") (define_expand "sleu" [(set (match_operand:QI 0 "register_operand" "") - (leu:QI (reg:CC 17) (const_int 0)))] + (leu:QI (reg:CC FLAGS_REG) (const_int 0)))] "" "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;") (define_expand "sunordered" [(set (match_operand:QI 0 "register_operand" "") - (unordered:QI (reg:CC 17) (const_int 0)))] + (unordered:QI (reg:CC FLAGS_REG) (const_int 0)))] "TARGET_80387 || TARGET_SSE" "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;") (define_expand "sordered" [(set (match_operand:QI 0 "register_operand" "") - (ordered:QI (reg:CC 17) (const_int 0)))] + (ordered:QI (reg:CC FLAGS_REG) (const_int 0)))] "TARGET_80387" "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;") (define_expand "suneq" [(set (match_operand:QI 0 "register_operand" "") - (uneq:QI (reg:CC 17) (const_int 0)))] + (uneq:QI (reg:CC FLAGS_REG) (const_int 0)))] "TARGET_80387 || TARGET_SSE" "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;") (define_expand "sunge" [(set (match_operand:QI 0 "register_operand" "") - (unge:QI (reg:CC 17) (const_int 0)))] + (unge:QI (reg:CC FLAGS_REG) (const_int 0)))] "TARGET_80387 || TARGET_SSE" "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;") (define_expand "sungt" [(set (match_operand:QI 0 "register_operand" "") - (ungt:QI (reg:CC 17) (const_int 0)))] + (ungt:QI (reg:CC FLAGS_REG) (const_int 0)))] "TARGET_80387 || TARGET_SSE" "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;") (define_expand "sunle" [(set (match_operand:QI 0 "register_operand" "") - (unle:QI (reg:CC 17) (const_int 0)))] + (unle:QI (reg:CC FLAGS_REG) (const_int 0)))] "TARGET_80387 || TARGET_SSE" "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;") (define_expand "sunlt" [(set (match_operand:QI 0 "register_operand" "") - (unlt:QI (reg:CC 17) (const_int 0)))] + (unlt:QI (reg:CC FLAGS_REG) (const_int 0)))] "TARGET_80387 || TARGET_SSE" "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;") (define_expand "sltgt" [(set (match_operand:QI 0 "register_operand" "") - (ltgt:QI (reg:CC 17) (const_int 0)))] + (ltgt:QI (reg:CC FLAGS_REG) (const_int 0)))] "TARGET_80387 || TARGET_SSE" "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;") @@ -13119,8 +13128,8 @@ (match_operand 2 "register_operand" "f")]) (label_ref (match_operand 3 "" "")) (pc))) - (clobber (reg:CCFP 18)) - (clobber (reg:CCFP 17))] + (clobber (reg:CCFP FPSR_REG)) + (clobber (reg:CCFP FLAGS_REG))] "TARGET_CMOVE && TARGET_80387 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1])) && FLOAT_MODE_P (GET_MODE (operands[1])) @@ -13135,8 +13144,8 @@ (match_operand 2 "nonimmediate_operand" "f#x,xm#f")]) (label_ref (match_operand 3 "" "")) (pc))) - (clobber (reg:CCFP 18)) - (clobber (reg:CCFP 17))] + (clobber (reg:CCFP FPSR_REG)) + (clobber (reg:CCFP FLAGS_REG))] "TARGET_80387 && SSE_FLOAT_MODE_P (GET_MODE (operands[1])) && GET_MODE (operands[1]) == GET_MODE (operands[2]) @@ -13150,8 +13159,8 @@ (match_operand 2 "nonimmediate_operand" "xm")]) (label_ref (match_operand 3 "" "")) (pc))) - (clobber (reg:CCFP 18)) - (clobber (reg:CCFP 17))] + (clobber (reg:CCFP FPSR_REG)) + (clobber (reg:CCFP FLAGS_REG))] "SSE_FLOAT_MODE_P (GET_MODE (operands[1])) && GET_MODE (operands[1]) == GET_MODE (operands[2]) && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" @@ -13164,8 +13173,8 @@ (match_operand 2 "register_operand" "f")]) (pc) (label_ref (match_operand 3 "" "")))) - (clobber (reg:CCFP 18)) - (clobber (reg:CCFP 17))] + (clobber (reg:CCFP FPSR_REG)) + (clobber (reg:CCFP FLAGS_REG))] "TARGET_CMOVE && TARGET_80387 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1])) && FLOAT_MODE_P (GET_MODE (operands[1])) @@ -13180,8 +13189,8 @@ (match_operand 2 "nonimmediate_operand" "f#x,xm#f")]) (pc) (label_ref (match_operand 3 "" "")))) - (clobber (reg:CCFP 18)) - (clobber (reg:CCFP 17))] + (clobber (reg:CCFP FPSR_REG)) + (clobber (reg:CCFP FLAGS_REG))] "TARGET_80387 && SSE_FLOAT_MODE_P (GET_MODE (operands[1])) && GET_MODE (operands[1]) == GET_MODE (operands[2]) @@ -13195,8 +13204,8 @@ (match_operand 2 "nonimmediate_operand" "xm")]) (pc) (label_ref (match_operand 3 "" "")))) - (clobber (reg:CCFP 18)) - (clobber (reg:CCFP 17))] + (clobber (reg:CCFP FPSR_REG)) + (clobber (reg:CCFP FLAGS_REG))] "SSE_FLOAT_MODE_P (GET_MODE (operands[1])) && GET_MODE (operands[1]) == GET_MODE (operands[2]) && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))" @@ -13209,8 +13218,8 @@ (match_operand 2 "nonimmediate_operand" "fm")]) (label_ref (match_operand 3 "" "")) (pc))) - (clobber (reg:CCFP 18)) - (clobber (reg:CCFP 17)) + (clobber (reg:CCFP FPSR_REG)) + (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 4 "=a"))] "TARGET_80387 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode) @@ -13228,8 +13237,8 @@ (match_operand 2 "nonimmediate_operand" "fm")]) (pc) (label_ref (match_operand 3 "" "")))) - (clobber (reg:CCFP 18)) - (clobber (reg:CCFP 17)) + (clobber (reg:CCFP FPSR_REG)) + (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 4 "=a"))] "TARGET_80387 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode) @@ -13247,8 +13256,8 @@ (match_operand 2 "register_operand" "f")]) (label_ref (match_operand 3 "" "")) (pc))) - (clobber (reg:CCFP 18)) - (clobber (reg:CCFP 17)) + (clobber (reg:CCFP FPSR_REG)) + (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 4 "=a"))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) @@ -13263,8 +13272,8 @@ (match_operand 2 "register_operand" "f")]) (pc) (label_ref (match_operand 3 "" "")))) - (clobber (reg:CCFP 18)) - (clobber (reg:CCFP 17)) + (clobber (reg:CCFP FPSR_REG)) + (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 4 "=a"))] "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1])) @@ -13279,8 +13288,8 @@ (match_operand 2 "nonimmediate_operand" "")]) (match_operand 3 "" "") (match_operand 4 "" ""))) - (clobber (reg:CCFP 18)) - (clobber (reg:CCFP 17))] + (clobber (reg:CCFP FPSR_REG)) + (clobber (reg:CCFP FLAGS_REG))] "reload_completed" [(const_int 0)] { @@ -13296,8 +13305,8 @@ (match_operand 2 "nonimmediate_operand" "")]) (match_operand 3 "" "") (match_operand 4 "" ""))) - (clobber (reg:CCFP 18)) - (clobber (reg:CCFP 17)) + (clobber (reg:CCFP FPSR_REG)) + (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 5 "=a"))] "reload_completed" [(set (pc) @@ -13432,7 +13441,7 @@ (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:SI 3 "=X,X,r")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_USE_LOOP && (reload_in_progress || reload_completed || register_operand (operands[2], VOIDmode))" @@ -13466,15 +13475,15 @@ (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:SI 2 "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_USE_LOOP && reload_completed && REGNO (operands[1]) != 2" - [(parallel [(set (reg:CCZ 17) + [(parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (plus:SI (match_dup 1) (const_int -1)) (const_int 0))) (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))]) - (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0)) + (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0)) (match_dup 0) (pc)))] "") @@ -13489,18 +13498,18 @@ (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:SI 3 "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_USE_LOOP && reload_completed && (! REG_P (operands[2]) || ! rtx_equal_p (operands[1], operands[2]))" [(set (match_dup 3) (match_dup 1)) - (parallel [(set (reg:CCZ 17) + (parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (plus:SI (match_dup 3) (const_int -1)) (const_int 0))) (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) (set (match_dup 2) (match_dup 3)) - (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0)) + (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0)) (match_dup 0) (pc)))] "") @@ -13535,7 +13544,7 @@ [(reg 17) (const_int 0)])) (parallel [(set (match_operand 3 "q_regs_operand" "") (zero_extend (match_dup 1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "(peep2_reg_dead_p (3, operands[1]) || operands_match_p (operands[1], operands[3])) && ! reg_overlap_mentioned_p (operands[3], operands[0])" @@ -13559,8 +13568,8 @@ (define_expand "call_pop" [(parallel [(call (match_operand:QI 0 "" "") (match_operand:SI 1 "" "")) - (set (reg:SI 7) - (plus:SI (reg:SI 7) + (set (reg:SI SP_REG) + (plus:SI (reg:SI SP_REG) (match_operand:SI 3 "" "")))])] "!TARGET_64BIT" { @@ -13571,7 +13580,7 @@ (define_insn "*call_pop_0" [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" "")) (match_operand:SI 1 "" "")) - (set (reg:SI 7) (plus:SI (reg:SI 7) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 2 "immediate_operand" "")))] "!TARGET_64BIT" { @@ -13585,7 +13594,7 @@ (define_insn "*call_pop_1" [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm")) (match_operand:SI 1 "" "")) - (set (reg:SI 7) (plus:SI (reg:SI 7) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 2 "immediate_operand" "i")))] "!TARGET_64BIT" { @@ -13689,8 +13698,8 @@ [(parallel [(set (match_operand 0 "" "") (call (match_operand:QI 1 "" "") (match_operand:SI 2 "" ""))) - (set (reg:SI 7) - (plus:SI (reg:SI 7) + (set (reg:SI SP_REG) + (plus:SI (reg:SI SP_REG) (match_operand:SI 4 "" "")))])] "!TARGET_64BIT" { @@ -13860,7 +13869,7 @@ (define_insn "set_got" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(const_int 0)] UNSPEC_SET_GOT)) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT" { return output_set_got (operands[0]); } [(set_attr "type" "multi") @@ -13919,16 +13928,16 @@ "ix86_expand_epilogue (2); DONE;") (define_insn "leave" - [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4))) - (set (reg:SI 6) (mem:SI (reg:SI 6))) + [(set (reg:SI SP_REG) (plus:SI (reg:SI BP_REG) (const_int 4))) + (set (reg:SI BP_REG) (mem:SI (reg:SI BP_REG))) (clobber (mem:BLK (scratch)))] "!TARGET_64BIT" "leave" [(set_attr "type" "leave")]) (define_insn "leave_rex64" - [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8))) - (set (reg:DI 6) (mem:DI (reg:DI 6))) + [(set (reg:DI SP_REG) (plus:DI (reg:DI BP_REG) (const_int 8))) + (set (reg:DI BP_REG) (mem:DI (reg:DI BP_REG))) (clobber (mem:BLK (scratch)))] "TARGET_64BIT" "leave" @@ -13939,7 +13948,7 @@ [(set (match_operand:SI 0 "register_operand" "") (ffs:SI (match_operand:SI 1 "nonimmediate_operand" ""))) (clobber (match_scratch:SI 2 "")) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "") @@ -13947,46 +13956,46 @@ [(set (match_operand:SI 0 "register_operand" "=r") (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))) (clobber (match_scratch:SI 2 "=&r")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_CMOVE" "#" "&& reload_completed" [(set (match_dup 2) (const_int -1)) - (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0))) + (parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0))) (set (match_dup 0) (ctz:SI (match_dup 1)))]) (set (match_dup 0) (if_then_else:SI - (eq (reg:CCZ 17) (const_int 0)) + (eq (reg:CCZ FLAGS_REG) (const_int 0)) (match_dup 2) (match_dup 0))) (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") (define_insn_and_split "*ffs_no_cmove" [(set (match_operand:SI 0 "nonimmediate_operand" "=r") (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))) (clobber (match_scratch:SI 2 "=&q")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "#" "reload_completed" - [(parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0))) + [(parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0))) (set (match_dup 0) (ctz:SI (match_dup 1)))]) (set (strict_low_part (match_dup 3)) - (eq:QI (reg:CCZ 17) (const_int 0))) + (eq:QI (reg:CCZ FLAGS_REG) (const_int 0))) (parallel [(set (match_dup 2) (neg:SI (match_dup 2))) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2))) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] { operands[3] = gen_lowpart (QImode, operands[2]); ix86_expand_clear (operands[2]); }) (define_insn "*ffssi_1" - [(set (reg:CCZ 17) + [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm") (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") @@ -13998,7 +14007,7 @@ (define_insn "ctzsi2" [(set (match_operand:SI 0 "register_operand" "=r") (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "bsf{l}\t{%1, %0|%0, %1}" [(set_attr "prefix_0f" "1")]) @@ -14008,10 +14017,10 @@ [(set (match_operand:SI 0 "register_operand" "") (minus:SI (const_int 31) (clz:SI (match_operand:SI 1 "nonimmediate_operand" "")))) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (parallel [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "") @@ -14019,7 +14028,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (const_int 31) (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "bsr{l}\t{%1, %0|%0, %1}" [(set_attr "prefix_0f" "1")]) @@ -14037,7 +14046,7 @@ UNSPEC_TLS_GD)) (clobber (match_scratch:SI 4 "=d")) (clobber (match_scratch:SI 5 "=c")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_GNU_TLS" "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3" [(set_attr "type" "multi") @@ -14051,7 +14060,7 @@ UNSPEC_TLS_GD)) (clobber (match_scratch:SI 4 "=d")) (clobber (match_scratch:SI 5 "=c")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_SUN_TLS" "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]} push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop" @@ -14067,7 +14076,7 @@ UNSPEC_TLS_GD)) (clobber (match_scratch:SI 4 "")) (clobber (match_scratch:SI 5 "")) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" { if (flag_pic) @@ -14108,7 +14117,7 @@ UNSPEC_TLS_LD_BASE)) (clobber (match_scratch:SI 3 "=d")) (clobber (match_scratch:SI 4 "=c")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_GNU_TLS" "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2" [(set_attr "type" "multi") @@ -14121,7 +14130,7 @@ UNSPEC_TLS_LD_BASE)) (clobber (match_scratch:SI 3 "=d")) (clobber (match_scratch:SI 4 "=c")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_SUN_TLS" "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]} push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3" @@ -14134,7 +14143,7 @@ UNSPEC_TLS_LD_BASE)) (clobber (match_scratch:SI 3 "")) (clobber (match_scratch:SI 4 "")) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" { if (flag_pic) @@ -14179,7 +14188,7 @@ UNSPEC_DTPOFF)))) (clobber (match_scratch:SI 4 "=d")) (clobber (match_scratch:SI 5 "=c")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "#" "" @@ -14188,7 +14197,7 @@ UNSPEC_TLS_GD)) (clobber (match_dup 4)) (clobber (match_dup 5)) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") ;; Load and add the thread base pointer from %gs:0. @@ -14208,7 +14217,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP) (match_operand:SI 1 "register_operand" "0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT" "add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}" [(set_attr "type" "alu") @@ -14232,7 +14241,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (unspec:DI [(const_int 0)] UNSPEC_TP) (match_operand:DI 1 "register_operand" "0"))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}" [(set_attr "type" "alu") @@ -14881,7 +14890,7 @@ (set (match_operand:XF 1 "register_operand" "=u") (unspec:XF [(match_dup 2) (match_dup 3)] UNSPEC_FPREM_U)) - (set (reg:CCFP 18) + (set (reg:CCFP FPSR_REG) (unspec:CCFP [(const_int 0)] UNSPEC_NOP))] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_unsafe_math_optimizations" @@ -14964,7 +14973,7 @@ (set (match_operand:XF 1 "register_operand" "=u") (unspec:XF [(match_dup 2) (match_dup 3)] UNSPEC_FPREM1_U)) - (set (reg:CCFP 18) + (set (reg:CCFP FPSR_REG) (unspec:CCFP [(const_int 0)] UNSPEC_NOP))] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_unsafe_math_optimizations" @@ -15937,7 +15946,7 @@ (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))]) (parallel [(set (match_operand:SI 0 "register_operand" "") (fix:SI (match_dup 3))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_unsafe_math_optimizations" { @@ -16328,7 +16337,7 @@ ;; Block operation instructions (define_insn "cld" - [(set (reg:SI 19) (const_int 0))] + [(set (reg:SI DIRFLAG_REG) (const_int 0))] "" "cld" [(set_attr "type" "cld")]) @@ -16366,9 +16375,9 @@ [(set (match_dup 4) (match_operand 3 "memory_operand" "")) (set (match_operand 1 "memory_operand" "") (match_dup 4)) (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5)) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6)) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" { rtx adjust = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[1]))); @@ -16396,7 +16405,7 @@ (match_operand 4 "" "")) (set (match_operand 2 "register_operand" "") (match_operand 5 "" "")) - (use (reg:SI 19))])] + (use (reg:SI DIRFLAG_REG))])] "TARGET_SINGLE_STRINGOP || optimize_size" "") @@ -16409,7 +16418,7 @@ (set (match_operand:DI 1 "register_operand" "=S") (plus:DI (match_dup 3) (const_int 8))) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" "movsq" [(set_attr "type" "str") @@ -16425,7 +16434,7 @@ (set (match_operand:SI 1 "register_operand" "=S") (plus:SI (match_dup 3) (const_int 4))) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" "{movsl|movsd}" [(set_attr "type" "str") @@ -16441,7 +16450,7 @@ (set (match_operand:DI 1 "register_operand" "=S") (plus:DI (match_dup 3) (const_int 4))) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" "{movsl|movsd}" [(set_attr "type" "str") @@ -16457,7 +16466,7 @@ (set (match_operand:SI 1 "register_operand" "=S") (plus:SI (match_dup 3) (const_int 2))) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" "movsw" [(set_attr "type" "str") @@ -16473,7 +16482,7 @@ (set (match_operand:DI 1 "register_operand" "=S") (plus:DI (match_dup 3) (const_int 2))) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" "movsw" [(set_attr "type" "str") @@ -16489,7 +16498,7 @@ (set (match_operand:SI 1 "register_operand" "=S") (plus:SI (match_dup 3) (const_int 1))) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" "movsb" [(set_attr "type" "str") @@ -16505,7 +16514,7 @@ (set (match_operand:DI 1 "register_operand" "=S") (plus:DI (match_dup 3) (const_int 1))) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" "movsb" [(set_attr "type" "str") @@ -16521,7 +16530,7 @@ (set (match_operand 1 "memory_operand" "") (match_operand 3 "memory_operand" "")) (use (match_dup 4)) - (use (reg:SI 19))])] + (use (reg:SI DIRFLAG_REG))])] "" "") @@ -16537,7 +16546,7 @@ (set (mem:BLK (match_dup 3)) (mem:BLK (match_dup 4))) (use (match_dup 5)) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "TARGET_64BIT" "{rep\;movsq|rep movsq}" [(set_attr "type" "str") @@ -16557,7 +16566,7 @@ (set (mem:BLK (match_dup 3)) (mem:BLK (match_dup 4))) (use (match_dup 5)) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "!TARGET_64BIT" "{rep\;movsl|rep movsd}" [(set_attr "type" "str") @@ -16577,7 +16586,7 @@ (set (mem:BLK (match_dup 3)) (mem:BLK (match_dup 4))) (use (match_dup 5)) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "TARGET_64BIT" "{rep\;movsl|rep movsd}" [(set_attr "type" "str") @@ -16595,7 +16604,7 @@ (set (mem:BLK (match_dup 3)) (mem:BLK (match_dup 4))) (use (match_dup 5)) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "!TARGET_64BIT" "{rep\;movsb|rep movsb}" [(set_attr "type" "str") @@ -16613,7 +16622,7 @@ (set (mem:BLK (match_dup 3)) (mem:BLK (match_dup 4))) (use (match_dup 5)) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "TARGET_64BIT" "{rep\;movsb|rep movsb}" [(set_attr "type" "str") @@ -16653,7 +16662,7 @@ (match_operand 2 "register_operand" "")) (parallel [(set (match_operand 0 "register_operand" "") (match_dup 3)) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" { if (GET_MODE (operands[1]) != GET_MODE (operands[2])) @@ -16677,7 +16686,7 @@ (match_operand 2 "register_operand" "")) (set (match_operand 0 "register_operand" "") (match_operand 3 "" "")) - (use (reg:SI 19))])] + (use (reg:SI DIRFLAG_REG))])] "TARGET_SINGLE_STRINGOP || optimize_size" "") @@ -16687,7 +16696,7 @@ (set (match_operand:DI 0 "register_operand" "=D") (plus:DI (match_dup 1) (const_int 8))) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" "stosq" [(set_attr "type" "str") @@ -16700,7 +16709,7 @@ (set (match_operand:SI 0 "register_operand" "=D") (plus:SI (match_dup 1) (const_int 4))) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" "{stosl|stosd}" [(set_attr "type" "str") @@ -16713,7 +16722,7 @@ (set (match_operand:DI 0 "register_operand" "=D") (plus:DI (match_dup 1) (const_int 4))) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" "{stosl|stosd}" [(set_attr "type" "str") @@ -16726,7 +16735,7 @@ (set (match_operand:SI 0 "register_operand" "=D") (plus:SI (match_dup 1) (const_int 2))) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" "stosw" [(set_attr "type" "str") @@ -16739,7 +16748,7 @@ (set (match_operand:DI 0 "register_operand" "=D") (plus:DI (match_dup 1) (const_int 2))) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" "stosw" [(set_attr "type" "str") @@ -16752,7 +16761,7 @@ (set (match_operand:SI 0 "register_operand" "=D") (plus:SI (match_dup 1) (const_int 1))) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" "stosb" [(set_attr "type" "str") @@ -16765,7 +16774,7 @@ (set (match_operand:DI 0 "register_operand" "=D") (plus:DI (match_dup 1) (const_int 1))) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)" "stosb" [(set_attr "type" "str") @@ -16779,7 +16788,7 @@ (set (match_operand 2 "memory_operand" "") (const_int 0)) (use (match_operand 3 "register_operand" "")) (use (match_dup 1)) - (use (reg:SI 19))])] + (use (reg:SI DIRFLAG_REG))])] "" "") @@ -16793,7 +16802,7 @@ (const_int 0)) (use (match_operand:DI 2 "register_operand" "a")) (use (match_dup 4)) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "TARGET_64BIT" "{rep\;stosq|rep stosq}" [(set_attr "type" "str") @@ -16811,7 +16820,7 @@ (const_int 0)) (use (match_operand:SI 2 "register_operand" "a")) (use (match_dup 4)) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "!TARGET_64BIT" "{rep\;stosl|rep stosd}" [(set_attr "type" "str") @@ -16829,7 +16838,7 @@ (const_int 0)) (use (match_operand:SI 2 "register_operand" "a")) (use (match_dup 4)) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "TARGET_64BIT" "{rep\;stosl|rep stosd}" [(set_attr "type" "str") @@ -16846,7 +16855,7 @@ (const_int 0)) (use (match_operand:QI 2 "register_operand" "a")) (use (match_dup 4)) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "!TARGET_64BIT" "{rep\;stosb|rep stosb}" [(set_attr "type" "str") @@ -16863,7 +16872,7 @@ (const_int 0)) (use (match_operand:QI 2 "register_operand" "a")) (use (match_dup 4)) - (use (reg:SI 19))] + (use (reg:SI DIRFLAG_REG))] "TARGET_64BIT" "{rep\;stosb|rep stosb}" [(set_attr "type" "str") @@ -16939,13 +16948,13 @@ (define_expand "cmpintqi" [(set (match_dup 1) - (gtu:QI (reg:CC 17) (const_int 0))) + (gtu:QI (reg:CC FLAGS_REG) (const_int 0))) (set (match_dup 2) - (ltu:QI (reg:CC 17) (const_int 0))) + (ltu:QI (reg:CC FLAGS_REG) (const_int 0))) (parallel [(set (match_operand:QI 0 "register_operand" "") (minus:QI (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "operands[1] = gen_reg_rtx (QImode); operands[2] = gen_reg_rtx (QImode);") @@ -16954,12 +16963,12 @@ ;; zero. Emit extra code to make sure that a zero-length compare is EQ. (define_expand "cmpstrqi_nz_1" - [(parallel [(set (reg:CC 17) + [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_operand 4 "memory_operand" "") (match_operand 5 "memory_operand" ""))) (use (match_operand 2 "register_operand" "")) (use (match_operand:SI 3 "immediate_operand" "")) - (use (reg:SI 19)) + (use (reg:SI DIRFLAG_REG)) (clobber (match_operand 0 "register_operand" "")) (clobber (match_operand 1 "register_operand" "")) (clobber (match_dup 2))])] @@ -16967,12 +16976,12 @@ "") (define_insn "*cmpstrqi_nz_1" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0")) (mem:BLK (match_operand:SI 5 "register_operand" "1")))) (use (match_operand:SI 6 "register_operand" "2")) (use (match_operand:SI 3 "immediate_operand" "i")) - (use (reg:SI 19)) + (use (reg:SI DIRFLAG_REG)) (clobber (match_operand:SI 0 "register_operand" "=S")) (clobber (match_operand:SI 1 "register_operand" "=D")) (clobber (match_operand:SI 2 "register_operand" "=c"))] @@ -16983,12 +16992,12 @@ (set_attr "prefix_rep" "1")]) (define_insn "*cmpstrqi_nz_rex_1" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0")) (mem:BLK (match_operand:DI 5 "register_operand" "1")))) (use (match_operand:DI 6 "register_operand" "2")) (use (match_operand:SI 3 "immediate_operand" "i")) - (use (reg:SI 19)) + (use (reg:SI DIRFLAG_REG)) (clobber (match_operand:DI 0 "register_operand" "=S")) (clobber (match_operand:DI 1 "register_operand" "=D")) (clobber (match_operand:DI 2 "register_operand" "=c"))] @@ -17001,15 +17010,15 @@ ;; The same, but the count is not known to not be zero. (define_expand "cmpstrqi_1" - [(parallel [(set (reg:CC 17) + [(parallel [(set (reg:CC FLAGS_REG) (if_then_else:CC (ne (match_operand 2 "register_operand" "") (const_int 0)) (compare:CC (match_operand 4 "memory_operand" "") (match_operand 5 "memory_operand" "")) (const_int 0))) (use (match_operand:SI 3 "immediate_operand" "")) - (use (reg:CC 17)) - (use (reg:SI 19)) + (use (reg:CC FLAGS_REG)) + (use (reg:SI DIRFLAG_REG)) (clobber (match_operand 0 "register_operand" "")) (clobber (match_operand 1 "register_operand" "")) (clobber (match_dup 2))])] @@ -17017,15 +17026,15 @@ "") (define_insn "*cmpstrqi_1" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2") (const_int 0)) (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0")) (mem:BLK (match_operand:SI 5 "register_operand" "1"))) (const_int 0))) (use (match_operand:SI 3 "immediate_operand" "i")) - (use (reg:CC 17)) - (use (reg:SI 19)) + (use (reg:CC FLAGS_REG)) + (use (reg:SI DIRFLAG_REG)) (clobber (match_operand:SI 0 "register_operand" "=S")) (clobber (match_operand:SI 1 "register_operand" "=D")) (clobber (match_operand:SI 2 "register_operand" "=c"))] @@ -17036,15 +17045,15 @@ (set_attr "prefix_rep" "1")]) (define_insn "*cmpstrqi_rex_1" - [(set (reg:CC 17) + [(set (reg:CC FLAGS_REG) (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2") (const_int 0)) (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0")) (mem:BLK (match_operand:DI 5 "register_operand" "1"))) (const_int 0))) (use (match_operand:SI 3 "immediate_operand" "i")) - (use (reg:CC 17)) - (use (reg:SI 19)) + (use (reg:CC FLAGS_REG)) + (use (reg:SI DIRFLAG_REG)) (clobber (match_operand:DI 0 "register_operand" "=S")) (clobber (match_operand:DI 1 "register_operand" "=D")) (clobber (match_operand:DI 2 "register_operand" "=c"))] @@ -17082,9 +17091,9 @@ (define_expand "strlenqi_1" [(parallel [(set (match_operand 0 "register_operand" "") (match_operand 2 "" "")) - (use (reg:SI 19)) + (use (reg:SI DIRFLAG_REG)) (clobber (match_operand 1 "register_operand" "")) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "") @@ -17094,9 +17103,9 @@ (match_operand:QI 2 "register_operand" "a") (match_operand:SI 3 "immediate_operand" "i") (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS)) - (use (reg:SI 19)) + (use (reg:SI DIRFLAG_REG)) (clobber (match_operand:SI 1 "register_operand" "=D")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT" "repnz{\;| }scasb" [(set_attr "type" "str") @@ -17109,9 +17118,9 @@ (match_operand:QI 2 "register_operand" "a") (match_operand:DI 3 "immediate_operand" "i") (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS)) - (use (reg:SI 19)) + (use (reg:SI DIRFLAG_REG)) (clobber (match_operand:DI 1 "register_operand" "=D")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "repnz{\;| }scasb" [(set_attr "type" "str") @@ -17134,30 +17143,30 @@ ;; This one handles cmpstr*_nz_1... (define_peephole2 [(parallel[ - (set (reg:CC 17) + (set (reg:CC FLAGS_REG) (compare:CC (mem:BLK (match_operand 4 "register_operand" "")) (mem:BLK (match_operand 5 "register_operand" "")))) (use (match_operand 6 "register_operand" "")) (use (match_operand:SI 3 "immediate_operand" "")) - (use (reg:SI 19)) + (use (reg:SI DIRFLAG_REG)) (clobber (match_operand 0 "register_operand" "")) (clobber (match_operand 1 "register_operand" "")) (clobber (match_operand 2 "register_operand" ""))]) (set (match_operand:QI 7 "register_operand" "") - (gtu:QI (reg:CC 17) (const_int 0))) + (gtu:QI (reg:CC FLAGS_REG) (const_int 0))) (set (match_operand:QI 8 "register_operand" "") - (ltu:QI (reg:CC 17) (const_int 0))) + (ltu:QI (reg:CC FLAGS_REG) (const_int 0))) (set (reg 17) (compare (match_dup 7) (match_dup 8))) ] "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])" [(parallel[ - (set (reg:CC 17) + (set (reg:CC FLAGS_REG) (compare:CC (mem:BLK (match_dup 4)) (mem:BLK (match_dup 5)))) (use (match_dup 6)) (use (match_dup 3)) - (use (reg:SI 19)) + (use (reg:SI DIRFLAG_REG)) (clobber (match_dup 0)) (clobber (match_dup 1)) (clobber (match_dup 2))])] @@ -17166,36 +17175,36 @@ ;; ...and this one handles cmpstr*_1. (define_peephole2 [(parallel[ - (set (reg:CC 17) + (set (reg:CC FLAGS_REG) (if_then_else:CC (ne (match_operand 6 "register_operand" "") (const_int 0)) (compare:CC (mem:BLK (match_operand 4 "register_operand" "")) (mem:BLK (match_operand 5 "register_operand" ""))) (const_int 0))) (use (match_operand:SI 3 "immediate_operand" "")) - (use (reg:CC 17)) - (use (reg:SI 19)) + (use (reg:CC FLAGS_REG)) + (use (reg:SI DIRFLAG_REG)) (clobber (match_operand 0 "register_operand" "")) (clobber (match_operand 1 "register_operand" "")) (clobber (match_operand 2 "register_operand" ""))]) (set (match_operand:QI 7 "register_operand" "") - (gtu:QI (reg:CC 17) (const_int 0))) + (gtu:QI (reg:CC FLAGS_REG) (const_int 0))) (set (match_operand:QI 8 "register_operand" "") - (ltu:QI (reg:CC 17) (const_int 0))) + (ltu:QI (reg:CC FLAGS_REG) (const_int 0))) (set (reg 17) (compare (match_dup 7) (match_dup 8))) ] "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])" [(parallel[ - (set (reg:CC 17) + (set (reg:CC FLAGS_REG) (if_then_else:CC (ne (match_dup 6) (const_int 0)) (compare:CC (mem:BLK (match_dup 4)) (mem:BLK (match_dup 5))) (const_int 0))) (use (match_dup 3)) - (use (reg:CC 17)) - (use (reg:SI 19)) + (use (reg:CC FLAGS_REG)) + (use (reg:SI DIRFLAG_REG)) (clobber (match_dup 0)) (clobber (match_dup 1)) (clobber (match_dup 2))])] @@ -17218,7 +17227,7 @@ (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "") (const_int -1) (const_int 0))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "sbb{q}\t%0, %0" ; Since we don't have the proper number of operands for an alu insn, @@ -17261,7 +17270,7 @@ (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "") (const_int -1) (const_int 0))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "" "sbb{l}\t%0, %0" ; Since we don't have the proper number of operands for an alu insn, @@ -17447,7 +17456,7 @@ (match_operand:SF 2 "nonimmediate_operand" "")) (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_SSE" "") @@ -17457,7 +17466,7 @@ (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0")) (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_SSE && TARGET_IEEE_FP" "#") @@ -17467,7 +17476,7 @@ (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x")) (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_SSE && !TARGET_IEEE_FP && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "#") @@ -17478,7 +17487,7 @@ (match_operand:SF 2 "nonimmediate_operand" "")) (match_operand:SF 3 "register_operand" "") (match_operand:SF 4 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "SSE_REG_P (operands[0]) && reload_completed && ((operands_match_p (operands[1], operands[3]) && operands_match_p (operands[2], operands[4])) @@ -17531,17 +17540,17 @@ (match_operand:SF 2 "register_operand" "")) (match_operand:SF 3 "register_operand" "") (match_operand:SF 4 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && ((operands_match_p (operands[1], operands[3]) && operands_match_p (operands[2], operands[4])) || (operands_match_p (operands[1], operands[4]) && operands_match_p (operands[2], operands[3])))" - [(set (reg:CCFP 17) + [(set (reg:CCFP FLAGS_REG) (compare:CCFP (match_dup 2) (match_dup 1))) (set (match_dup 0) - (if_then_else:SF (ge (reg:CCFP 17) (const_int 0)) + (if_then_else:SF (ge (reg:CCFP FLAGS_REG) (const_int 0)) (match_dup 1) (match_dup 2)))]) @@ -17563,7 +17572,7 @@ (match_operand:DF 2 "nonimmediate_operand" "")) (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_SSE2 && TARGET_SSE_MATH" "#") @@ -17573,7 +17582,7 @@ (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0")) (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH" "#") @@ -17583,7 +17592,7 @@ (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y")) (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "#") @@ -17594,7 +17603,7 @@ (match_operand:DF 2 "nonimmediate_operand" "")) (match_operand:DF 3 "register_operand" "") (match_operand:DF 4 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "SSE_REG_P (operands[0]) && reload_completed && ((operands_match_p (operands[1], operands[3]) && operands_match_p (operands[2], operands[4])) @@ -17613,17 +17622,17 @@ (match_operand:DF 2 "register_operand" "")) (match_operand:DF 3 "register_operand" "") (match_operand:DF 4 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && ((operands_match_p (operands[1], operands[3]) && operands_match_p (operands[2], operands[4])) || (operands_match_p (operands[1], operands[4]) && operands_match_p (operands[2], operands[3])))" - [(set (reg:CCFP 17) + [(set (reg:CCFP FLAGS_REG) (compare:CCFP (match_dup 2) (match_dup 1))) (set (match_dup 0) - (if_then_else:DF (ge (reg:CCFP 17) (const_int 0)) + (if_then_else:DF (ge (reg:CCFP FLAGS_REG) (const_int 0)) (match_dup 1) (match_dup 2)))]) @@ -17645,7 +17654,7 @@ (match_operand:SF 2 "nonimmediate_operand" "")) (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_SSE" "#") @@ -17655,7 +17664,7 @@ (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0")) (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_SSE && TARGET_IEEE_FP" "#") @@ -17665,7 +17674,7 @@ (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x")) (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_SSE && !TARGET_IEEE_FP && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "#") @@ -17676,7 +17685,7 @@ (match_operand:SF 2 "nonimmediate_operand" "")) (match_operand:SF 3 "register_operand" "") (match_operand:SF 4 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "SSE_REG_P (operands[0]) && reload_completed && ((operands_match_p (operands[1], operands[3]) && operands_match_p (operands[2], operands[4])) @@ -17694,17 +17703,17 @@ (match_operand:SF 2 "register_operand" "")) (match_operand:SF 3 "register_operand" "") (match_operand:SF 4 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && ((operands_match_p (operands[1], operands[3]) && operands_match_p (operands[2], operands[4])) || (operands_match_p (operands[1], operands[4]) && operands_match_p (operands[2], operands[3])))" - [(set (reg:CCFP 17) + [(set (reg:CCFP FLAGS_REG) (compare:CCFP (match_dup 1) (match_dup 2))) (set (match_dup 0) - (if_then_else:SF (gt (reg:CCFP 17) (const_int 0)) + (if_then_else:SF (gt (reg:CCFP FLAGS_REG) (const_int 0)) (match_dup 1) (match_dup 2)))]) @@ -17726,7 +17735,7 @@ (match_operand:DF 2 "nonimmediate_operand" "")) (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_SSE2 && TARGET_SSE_MATH" "#") @@ -17736,7 +17745,7 @@ (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0")) (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP" "#") @@ -17746,7 +17755,7 @@ (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y")) (match_dup 1) (match_dup 2))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "#") @@ -17757,7 +17766,7 @@ (match_operand:DF 2 "nonimmediate_operand" "")) (match_operand:DF 3 "register_operand" "") (match_operand:DF 4 "nonimmediate_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "SSE_REG_P (operands[0]) && reload_completed && ((operands_match_p (operands[1], operands[3]) && operands_match_p (operands[2], operands[4])) @@ -17775,17 +17784,17 @@ (match_operand:DF 2 "register_operand" "")) (match_operand:DF 3 "register_operand" "") (match_operand:DF 4 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "reload_completed && ((operands_match_p (operands[1], operands[3]) && operands_match_p (operands[2], operands[4])) || (operands_match_p (operands[1], operands[4]) && operands_match_p (operands[2], operands[3])))" - [(set (reg:CCFP 17) + [(set (reg:CCFP FLAGS_REG) (compare:CCFP (match_dup 1) (match_dup 2))) (set (match_dup 0) - (if_then_else:DF (gt (reg:CCFP 17) (const_int 0)) + (if_then_else:DF (gt (reg:CCFP FLAGS_REG) (const_int 0)) (match_dup 1) (match_dup 2)))]) @@ -17815,7 +17824,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r") (plus:SI (match_operand:SI 1 "register_operand" "0,r") (match_operand:SI 2 "immediate_operand" "i,i"))) - (clobber (reg:CC 17)) + (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))] "!TARGET_64BIT" { @@ -17856,7 +17865,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (plus:DI (match_operand:DI 1 "register_operand" "0,r") (match_operand:DI 2 "x86_64_immediate_operand" "e,e"))) - (clobber (reg:CC 17)) + (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))] "TARGET_64BIT" { @@ -17900,7 +17909,7 @@ (plus:DI (match_operand:DI 1 "register_operand" "0,r") (match_operand:DI 3 "immediate_operand" "i,i"))) (use (match_operand:DI 2 "register_operand" "r,r")) - (clobber (reg:CC 17)) + (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))] "TARGET_64BIT" { @@ -17936,7 +17945,7 @@ (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx") (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx"))) (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_SSE && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM) /* Avoid combine from being smart and converting min/max @@ -17956,7 +17965,7 @@ (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx") (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx"))) (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_SSE && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" "#") @@ -17969,7 +17978,7 @@ (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY") (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY"))) (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_SSE2 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM) /* Avoid combine from being smart and converting min/max @@ -17989,7 +17998,7 @@ (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY") (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY"))) (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_SSE && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)" "#") @@ -18003,7 +18012,7 @@ (match_operand 2 "nonimmediate_operand" "") (match_operand 3 "nonimmediate_operand" ""))) (clobber (match_operand 6 "" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!SSE_REG_P (operands[0]) && reload_completed && VALID_SSE_REG_MODE (GET_MODE (operands[0]))" [(const_int 0)] @@ -18029,7 +18038,7 @@ (match_operand:SF 2 "register_operand" "") (match_operand:SF 3 "register_operand" ""))) (clobber (match_operand 6 "" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "SSE_REG_P (operands[0]) && reload_completed" [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)])) (set (match_dup 2) (and:V4SF (match_dup 2) @@ -18067,7 +18076,7 @@ (match_operand:DF 2 "register_operand" "") (match_operand:DF 3 "register_operand" ""))) (clobber (match_operand 6 "" "")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "SSE_REG_P (operands[0]) && reload_completed" [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)])) (set (match_dup 2) (and:V2DF (match_dup 2) @@ -18302,9 +18311,9 @@ (define_insn "allocate_stack_worker_1" [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE) - (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0))) + (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0))) (clobber (match_scratch:SI 1 "=0")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_STACK_PROBE" "call\t__alloca" [(set_attr "type" "multi") @@ -18313,17 +18322,17 @@ (define_expand "allocate_stack_worker_postreload" [(parallel [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE) - (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0))) + (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0))) (clobber (match_dup 0)) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "") (define_insn "allocate_stack_worker_rex64" [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE) - (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0))) + (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0))) (clobber (match_scratch:DI 1 "=0")) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_STACK_PROBE" "call\t__alloca" [(set_attr "type" "multi") @@ -18332,20 +18341,20 @@ (define_expand "allocate_stack_worker_rex64_postreload" [(parallel [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE) - (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0))) + (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0))) (clobber (match_dup 0)) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "" "") (define_expand "allocate_stack" [(parallel [(set (match_operand:SI 0 "register_operand" "=r") - (minus:SI (reg:SI 7) + (minus:SI (reg:SI SP_REG) (match_operand:SI 1 "general_operand" ""))) - (clobber (reg:CC 17))]) - (parallel [(set (reg:SI 7) - (minus:SI (reg:SI 7) (match_dup 1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))]) + (parallel [(set (reg:SI SP_REG) + (minus:SI (reg:SI SP_REG) (match_dup 1))) + (clobber (reg:CC FLAGS_REG))])] "TARGET_STACK_PROBE" { #ifdef CHECK_STACK_LIMIT @@ -18377,7 +18386,7 @@ (match_operator 3 "promotable_binary_operator" [(match_operand 1 "register_operand" "") (match_operand 2 "aligned_operand" "")])) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "! TARGET_PARTIAL_REG_STALL && reload_completed && ((GET_MODE (operands[0]) == HImode && ((!optimize_size && !TARGET_FAST_PREFIX) @@ -18387,7 +18396,7 @@ && (TARGET_PROMOTE_QImode || optimize_size)))" [(parallel [(set (match_dup 0) (match_op_dup 3 [(match_dup 1) (match_dup 2)])) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[0] = gen_lowpart (SImode, operands[0]); operands[1] = gen_lowpart (SImode, operands[1]); if (GET_CODE (operands[3]) != ASHIFT) @@ -18411,7 +18420,7 @@ && ! optimize_size && ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX) || (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))" - [(parallel [(set (reg:CCNO 17) + [(parallel [(set (reg:CCNO FLAGS_REG) (compare:CCNO (and:SI (match_dup 1) (match_dup 2)) (const_int 0))) (set (match_dup 0) @@ -18437,7 +18446,7 @@ && ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode) && ! TARGET_FAST_PREFIX && ! optimize_size" - [(set (reg:CCNO 17) + [(set (reg:CCNO FLAGS_REG) (compare:CCNO (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))] "operands[1] @@ -18449,14 +18458,14 @@ (define_split [(set (match_operand 0 "register_operand" "") (neg (match_operand 1 "register_operand" ""))) - (clobber (reg:CC 17))] + (clobber (reg:CC FLAGS_REG))] "! TARGET_PARTIAL_REG_STALL && reload_completed && (GET_MODE (operands[0]) == HImode || (GET_MODE (operands[0]) == QImode && (TARGET_PROMOTE_QImode || optimize_size)))" [(parallel [(set (match_dup 0) (neg:SI (match_dup 1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[0] = gen_lowpart (SImode, operands[0]); operands[1] = gen_lowpart (SImode, operands[1]);") @@ -18552,7 +18561,7 @@ && get_attr_length (insn) >= ix86_cost->large_insn && peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (match_dup 1) (const_int 0)) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (set (match_dup 0) (match_dup 1))] "") @@ -18566,7 +18575,7 @@ && get_attr_length (insn) >= ix86_cost->large_insn && peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (match_dup 2) (const_int 0)) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (set (match_dup 0) (match_dup 1))] "operands[2] = gen_lowpart (SImode, operands[1]);") @@ -18580,7 +18589,7 @@ && get_attr_length (insn) >= ix86_cost->large_insn && peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (match_dup 2) (const_int 0)) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (set (match_dup 0) (match_dup 1))] "operands[2] = gen_lowpart (SImode, operands[1]);") @@ -18623,7 +18632,7 @@ (match_scratch:SI 3 "r")] "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size" [(set (match_dup 3) (match_dup 0)) - (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))] + (set (reg:CCNO FLAGS_REG) (compare:CCNO (match_dup 3) (const_int 0)))] "") ;; NOT is not pairable on Pentium, while XOR is, but one byte longer. @@ -18648,7 +18657,7 @@ || (TARGET_K6 && long_memory_operand (operands[0], SImode)))" [(parallel [(set (match_dup 0) (xor:SI (match_dup 1) (const_int -1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") (define_peephole2 @@ -18662,7 +18671,7 @@ || (TARGET_K6 && long_memory_operand (operands[0], HImode)))" [(parallel [(set (match_dup 0) (xor:HI (match_dup 1) (const_int -1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") (define_peephole2 @@ -18676,7 +18685,7 @@ || (TARGET_K6 && long_memory_operand (operands[0], QImode)))" [(parallel [(set (match_dup 0) (xor:QI (match_dup 1) (const_int -1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") ;; Non pairable "test imm, reg" instructions can be translated to @@ -18697,7 +18706,7 @@ && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))) && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" [(parallel - [(set (reg:CCNO 17) + [(set (reg:CCNO FLAGS_REG) (compare:CCNO (and:SI (match_dup 0) (match_dup 1)) (const_int 0))) @@ -18718,7 +18727,7 @@ && true_regnum (operands[0]) != 0 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" [(parallel - [(set (reg:CCNO 17) + [(set (reg:CCNO FLAGS_REG) (compare:CCNO (and:QI (match_dup 0) (match_dup 1)) (const_int 0))) @@ -18740,7 +18749,7 @@ && ix86_match_ccmode (insn, CCNOmode) && true_regnum (operands[0]) != 0 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" - [(parallel [(set (reg:CCNO 17) + [(parallel [(set (reg:CCNO FLAGS_REG) (compare:CCNO (and:SI (zero_extract:SI @@ -18767,12 +18776,12 @@ (match_operator:SI 3 "arith_or_logical_operator" [(match_dup 0) (match_operand:SI 1 "memory_operand" "")])) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "! optimize_size && ! TARGET_READ_MODIFY" [(set (match_dup 2) (match_dup 1)) (parallel [(set (match_dup 0) (match_op_dup 3 [(match_dup 0) (match_dup 2)])) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") (define_peephole2 @@ -18781,12 +18790,12 @@ (match_operator:SI 3 "arith_or_logical_operator" [(match_operand:SI 1 "memory_operand" "") (match_dup 0)])) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "! optimize_size && ! TARGET_READ_MODIFY" [(set (match_dup 2) (match_dup 1)) (parallel [(set (match_dup 0) (match_op_dup 3 [(match_dup 2) (match_dup 0)])) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") ; Don't do logical operations with memory outputs @@ -18801,12 +18810,12 @@ (match_operator:SI 3 "arith_or_logical_operator" [(match_dup 0) (match_operand:SI 1 "nonmemory_operand" "")])) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "! optimize_size && ! TARGET_READ_MODIFY_WRITE" [(set (match_dup 2) (match_dup 0)) (parallel [(set (match_dup 2) (match_op_dup 3 [(match_dup 2) (match_dup 1)])) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (set (match_dup 0) (match_dup 2))] "") @@ -18816,12 +18825,12 @@ (match_operator:SI 3 "arith_or_logical_operator" [(match_operand:SI 1 "nonmemory_operand" "") (match_dup 0)])) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "! optimize_size && ! TARGET_READ_MODIFY_WRITE" [(set (match_dup 2) (match_dup 0)) (parallel [(set (match_dup 2) (match_op_dup 3 [(match_dup 1) (match_dup 2)])) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (set (match_dup 0) (match_dup 2))] "") @@ -18836,7 +18845,7 @@ && (! TARGET_USE_MOV0 || optimize_size) && peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (match_dup 0) (const_int 0)) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode, operands[0]);") @@ -18848,7 +18857,7 @@ && (! TARGET_USE_MOV0 || optimize_size) && peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0)) - (clobber (reg:CC 17))])]) + (clobber (reg:CC FLAGS_REG))])]) ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg. (define_peephole2 @@ -18860,7 +18869,7 @@ && (optimize_size || TARGET_PENTIUM) && peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (match_dup 0) (const_int -1)) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode, operands[0]);") @@ -18872,7 +18881,7 @@ (match_operand:SI 1 "nonmemory_operand" "")))] "peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") (define_peephole2 @@ -18881,7 +18890,7 @@ (match_operand:DI 2 "nonmemory_operand" "")) 0))] "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])" [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[2] = gen_lowpart (SImode, operands[2]);") (define_peephole2 @@ -18890,7 +18899,7 @@ (match_operand:DI 1 "x86_64_general_operand" "")))] "peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") (define_peephole2 @@ -18900,7 +18909,7 @@ "exact_log2 (INTVAL (operands[1])) >= 0 && peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));") (define_peephole2 @@ -18910,7 +18919,7 @@ "exact_log2 (INTVAL (operands[1])) >= 0 && peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));") (define_peephole2 @@ -18921,7 +18930,7 @@ && REGNO (operands[0]) == REGNO (operands[1]) && peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));") ;; The ESP adjustments can be done by the push and pop instructions. Resulting @@ -18945,52 +18954,52 @@ (define_peephole2 [(match_scratch:SI 0 "r") - (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4))) - (clobber (reg:CC 17)) + (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4))) + (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_SUB_ESP_4" [(clobber (match_dup 0)) - (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) + (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0)) (clobber (mem:BLK (scratch)))])]) (define_peephole2 [(match_scratch:SI 0 "r") - (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) - (clobber (reg:CC 17)) + (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8))) + (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_SUB_ESP_8" [(clobber (match_dup 0)) - (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) - (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) + (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0)) + (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0)) (clobber (mem:BLK (scratch)))])]) ;; Convert esp subtractions to push. (define_peephole2 [(match_scratch:SI 0 "r") - (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4))) - (clobber (reg:CC 17))])] + (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4))) + (clobber (reg:CC FLAGS_REG))])] "optimize_size || !TARGET_SUB_ESP_4" [(clobber (match_dup 0)) - (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))]) + (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))]) (define_peephole2 [(match_scratch:SI 0 "r") - (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8))) - (clobber (reg:CC 17))])] + (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8))) + (clobber (reg:CC FLAGS_REG))])] "optimize_size || !TARGET_SUB_ESP_8" [(clobber (match_dup 0)) - (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0)) - (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))]) + (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0)) + (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))]) ;; Convert epilogue deallocator to pop. (define_peephole2 [(match_scratch:SI 0 "r") - (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) - (clobber (reg:CC 17)) + (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4))) + (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_ADD_ESP_4" - [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) - (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) + [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG))) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4))) (clobber (mem:BLK (scratch)))])] "") @@ -18999,38 +19008,38 @@ (define_peephole2 [(match_scratch:SI 0 "r") (match_scratch:SI 1 "r") - (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) - (clobber (reg:CC 17)) + (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8))) + (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_ADD_ESP_8" - [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) - (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) + [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG))) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4))) (clobber (mem:BLK (scratch)))]) - (parallel [(set (match_dup 1) (mem:SI (reg:SI 7))) - (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] + (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG))) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])] "") (define_peephole2 [(match_scratch:SI 0 "r") - (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) - (clobber (reg:CC 17)) + (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8))) + (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "optimize_size" - [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) - (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) + [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG))) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4))) (clobber (mem:BLK (scratch)))]) - (parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) - (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] + (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG))) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])] "") ;; Convert esp additions to pop. (define_peephole2 [(match_scratch:SI 0 "r") - (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4))) - (clobber (reg:CC 17))])] + (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4))) + (clobber (reg:CC FLAGS_REG))])] "" - [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) - (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] + [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG))) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])] "") ;; Two pops case is tricky, since pop causes dependency on destination register. @@ -19038,24 +19047,24 @@ (define_peephole2 [(match_scratch:SI 0 "r") (match_scratch:SI 1 "r") - (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) - (clobber (reg:CC 17))])] + (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8))) + (clobber (reg:CC FLAGS_REG))])] "" - [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) - (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))]) - (parallel [(set (match_dup 1) (mem:SI (reg:SI 7))) - (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] + [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG))) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))]) + (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG))) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])] "") (define_peephole2 [(match_scratch:SI 0 "r") - (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8))) - (clobber (reg:CC 17))])] + (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8))) + (clobber (reg:CC FLAGS_REG))])] "optimize_size" - [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) - (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))]) - (parallel [(set (match_dup 0) (mem:SI (reg:SI 7))) - (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])] + [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG))) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))]) + (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG))) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])] "") ;; Convert compares with 1 to shorter inc/dec operations when CF is not @@ -19066,7 +19075,7 @@ (match_operand:SI 1 "incdec_operand" "")))] "ix86_match_ccmode (insn, CCGCmode) && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" - [(parallel [(set (reg:CCGC 17) + [(parallel [(set (reg:CCGC FLAGS_REG) (compare:CCGC (match_dup 0) (match_dup 1))) (clobber (match_dup 0))])] @@ -19078,7 +19087,7 @@ (match_operand:HI 1 "incdec_operand" "")))] "ix86_match_ccmode (insn, CCGCmode) && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" - [(parallel [(set (reg:CCGC 17) + [(parallel [(set (reg:CCGC FLAGS_REG) (compare:CCGC (match_dup 0) (match_dup 1))) (clobber (match_dup 0))])] @@ -19090,7 +19099,7 @@ (match_operand:QI 1 "incdec_operand" "")))] "ix86_match_ccmode (insn, CCGCmode) && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" - [(parallel [(set (reg:CCGC 17) + [(parallel [(set (reg:CCGC FLAGS_REG) (compare:CCGC (match_dup 0) (match_dup 1))) (clobber (match_dup 0))])] @@ -19103,7 +19112,7 @@ (const_int 128)))] "ix86_match_ccmode (insn, CCGCmode) && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" - [(parallel [(set (reg:CCGC 17) + [(parallel [(set (reg:CCGC FLAGS_REG) (compare:CCGC (match_dup 0) (const_int 128))) (clobber (match_dup 0))])] @@ -19115,7 +19124,7 @@ (const_int 128)))] "ix86_match_ccmode (insn, CCGCmode) && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" - [(parallel [(set (reg:CCGC 17) + [(parallel [(set (reg:CCGC FLAGS_REG) (compare:CCGC (match_dup 0) (const_int 128))) (clobber (match_dup 0))])] @@ -19123,52 +19132,52 @@ (define_peephole2 [(match_scratch:DI 0 "r") - (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) - (clobber (reg:CC 17)) + (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8))) + (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_SUB_ESP_4" [(clobber (match_dup 0)) - (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) + (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0)) (clobber (mem:BLK (scratch)))])]) (define_peephole2 [(match_scratch:DI 0 "r") - (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) - (clobber (reg:CC 17)) + (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16))) + (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_SUB_ESP_8" [(clobber (match_dup 0)) - (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) - (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) + (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0)) + (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0)) (clobber (mem:BLK (scratch)))])]) ;; Convert esp subtractions to push. (define_peephole2 [(match_scratch:DI 0 "r") - (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8))) - (clobber (reg:CC 17))])] + (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8))) + (clobber (reg:CC FLAGS_REG))])] "optimize_size || !TARGET_SUB_ESP_4" [(clobber (match_dup 0)) - (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))]) + (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))]) (define_peephole2 [(match_scratch:DI 0 "r") - (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16))) - (clobber (reg:CC 17))])] + (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16))) + (clobber (reg:CC FLAGS_REG))])] "optimize_size || !TARGET_SUB_ESP_8" [(clobber (match_dup 0)) - (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0)) - (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))]) + (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0)) + (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))]) ;; Convert epilogue deallocator to pop. (define_peephole2 [(match_scratch:DI 0 "r") - (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) - (clobber (reg:CC 17)) + (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8))) + (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_ADD_ESP_4" - [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) - (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) + [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG))) + (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8))) (clobber (mem:BLK (scratch)))])] "") @@ -19177,38 +19186,38 @@ (define_peephole2 [(match_scratch:DI 0 "r") (match_scratch:DI 1 "r") - (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) - (clobber (reg:CC 17)) + (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16))) + (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "optimize_size || !TARGET_ADD_ESP_8" - [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) - (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) + [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG))) + (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8))) (clobber (mem:BLK (scratch)))]) - (parallel [(set (match_dup 1) (mem:DI (reg:DI 7))) - (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] + (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG))) + (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])] "") (define_peephole2 [(match_scratch:DI 0 "r") - (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) - (clobber (reg:CC 17)) + (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16))) + (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "optimize_size" - [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) - (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) + [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG))) + (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8))) (clobber (mem:BLK (scratch)))]) - (parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) - (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] + (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG))) + (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])] "") ;; Convert esp additions to pop. (define_peephole2 [(match_scratch:DI 0 "r") - (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8))) - (clobber (reg:CC 17))])] + (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8))) + (clobber (reg:CC FLAGS_REG))])] "" - [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) - (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] + [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG))) + (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])] "") ;; Two pops case is tricky, since pop causes dependency on destination register. @@ -19216,24 +19225,24 @@ (define_peephole2 [(match_scratch:DI 0 "r") (match_scratch:DI 1 "r") - (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) - (clobber (reg:CC 17))])] + (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16))) + (clobber (reg:CC FLAGS_REG))])] "" - [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) - (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))]) - (parallel [(set (match_dup 1) (mem:DI (reg:DI 7))) - (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] + [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG))) + (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))]) + (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG))) + (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])] "") (define_peephole2 [(match_scratch:DI 0 "r") - (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16))) - (clobber (reg:CC 17))])] + (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16))) + (clobber (reg:CC FLAGS_REG))])] "optimize_size" - [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) - (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))]) - (parallel [(set (match_dup 0) (mem:DI (reg:DI 7))) - (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])] + [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG))) + (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))]) + (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG))) + (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])] "") ;; Imul $32bit_imm, mem, reg is vector decoded, while @@ -19243,13 +19252,13 @@ (parallel [(set (match_operand:DI 0 "register_operand" "") (mult:DI (match_operand:DI 1 "memory_operand" "") (match_operand:DI 2 "immediate_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_K8 && !optimize_size && (GET_CODE (operands[2]) != CONST_INT || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))" [(set (match_dup 3) (match_dup 1)) (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") (define_peephole2 @@ -19257,13 +19266,13 @@ (parallel [(set (match_operand:SI 0 "register_operand" "") (mult:SI (match_operand:SI 1 "memory_operand" "") (match_operand:SI 2 "immediate_operand" ""))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_K8 && !optimize_size && (GET_CODE (operands[2]) != CONST_INT || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))" [(set (match_dup 3) (match_dup 1)) (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") (define_peephole2 @@ -19272,13 +19281,13 @@ (zero_extend:DI (mult:SI (match_operand:SI 1 "memory_operand" "") (match_operand:SI 2 "immediate_operand" "")))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "TARGET_K8 && !optimize_size && (GET_CODE (operands[2]) != CONST_INT || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))" [(set (match_dup 3) (match_dup 1)) (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2)))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] "") ;; imul $8/16bit_imm, regmem, reg is vector decoded. @@ -19289,13 +19298,13 @@ [(parallel [(set (match_operand:DI 0 "register_operand" "") (mult:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "const_int_operand" ""))) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (match_scratch:DI 3 "r")] "TARGET_K8 && !optimize_size && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" [(set (match_dup 3) (match_dup 2)) (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] { if (!rtx_equal_p (operands[0], operands[1])) emit_move_insn (operands[0], operands[1]); @@ -19305,13 +19314,13 @@ [(parallel [(set (match_operand:SI 0 "register_operand" "") (mult:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:SI 2 "const_int_operand" ""))) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (match_scratch:SI 3 "r")] "TARGET_K8 && !optimize_size && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" [(set (match_dup 3) (match_dup 2)) (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] { if (!rtx_equal_p (operands[0], operands[1])) emit_move_insn (operands[0], operands[1]); @@ -19321,12 +19330,12 @@ [(parallel [(set (match_operand:HI 0 "register_operand" "") (mult:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:HI 2 "immediate_operand" ""))) - (clobber (reg:CC 17))]) + (clobber (reg:CC FLAGS_REG))]) (match_scratch:HI 3 "r")] "TARGET_K8 && !optimize_size" [(set (match_dup 3) (match_dup 2)) (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3))) - (clobber (reg:CC 17))])] + (clobber (reg:CC FLAGS_REG))])] { if (!rtx_equal_p (operands[0], operands[1])) emit_move_insn (operands[0], operands[1]); @@ -19339,7 +19348,7 @@ [(set (match_operand 0 "" "") (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" "")) (match_operand:SI 2 "" ""))) - (set (reg:SI 7) (plus:SI (reg:SI 7) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 3 "immediate_operand" "")))] "!TARGET_64BIT" { @@ -19354,7 +19363,7 @@ [(set (match_operand 0 "" "") (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm")) (match_operand:SI 2 "" ""))) - (set (reg:SI 7) (plus:SI (reg:SI 7) + (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 3 "immediate_operand" "i")))] "!TARGET_64BIT" { @@ -19977,7 +19986,7 @@ (match_operand 1 "register_operand" ""))] "!TARGET_64BIT && reload_completed && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))" - [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 3))) + [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 3))) (set (match_dup 2) (match_dup 1))] "operands[2] = change_address (operands[0], GET_MODE (operands[0]), stack_pointer_rtx); @@ -19988,7 +19997,7 @@ (match_operand 1 "register_operand" ""))] "TARGET_64BIT && reload_completed && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))" - [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 3))) + [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 3))) (set (match_dup 2) (match_dup 1))] "operands[2] = change_address (operands[0], GET_MODE (operands[0]), stack_pointer_rtx); @@ -20868,7 +20877,7 @@ (set_attr "mode" "SF")]) (define_insn "sse_comi" - [(set (reg:CCFP 17) + [(set (reg:CCFP FLAGS_REG) (compare:CCFP (vec_select:SF (match_operand:V4SF 0 "register_operand" "x") (parallel [(const_int 0)])) @@ -20881,7 +20890,7 @@ (set_attr "mode" "SF")]) (define_insn "sse_ucomi" - [(set (reg:CCFPU 17) + [(set (reg:CCFPU FLAGS_REG) (compare:CCFPU (vec_select:SF (match_operand:V4SF 0 "register_operand" "x") (parallel [(const_int 0)])) @@ -22492,7 +22501,7 @@ (set_attr "mode" "DF")]) (define_insn "sse2_comi" - [(set (reg:CCFP 17) + [(set (reg:CCFP FLAGS_REG) (compare:CCFP (vec_select:DF (match_operand:V2DF 0 "register_operand" "x") (parallel [(const_int 0)])) @@ -22505,7 +22514,7 @@ (set_attr "mode" "DF")]) (define_insn "sse2_ucomi" - [(set (reg:CCFPU 17) + [(set (reg:CCFPU FLAGS_REG) (compare:CCFPU (vec_select:DF (match_operand:V2DF 0 "register_operand" "x") (parallel [(const_int 0)]))