diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6129ba21ca9..ebb09f23482 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,23 @@ +2013-09-06 James Greenhalgh + + * config/arm/types.md (type): Add "mrs" type. + * config/aarch64/aarch64.md + (aarch64_load_tp_hard): Make type "mrs". + * config/arm/arm.md + (load_tp_hard): Make type "mrs". + * config/arm/cortex-a15.md: Update with new attributes. + * config/arm/cortex-a5.md: Update with new attributes. + * config/arm/cortex-a53.md: Update with new attributes. + * config/arm/cortex-a7.md: Update with new attributes. + * config/arm/cortex-a8.md: Update with new attributes. + * config/arm/cortex-a9.md: Update with new attributes. + * config/arm/cortex-m4.md: Update with new attributes. + * config/arm/cortex-r4.md: Update with new attributes. + * config/arm/fa526.md: Update with new attributes. + * config/arm/fa606te.md: Update with new attributes. + * config/arm/fa626te.md: Update with new attributes. + * config/arm/fa726te.md: Update with new attributes. + 2013-09-06 James Greenhalgh * config/aarch64/aarch64.md diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 96705862de6..5aa127bcb47 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4134,7 +4134,7 @@ "" "mrs\\t%0, tpidr_el0" [(set_attr "v8type" "mrs") - (set_attr "type" "mov_reg") + (set_attr "type" "mrs") (set_attr "mode" "DI")] ) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index fd0b1cbdccd..8a482b570ec 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12453,7 +12453,7 @@ "TARGET_HARD_TP" "mrc%?\\tp15, 0, %0, c13, c0, 3\\t@ load_tp_hard" [(set_attr "predicable" "yes") - (set_attr "type" "mov_reg")] + (set_attr "type" "mrs")] ) ;; Doesn't clobber R1-R3. Must use r0 for the first operand. diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md index 6b155926024..ccad6207608 100644 --- a/gcc/config/arm/cortex-a15.md +++ b/gcc/config/arm/cortex-a15.md @@ -68,7 +68,7 @@ shift_imm,shift_reg,\ mov_imm,mov_reg,\ mvn_imm,mvn_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)") ;; ALU ops with immediate shift diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md index fa3e9d59c91..22e0a08f38e 100644 --- a/gcc/config/arm/cortex-a5.md +++ b/gcc/config/arm/cortex-a5.md @@ -64,7 +64,7 @@ adr,bfm,rev,\ shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "cortex_a5_ex1") (define_insn_reservation "cortex_a5_alu_shift" 2 diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index 33b5ca30150..48d0d03853f 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -73,7 +73,7 @@ adr,bfm,csel,rev,\ shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "cortex_a53_slot_any") (define_insn_reservation "cortex_a53_alu_shift" 2 diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md index ba9da8046eb..a72a88d90af 100644 --- a/gcc/config/arm/cortex-a7.md +++ b/gcc/config/arm/cortex-a7.md @@ -110,7 +110,7 @@ logic_shift_reg,logics_shift_reg,\ mov_shift,mov_shift_reg,\ mvn_shift,mvn_shift_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "cortex_a7_ex1") ;; Forwarding path for unshifted operands. diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md index ed0b351365c..1eade5e1244 100644 --- a/gcc/config/arm/cortex-a8.md +++ b/gcc/config/arm/cortex-a8.md @@ -111,7 +111,8 @@ (define_insn_reservation "cortex_a8_mov" 1 (and (eq_attr "tune" "cortexa8") (eq_attr "type" "mov_imm,mov_reg,mov_shift,mov_shift_reg,\ - mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")) + mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\ + mrs")) "cortex_a8_default") ;; Exceptions to the default latencies for data processing instructions. diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md index dd7505a0cf5..7c62d8489ae 100644 --- a/gcc/config/arm/cortex-a9.md +++ b/gcc/config/arm/cortex-a9.md @@ -87,7 +87,7 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1") shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ mov_shift_reg,mov_shift,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "cortex_a9_p0_default|cortex_a9_p1_default") ;; An instruction using the shifter will go down E1. diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md index 8663eb77fa1..9ae4cc3143b 100644 --- a/gcc/config/arm/cortex-m4.md +++ b/gcc/config/arm/cortex-m4.md @@ -42,7 +42,7 @@ logic_shift_reg,logics_shift_reg,\ mov_imm,mov_reg,mov_shift,mov_shift_reg,\ mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\ - multiple,no_insn") + mrs,multiple,no_insn") (ior (eq_attr "mul32" "yes") (eq_attr "mul64" "yes")))) "cortex_m4_ex") diff --git a/gcc/config/arm/cortex-r4.md b/gcc/config/arm/cortex-r4.md index 11a6e6419f5..7a3ceeb15d7 100644 --- a/gcc/config/arm/cortex-r4.md +++ b/gcc/config/arm/cortex-r4.md @@ -102,7 +102,7 @@ (eq_attr "type" "alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ mov_shift_reg,mvn_shift_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "cortex_r4_alu_shift_reg") ;; An ALU instruction followed by an ALU instruction with no early dep. diff --git a/gcc/config/arm/fa526.md b/gcc/config/arm/fa526.md index ddd48fe107e..401abd3c0a0 100644 --- a/gcc/config/arm/fa526.md +++ b/gcc/config/arm/fa526.md @@ -68,7 +68,7 @@ adr,bfm,rev,\ shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "fa526_core") (define_insn_reservation "526_alu_shift_op" 2 diff --git a/gcc/config/arm/fa606te.md b/gcc/config/arm/fa606te.md index 892ea31fccd..88347bc2d96 100644 --- a/gcc/config/arm/fa606te.md +++ b/gcc/config/arm/fa606te.md @@ -73,7 +73,7 @@ logic_shift_reg,logics_shift_reg,\ mov_imm,mov_reg,mov_shift,mov_shift_reg,\ mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "fa606te_core") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/config/arm/fa626te.md b/gcc/config/arm/fa626te.md index 8b9253171d4..e6790a21215 100644 --- a/gcc/config/arm/fa626te.md +++ b/gcc/config/arm/fa626te.md @@ -74,7 +74,7 @@ adr,bfm,rev,\ shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "fa626te_core") (define_insn_reservation "626te_alu_shift_op" 2 diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md index 28be92de75a..d0a03981eec 100644 --- a/gcc/config/arm/fa726te.md +++ b/gcc/config/arm/fa726te.md @@ -91,7 +91,7 @@ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ shift_imm,shift_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") ;; ALU operations with a shift-by-register operand. diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index 6c2db277dca..7a96438fd48 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -106,6 +106,7 @@ ; register. This includes MOVW, but not MOVT. ; mov_shift simple MOV instruction, shifted operand by a constant. ; mov_shift_reg simple MOV instruction, shifted operand by a register. +; mrs system/special/co-processor register move. ; mul integer multiply. ; muls integer multiply, flag setting. ; multiple more than one instruction, candidate for future @@ -372,6 +373,7 @@ mov_reg,\ mov_shift,\ mov_shift_reg,\ + mrs,\ mul,\ muls,\ multiple,\