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re PR rtl-optimization/6822 (GCC 3.1.1 - Internal compiler error in extract_insn, at recog.c:2132) 

PR optimization/6822
        * config/i386/i386.c (ix86_expand_int_movcc): Don't cast INTVAL
        to unsigned int for op1 comparisons.  Use gen_int_mode.

	* gcc.c-torture/compile/20020530-1.c: New.

Co-Authored-By: Eric Botcazou <ebotcazou@multimania.com>

From-SVN: r54078
This commit is contained in:
Richard Henderson 2002-05-30 16:13:20 -07:00 committed by Richard Henderson
parent 44776a0a45
commit 8c5f811911
2 changed files with 14 additions and 4 deletions
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8
gcc/ChangeLog
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@ -1,4 +1,12 @@
2002-05-30 Richard Henderson <rth@redhat.com>
Eric Botcazou <ebotcazou@multimania.com>
PR optimization/6822
* config/i386/i386.c (ix86_expand_int_movcc): Don't cast INTVAL
to unsigned int for op1 comparisons. Use gen_int_mode.
2002-05-30 Marc Espie <espie@openbsd.org>
* config.gcc (sparc64-*-openbsd*): New.
* config/sparc/openbsd1-64.h: New.
* config/sparc/openbsd64.h: New.

10
gcc/config/i386/i386.c
View File

@ -7963,11 +7963,12 @@ ix86_expand_int_movcc (operands)
if ((code == LEU || code == GTU)
&& GET_CODE (ix86_compare_op1) == CONST_INT
&& mode != HImode
&& (unsigned int) INTVAL (ix86_compare_op1) != 0xffffffff
/* The operand still must be representable as sign extended value. */
&& INTVAL (ix86_compare_op1) != -1
/* For x86-64, the immediate field in the instruction is 32-bit
signed, so we can't increment a DImode value above 0x7fffffff. */
&& (!TARGET_64BIT
|| GET_MODE (ix86_compare_op0) != DImode
|| (unsigned int) INTVAL (ix86_compare_op1) != 0x7fffffff)
|| INTVAL (ix86_compare_op1) != 0x7fffffff)
&& GET_CODE (operands[2]) == CONST_INT
&& GET_CODE (operands[3]) == CONST_INT)
{
@ -7975,7 +7976,8 @@ ix86_expand_int_movcc (operands)
code = LTU;
else
code = GEU;
ix86_compare_op1 = GEN_INT (INTVAL (ix86_compare_op1) + 1);
ix86_compare_op1 = gen_int_mode (INTVAL (ix86_compare_op1) + 1,
GET_MODE (ix86_compare_op0));
}
start_sequence ();