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[NDS32] Add abssi2 pattern.

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gcc/
	* common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS): Add
	MASK_HW_ABS.
	* config/nds32/nds32.md (abssi2): New pattern.

From-SVN: r260398
This commit is contained in:
Chung-Ju Wu 2018-05-19 14:51:09 +00:00 committed by Chung-Ju Wu
parent cca59a3cfc
commit 8c9babb851
3 changed files with 22 additions and 0 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2018-05-19 Chung-Ju Wu <jasonwucj@gmail.com>
* common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS): Add
MASK_HW_ABS.
* config/nds32/nds32.md (abssi2): New pattern.
2018-05-19 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (rex64namesuffix): New mode attribute.

2
gcc/common/config/nds32/nds32-common.c
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@ -103,6 +103,7 @@ static const struct default_options nds32_option_optimization_table[] =
TARGET_EXT_PERF : Generate performance extention instrcution.
TARGET_EXT_PERF2 : Generate performance extention version 2 instrcution.
TARGET_EXT_STRING : Generate string extention instrcution.
TARGET_HW_ABS : Generate hardware abs instruction.
TARGET_CMOV : Generate conditional move instruction. */
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS \
@ -113,6 +114,7 @@ static const struct default_options nds32_option_optimization_table[] =
| MASK_EXT_PERF \
| MASK_EXT_PERF2 \
| MASK_EXT_STRING \
| MASK_HW_ABS \
| MASK_CMOV)
#undef TARGET_HANDLE_OPTION

14
gcc/config/nds32/nds32.md
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@ -2086,6 +2086,20 @@
;; Performance Extension
; If -fwrapv option is issued, GCC expects there will be
; signed overflow situation. So the ABS(INT_MIN) is still INT_MIN
; (e.g. ABS(0x80000000)=0x80000000).
; However, the hardware ABS instruction of nds32 target
; always performs saturation: abs 0x80000000 -> 0x7fffffff.
; So that we can only enable abssi2 pattern if flag_wrapv is NOT presented.
(define_insn "abssi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(abs:SI (match_operand:SI 1 "register_operand" " r")))]
"TARGET_EXT_PERF && TARGET_HW_ABS && !flag_wrapv"
"abs\t%0, %1"
[(set_attr "type" "alu")
(set_attr "length" "4")])
(define_insn "clzsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(clz:SI (match_operand:SI 1 "register_operand" " r")))]