neon.ml (opcode): Add Vrintn, Vrinta, Vrintp, Vrintm, Vrintz to type.
gcc/ChangeLog 2012-12-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/arm/neon.ml (opcode): Add Vrintn, Vrinta, Vrintp, Vrintm, Vrintz to type. (type features): Add Requires_arch type constructor. (ops): Define Vrintn, Vrinta, Vrintp, Vrintm, Vrintz features. * config/arm/neon-docgen.ml (intrinsic_groups): Define Vrintn, Vrinta, Vrintp, Vrintm, Vrintz, Vrintx. * config/arm/neon-testgen.ml (effective_target): Define check for Requires_arch 8. * config/arm/neon-gen.ml (print_feature_test_start): Handle Requires_arch. (print_feature_test_end): Likewise. Add 2012 to Copyright notice. * doc/arm-neon-intrinsics.texi: Regenerate. * config/arm/arm_neon.h: Regenerate. gcc/testsuite/ChangeLog 2012-12-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gcc.target/arm/neon/vrndaf32.c: New test. * gcc.target/arm/neon/vrndqaf32.c: Likewise. * gcc.target/arm/neon/vrndf32.c: Likewise. * gcc.target/arm/neon/vrndqf32.c: Likewise. * gcc.target/arm/neon/vrndmf32.c: Likewise. * gcc.target/arm/neon/vrndqmf32.c: Likewise. * gcc.target/arm/neon/vrndnf32.c: Likewise. * gcc.target/arm/neon/vrndqnf32.c: Likewise. * gcc.target/arm/neon/vrndpf32.c: Likewise. * gcc.target/arm/neon/vrndqpf32.c: Likewise. From-SVN: r194353
This commit is contained in:
Kyrylo Tkachov
Kyrylo Tkachov
parent
0da911e95e
commit
8d28afb446
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@ -1,3 +1,20 @@
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2012-12-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/neon.ml (opcode): Add Vrintn, Vrinta, Vrintp, Vrintm,
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Vrintz to type.
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(type features): Add Requires_arch type constructor.
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(ops): Define Vrintn, Vrinta, Vrintp, Vrintm, Vrintz features.
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* config/arm/neon-docgen.ml (intrinsic_groups): Define Vrintn,
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Vrinta, Vrintp, Vrintm, Vrintz, Vrintx.
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* config/arm/neon-testgen.ml (effective_target): Define check for
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Requires_arch 8.
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* config/arm/neon-gen.ml
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(print_feature_test_start): Handle Requires_arch.
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(print_feature_test_end): Likewise.
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Add 2012 to Copyright notice.
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* doc/arm-neon-intrinsics.texi: Regenerate.
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* config/arm/arm_neon.h: Regenerate.
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2012-12-10 Kai Tietz <ktietz@redhat.com>
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* stmt.c (expand_sjlj_dispatch_table): Fix off by one.
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@ -1,7 +1,7 @@
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/* ARM NEON intrinsics include file. This file is generated automatically
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using neon-gen.ml. Please do not edit manually.
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Copyright (C) 2006, 2007, 2009 Free Software Foundation, Inc.
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Copyright (C) 2006, 2007, 2009, 2012 Free Software Foundation, Inc.
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Contributed by CodeSourcery.
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This file is part of GCC.
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@ -1381,6 +1381,86 @@ vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
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return (float32x4_t)__builtin_neon_vfmsv4sf (__a, __b, __c, 3);
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}
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#endif
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#if __ARM_ARCH >= 8
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__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
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vrndn_f32 (float32x2_t __a)
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{
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return (float32x2_t)__builtin_neon_vrintnv2sf (__a);
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}
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#endif
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#if __ARM_ARCH >= 8
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__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
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vrndqn_f32 (float32x4_t __a)
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{
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return (float32x4_t)__builtin_neon_vrintnv4sf (__a);
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}
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#endif
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#if __ARM_ARCH >= 8
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__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
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vrnda_f32 (float32x2_t __a)
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{
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return (float32x2_t)__builtin_neon_vrintav2sf (__a);
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}
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#endif
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#if __ARM_ARCH >= 8
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__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
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vrndqa_f32 (float32x4_t __a)
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{
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return (float32x4_t)__builtin_neon_vrintav4sf (__a);
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}
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#endif
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#if __ARM_ARCH >= 8
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__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
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vrndp_f32 (float32x2_t __a)
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{
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return (float32x2_t)__builtin_neon_vrintpv2sf (__a);
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}
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#endif
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#if __ARM_ARCH >= 8
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__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
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vrndqp_f32 (float32x4_t __a)
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{
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return (float32x4_t)__builtin_neon_vrintpv4sf (__a);
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}
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#endif
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#if __ARM_ARCH >= 8
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__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
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vrndm_f32 (float32x2_t __a)
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{
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return (float32x2_t)__builtin_neon_vrintmv2sf (__a);
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}
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#endif
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#if __ARM_ARCH >= 8
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__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
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vrndqm_f32 (float32x4_t __a)
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{
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return (float32x4_t)__builtin_neon_vrintmv4sf (__a);
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}
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#endif
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#if __ARM_ARCH >= 8
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__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
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vrnd_f32 (float32x2_t __a)
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{
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return (float32x2_t)__builtin_neon_vrintzv2sf (__a);
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}
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#endif
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#if __ARM_ARCH >= 8
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__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
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vrndq_f32 (float32x4_t __a)
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{
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return (float32x4_t)__builtin_neon_vrintzv4sf (__a);
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}
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#endif
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__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
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vsub_s8 (int8x8_t __a, int8x8_t __b)
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@ -105,6 +105,11 @@ let intrinsic_groups =
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"Multiply-subtract", single_opcode Vmls;
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"Fused-multiply-accumulate", single_opcode Vfma;
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"Fused-multiply-subtract", single_opcode Vfms;
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"Round to integral (to nearest, ties to even)", single_opcode Vrintn;
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"Round to integral (to nearest, ties away from zero)", single_opcode Vrinta;
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"Round to integral (towards +Inf)", single_opcode Vrintp;
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"Round to integral (towards -Inf)", single_opcode Vrintm;
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"Round to integral (towards 0)", single_opcode Vrintz;
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"Subtraction", single_opcode Vsub;
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"Comparison (equal-to)", single_opcode Vceq;
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"Comparison (greater-than-or-equal-to)", single_opcode Vcge;
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@ -290,17 +290,21 @@ let print_feature_test_start features =
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try
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match List.find (fun feature ->
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match feature with Requires_feature _ -> true
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| Requires_arch _ -> true
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| _ -> false)
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features with
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Requires_feature feature ->
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Format.printf "#ifdef __ARM_FEATURE_%s@\n" feature
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| Requires_arch arch ->
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Format.printf "#if __ARM_ARCH >= %d@\n" arch
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| _ -> assert false
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with Not_found -> assert true
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let print_feature_test_end features =
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let feature =
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List.exists (function Requires_feature x -> true
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| _ -> false) features in
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| Requires_arch x -> true
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| _ -> false) features in
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if feature then Format.printf "#endif@\n"
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@ -437,7 +441,7 @@ let _ =
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"/* ARM NEON intrinsics include file. This file is generated automatically";
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" using neon-gen.ml. Please do not edit manually.";
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"";
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" Copyright (C) 2006, 2007, 2009 Free Software Foundation, Inc.";
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" Copyright (C) 2006, 2007, 2009, 2012 Free Software Foundation, Inc.";
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" Contributed by CodeSourcery.";
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"";
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" This file is part of GCC.";
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@ -162,9 +162,11 @@ let effective_target features =
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try
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match List.find (fun feature ->
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match feature with Requires_feature _ -> true
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| Requires_arch _ -> true
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| _ -> false)
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features with
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Requires_feature "FMA" -> "arm_neonv2"
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| Requires_arch 8 -> "arm_v8_neon"
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| _ -> assert false
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with Not_found -> "arm_neon"
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@ -152,6 +152,11 @@ type opcode =
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| Vqdmulh_n
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| Vqdmulh_lane
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(* Unary ops. *)
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| Vrintn
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| Vrinta
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| Vrintp
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| Vrintm
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| Vrintz
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| Vabs
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| Vneg
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| Vcls
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@ -279,6 +284,7 @@ type features =
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| Fixed_core_reg
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(* Mark that the intrinsic requires __ARM_FEATURE_string to be defined. *)
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| Requires_feature of string
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| Requires_arch of int
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exception MixedMode of elts * elts
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@ -812,6 +818,27 @@ let ops =
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Vfms, [Requires_feature "FMA"], All (3, Dreg), "vfms", elts_same_io, [F32];
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Vfms, [Requires_feature "FMA"], All (3, Qreg), "vfmsQ", elts_same_io, [F32];
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(* Round to integral. *)
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Vrintn, [Builtin_name "vrintn"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
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"vrndn", elts_same_1, [F32];
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Vrintn, [Builtin_name "vrintn"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
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"vrndqn", elts_same_1, [F32];
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Vrinta, [Builtin_name "vrinta"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
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"vrnda", elts_same_1, [F32];
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Vrinta, [Builtin_name "vrinta"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
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"vrndqa", elts_same_1, [F32];
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Vrintp, [Builtin_name "vrintp"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
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"vrndp", elts_same_1, [F32];
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Vrintp, [Builtin_name "vrintp"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
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"vrndqp", elts_same_1, [F32];
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Vrintm, [Builtin_name "vrintm"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
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"vrndm", elts_same_1, [F32];
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Vrintm, [Builtin_name "vrintm"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
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"vrndqm", elts_same_1, [F32];
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Vrintz, [Builtin_name "vrintz"; Requires_arch 8], Use_operands [| Dreg; Dreg |],
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"vrnd", elts_same_1, [F32];
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Vrintz, [Builtin_name "vrintz"; Requires_arch 8], Use_operands [| Qreg; Qreg |],
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"vrndq", elts_same_1, [F32];
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(* Subtraction. *)
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Vsub, [], All (3, Dreg), "vsub", sign_invar_2, F32 :: su_8_32;
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Vsub, [No_op], All (3, Dreg), "vsub", sign_invar_2, [S64; U64];
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@ -1004,6 +1004,86 @@
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@subsubsection Round to integral (to nearest, ties to even)
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@itemize @bullet
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@item float32x2_t vrndn_f32 (float32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vrintn.f32 @var{d0}, @var{d0}}
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@end itemize
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@itemize @bullet
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@item float32x4_t vrndqn_f32 (float32x4_t)
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@*@emph{Form of expected instruction(s):} @code{vrintn.f32 @var{q0}, @var{q0}}
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@end itemize
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@subsubsection Round to integral (to nearest, ties away from zero)
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@itemize @bullet
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@item float32x2_t vrnda_f32 (float32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vrinta.f32 @var{d0}, @var{d0}}
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@end itemize
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@itemize @bullet
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@item float32x4_t vrndqa_f32 (float32x4_t)
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@*@emph{Form of expected instruction(s):} @code{vrinta.f32 @var{q0}, @var{q0}}
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@end itemize
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@subsubsection Round to integral (towards +Inf)
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@itemize @bullet
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@item float32x2_t vrndp_f32 (float32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vrintp.f32 @var{d0}, @var{d0}}
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@end itemize
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@itemize @bullet
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@item float32x4_t vrndqp_f32 (float32x4_t)
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@*@emph{Form of expected instruction(s):} @code{vrintp.f32 @var{q0}, @var{q0}}
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@end itemize
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@subsubsection Round to integral (towards -Inf)
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@itemize @bullet
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@item float32x2_t vrndm_f32 (float32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vrintm.f32 @var{d0}, @var{d0}}
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@end itemize
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@itemize @bullet
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@item float32x4_t vrndqm_f32 (float32x4_t)
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@*@emph{Form of expected instruction(s):} @code{vrintm.f32 @var{q0}, @var{q0}}
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@end itemize
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@subsubsection Round to integral (towards 0)
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@itemize @bullet
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@item float32x2_t vrnd_f32 (float32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vrintz.f32 @var{d0}, @var{d0}}
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@end itemize
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@itemize @bullet
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@item float32x4_t vrndq_f32 (float32x4_t)
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@*@emph{Form of expected instruction(s):} @code{vrintz.f32 @var{q0}, @var{q0}}
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@end itemize
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@subsubsection Subtraction
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@itemize @bullet
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@ -7217,12 +7297,6 @@
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@subsubsection Transpose elements
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@itemize @bullet
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@item uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
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@end itemize
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@itemize @bullet
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@item uint16x4x2_t vtrn_u16 (uint16x4_t, uint16x4_t)
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@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
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@ -7235,12 +7309,6 @@
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@end itemize
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@itemize @bullet
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@item int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
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@end itemize
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@itemize @bullet
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@item int16x4x2_t vtrn_s16 (int16x4_t, int16x4_t)
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@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
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@ -7253,12 +7321,6 @@
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@end itemize
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@itemize @bullet
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@item float32x2x2_t vtrn_f32 (float32x2_t, float32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
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@end itemize
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@itemize @bullet
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@item poly16x4x2_t vtrn_p16 (poly16x4_t, poly16x4_t)
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@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
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@ -7271,6 +7333,24 @@
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@end itemize
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@itemize @bullet
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@item float32x2x2_t vtrn_f32 (float32x2_t, float32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
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@end itemize
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@itemize @bullet
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@item uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
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@end itemize
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@itemize @bullet
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@item int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
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@end itemize
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@itemize @bullet
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@item uint32x4x2_t vtrnq_u32 (uint32x4_t, uint32x4_t)
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@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
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@ -7329,12 +7409,6 @@
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@subsubsection Zip elements
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@itemize @bullet
|
||||
@item uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint16x4x2_t vzip_u16 (uint16x4_t, uint16x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
|
||||
|
|
@ -7347,12 +7421,6 @@
|
|||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item int32x2x2_t vzip_s32 (int32x2_t, int32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item int16x4x2_t vzip_s16 (int16x4_t, int16x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
|
||||
|
|
@ -7365,12 +7433,6 @@
|
|||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item float32x2x2_t vzip_f32 (float32x2_t, float32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item poly16x4x2_t vzip_p16 (poly16x4_t, poly16x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
|
||||
|
|
@ -7383,6 +7445,24 @@
|
|||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item float32x2x2_t vzip_f32 (float32x2_t, float32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item int32x2x2_t vzip_s32 (int32x2_t, int32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x4x2_t vzipq_u32 (uint32x4_t, uint32x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
|
||||
|
|
@ -7939,13 +8019,13 @@
|
|||
|
||||
@itemize @bullet
|
||||
@item uint64x2_t vld1q_dup_u64 (const uint64_t *)
|
||||
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
|
||||
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item int64x2_t vld1q_dup_s64 (const int64_t *)
|
||||
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
|
||||
@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
|
||||
@end itemize
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,16 @@
|
|||
2012-12-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
||||
|
||||
* gcc.target/arm/neon/vrndaf32.c: New test.
|
||||
* gcc.target/arm/neon/vrndqaf32.c: Likewise.
|
||||
* gcc.target/arm/neon/vrndf32.c: Likewise.
|
||||
* gcc.target/arm/neon/vrndqf32.c: Likewise.
|
||||
* gcc.target/arm/neon/vrndmf32.c: Likewise.
|
||||
* gcc.target/arm/neon/vrndqmf32.c: Likewise.
|
||||
* gcc.target/arm/neon/vrndnf32.c: Likewise.
|
||||
* gcc.target/arm/neon/vrndqnf32.c: Likewise.
|
||||
* gcc.target/arm/neon/vrndpf32.c: Likewise.
|
||||
* gcc.target/arm/neon/vrndqpf32.c: Likewise.
|
||||
|
||||
2012-12-09 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
|
||||
|
||||
* gcc.misc-tests/gcov-12.c: Fix dg order.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vrndaf32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_v8_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_v8_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vrndaf32 (void)
|
||||
{
|
||||
float32x2_t out_float32x2_t;
|
||||
float32x2_t arg0_float32x2_t;
|
||||
|
||||
out_float32x2_t = vrnda_f32 (arg0_float32x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrinta\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vrndf32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_v8_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_v8_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vrndf32 (void)
|
||||
{
|
||||
float32x2_t out_float32x2_t;
|
||||
float32x2_t arg0_float32x2_t;
|
||||
|
||||
out_float32x2_t = vrnd_f32 (arg0_float32x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrintz\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vrndmf32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_v8_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_v8_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vrndmf32 (void)
|
||||
{
|
||||
float32x2_t out_float32x2_t;
|
||||
float32x2_t arg0_float32x2_t;
|
||||
|
||||
out_float32x2_t = vrndm_f32 (arg0_float32x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrintm\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vrndnf32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_v8_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_v8_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vrndnf32 (void)
|
||||
{
|
||||
float32x2_t out_float32x2_t;
|
||||
float32x2_t arg0_float32x2_t;
|
||||
|
||||
out_float32x2_t = vrndn_f32 (arg0_float32x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrintn\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vrndpf32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_v8_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_v8_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vrndpf32 (void)
|
||||
{
|
||||
float32x2_t out_float32x2_t;
|
||||
float32x2_t arg0_float32x2_t;
|
||||
|
||||
out_float32x2_t = vrndp_f32 (arg0_float32x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrintp\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vrndqaf32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_v8_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_v8_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vrndqaf32 (void)
|
||||
{
|
||||
float32x4_t out_float32x4_t;
|
||||
float32x4_t arg0_float32x4_t;
|
||||
|
||||
out_float32x4_t = vrndqa_f32 (arg0_float32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrinta\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vrndqf32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_v8_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_v8_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vrndqf32 (void)
|
||||
{
|
||||
float32x4_t out_float32x4_t;
|
||||
float32x4_t arg0_float32x4_t;
|
||||
|
||||
out_float32x4_t = vrndq_f32 (arg0_float32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrintz\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vrndqmf32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_v8_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_v8_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vrndqmf32 (void)
|
||||
{
|
||||
float32x4_t out_float32x4_t;
|
||||
float32x4_t arg0_float32x4_t;
|
||||
|
||||
out_float32x4_t = vrndqm_f32 (arg0_float32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrintm\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vrndqnf32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_v8_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_v8_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vrndqnf32 (void)
|
||||
{
|
||||
float32x4_t out_float32x4_t;
|
||||
float32x4_t arg0_float32x4_t;
|
||||
|
||||
out_float32x4_t = vrndqn_f32 (arg0_float32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrintn\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vrndqpf32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_v8_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_v8_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vrndqpf32 (void)
|
||||
{
|
||||
float32x4_t out_float32x4_t;
|
||||
float32x4_t arg0_float32x4_t;
|
||||
|
||||
out_float32x4_t = vrndqp_f32 (arg0_float32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrintp\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
Loading…
Reference in New Issue