diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9c952be5ab7..7b8e319ab6f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2002-09-04  John David Anglin  <dave@hiauly1.hia.nrc.ca>
+
+	* pa.md (setccfp0, setccfp1): New patterns.
+
 2002-09-04  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
 
 	* frv-protos.h (frv_init_builtins, frv_expand_builtin,
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 7632beba83c..29fe1c874e6 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -628,6 +628,26 @@
   [(set_attr "length" "4")
    (set_attr "type" "fpcc")])
 
+;; The following two patterns are optimization placeholders.  In almost
+;; all cases, the user of the condition code will be simplified and the
+;; original condition code setting insn should be eliminated.
+
+(define_insn "*setccfp0"
+  [(set (reg:CCFP 0)
+	(const_int 0))]
+  "! TARGET_SOFT_FLOAT"
+  "fcmp,dbl,!= %%fr0,%%fr0"
+  [(set_attr "length" "4")
+   (set_attr "type" "fpcc")])
+
+(define_insn "*setccfp1"
+  [(set (reg:CCFP 0)
+	(const_int 1))]
+  "! TARGET_SOFT_FLOAT"
+  "fcmp,dbl,= %%fr0,%%fr0"
+  [(set_attr "length" "4")
+   (set_attr "type" "fpcc")])
+
 ;; scc insns.
 
 (define_expand "seq"