(ext_shift_insns, ext_shift_amounts): new arrays.
(gen_ashift_hi, gen_shifty_hi_op, shl_and_kind): new functions. rtx_equal_function_value_matters: declare. (shl_and_length, shl_and_src_length, gen_shl_and): new functions. (shl_sext_kind, shl_sext_length, gen_shl_sext): new functions. From-SVN: r12726
This commit is contained in:
Jim Wilson
parent
98e819b9b7
commit
8d4812411e
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@ -684,6 +684,23 @@ static short shift_amounts[32][5] = {
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{16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
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{16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
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/* Likewise, but for shift amounts < 16, up to three highmost bits
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might be clobbered. This is typically used when combined with some
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kind of sign or zero extension. */
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static char ext_shift_insns[] =
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{ 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
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static short ext_shift_amounts[32][4] = {
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{0}, {1}, {2}, {2, 1},
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{2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
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{8}, {8, 1}, {8, 2}, {8, 1, 2},
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{8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
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{16}, {16, 1}, {16, 2}, {16, 1, 2},
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{16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
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{16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
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{16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
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/* This is used in length attributes in sh.md to help compute the length
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of arbitrary constant shift instructions. */
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@ -825,6 +842,41 @@ gen_ashift (type, n, reg)
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}
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}
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/* Same for HImode */
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void
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gen_ashift_hi (type, n, reg)
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int type;
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int n;
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rtx reg;
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{
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/* Negative values here come from the shift_amounts array. */
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if (n < 0)
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{
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if (type == ASHIFT)
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type = LSHIFTRT;
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else
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type = ASHIFT;
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n = -n;
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}
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switch (type)
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{
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case ASHIFTRT:
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emit_insn (gen_ashrhi3_k (reg, reg, GEN_INT (n)));
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break;
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case LSHIFTRT:
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if (n == 1)
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emit_insn (gen_lshrhi3_m (reg, reg, GEN_INT (n)));
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else
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emit_insn (gen_lshrhi3_k (reg, reg, GEN_INT (n)));
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break;
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case ASHIFT:
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emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
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break;
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}
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}
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/* Output RTL to split a constant shift into its component SH constant
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shift instructions. */
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@ -872,6 +924,41 @@ gen_shifty_op (code, operands)
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for (i = 0; i < max; i++)
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gen_ashift (code, shift_amounts[value][i], operands[0]);
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}
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/* Same as above, but optimized for values where the topmost bits don't
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matter. */
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int
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gen_shifty_hi_op (code, operands)
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int code;
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rtx *operands;
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{
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int value = INTVAL (operands[2]);
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int max, i;
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void (*gen_fun)();
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/* This operation is used by and_shl for SImode values with a few
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high bits known to be cleared. */
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value &= 31;
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if (value == 0)
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{
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emit_insn (gen_nop ());
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return;
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}
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gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
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if (code == ASHIFT)
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{
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max = ext_shift_insns[value];
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for (i = 0; i < max; i++)
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gen_fun (code, ext_shift_amounts[value][i], operands[0]);
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}
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else
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/* When shifting right, emit the shifts in reverse order, so that
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solitary negative values come first. */
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for (i = ext_shift_insns[value] - 1; i >= 0; i--)
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gen_fun (code, ext_shift_amounts[value][i], operands[0]);
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}
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/* Output RTL for an arithmetic right shift. */
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@ -945,6 +1032,504 @@ expand_ashiftrt (operands)
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emit_move_insn (operands[0], gen_rtx (REG, SImode, 4));
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return 1;
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}
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/* Try to find a good way to implement the combiner pattern
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[(set (match_operand:SI 0 "register_operand" "r")
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(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "const_int_operand" "n"))
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(match_operand:SI 3 "const_int_operand" "n"))) .
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LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
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return 0 for simple right / left or left/right shift combination.
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return 1 for a combination of shifts with zero_extend.
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return 2 for a combination of shifts with an AND that needs r0.
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return 3 for a combination of shifts with an AND that needs an extra
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scratch register, when the three highmost bits of the AND mask are clear.
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return 4 for a combination of shifts with an AND that needs an extra
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scratch register, when any of the three highmost bits of the AND mask
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is set.
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If ATTRP is set, store an initial right shift width in ATTRP[0],
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and the instruction length in ATTRP[1] . These values are not valid
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when returning 0.
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When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
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shift_amounts for the last shift value that is to be used before the
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sign extend. */
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int
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shl_and_kind (left_rtx, mask_rtx, attrp)
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rtx left_rtx, mask_rtx;
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int *attrp;
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{
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unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
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int left = INTVAL (left_rtx), right;
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int best = 0;
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int cost, best_cost = 10000;
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int best_right = 0, best_len = 0;
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int i;
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int can_ext;
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if (left < 0 || left > 31)
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return 0;
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if (GET_CODE (mask_rtx) == CONST_INT)
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mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
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else
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mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
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/* Can this be expressed as a right shift / left shift pair ? */
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lsb = ((mask ^ (mask - 1)) >> 1) + 1;
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right = exact_log2 (lsb);
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mask2 = ~(mask + lsb - 1);
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lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
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/* mask has no zeroes but trailing zeroes <==> ! mask2 */
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if (! mask2)
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best_cost = shift_insns[right] + shift_insns[right + left];
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/* mask has no trailing zeroes <==> ! right */
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else if (! right && mask2 == ~(lsb2 - 1))
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{
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int late_right = exact_log2 (lsb2);
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best_cost = shift_insns[left + late_right] + shift_insns[late_right];
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}
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/* Try to use zero extend */
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if (mask2 == ~(lsb2 - 1))
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{
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int width, first;
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for (width = 8; width <= 16; width += 8)
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{
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/* Can we zero-extend right away? */
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if (lsb2 == (HOST_WIDE_INT)1 << width)
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{
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cost
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= 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
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if (cost < best_cost)
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{
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best = 1;
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best_cost = cost;
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best_right = right;
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best_len = cost;
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if (attrp)
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attrp[2] = -1;
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}
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continue;
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}
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/* ??? Could try to put zero extend into initial right shift,
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or even shift a bit left before the right shift. */
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/* Determine value of first part of left shift, to get to the
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zero extend cut-off point. */
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first = width - exact_log2 (lsb2) + right;
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if (first >= 0 && right + left - first >= 0)
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{
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cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
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+ ext_shift_insns[right + left - first];
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if (cost < best_cost)
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{
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best = 1;
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best_cost = cost;
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best_right = right;
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best_len = cost;
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if (attrp)
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attrp[2] = first;
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}
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}
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}
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}
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/* Try to use r0 AND pattern */
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for (i = 0; i <= 2; i++)
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{
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if (i > right)
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break;
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if (! CONST_OK_FOR_L (mask >> i))
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continue;
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cost = (i != 0) + 2 + ext_shift_insns[left + i];
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if (cost < best_cost)
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{
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best = 2;
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best_cost = cost;
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best_right = i;
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best_len = cost - 1;
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}
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}
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/* Try to use a scratch register to hold the AND operand. */
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can_ext = ((mask << left) & 0xe0000000) == 0;
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for (i = 0; i <= 2; i++)
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{
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if (i > right)
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break;
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cost = (i != 0) + (CONST_OK_FOR_I (mask >> i) ? 2 : 3)
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+ (can_ext ? ext_shift_insns : shift_insns)[left];
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if (cost < best_cost)
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{
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best = 4 - can_ext;
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best_cost = cost;
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best_right = i;
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best_len = cost - 1 - ! CONST_OK_FOR_I (mask >> i);
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}
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}
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if (attrp)
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{
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attrp[0] = best_right;
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attrp[1] = best_len;
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}
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return best;
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}
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/* This is used in length attributes of the unnamed instructions
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corresponding to shl_and_kind return values of 1 and 2. */
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int
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shl_and_length (insn)
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rtx insn;
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{
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rtx set_src, left_rtx, mask_rtx;
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int attributes[3];
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set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
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left_rtx = XEXP (XEXP (set_src, 0), 1);
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mask_rtx = XEXP (set_src, 1);
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shl_and_kind (left_rtx, mask_rtx, attributes);
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return attributes[1];
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}
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/* This is used in length attribute of the and_shl_scratch instruction. */
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int
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shl_and_scr_length (insn)
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rtx insn;
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{
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rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
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int len = shift_insns[INTVAL (XEXP (set_src, 1))];
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rtx op = XEXP (set_src, 0);
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len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
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op = XEXP (XEXP (op, 0), 0);
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return len + shift_insns[INTVAL (XEXP (op, 1))];
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}
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/* Generating rtl? */
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extern int rtx_equal_function_value_matters;
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/* Generate rtl for instructions for which shl_and_kind advised a particular
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method of generating them, i.e. returned zero. */
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int
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gen_shl_and (dest, left_rtx, mask_rtx, source)
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rtx dest, left_rtx, mask_rtx, source;
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{
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int attributes[3];
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unsigned HOST_WIDE_INT mask;
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int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
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int right, total_shift;
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int (*shift_gen_fun) PROTO((int, rtx*)) = gen_shifty_hi_op;
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right = attributes[0];
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total_shift = INTVAL (left_rtx) + right;
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mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
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switch (kind)
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{
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default:
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return -1;
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case 1:
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{
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int first = attributes[2];
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rtx operands[3];
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if (first < 0)
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{
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emit_insn ((mask << right) == 0xff
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? gen_zero_extendqisi2(dest, gen_rtx (SUBREG, QImode,
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source, 0))
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: gen_zero_extendhisi2(dest, gen_rtx (SUBREG, HImode,
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source, 0)));
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source = dest;
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}
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if (source != dest)
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emit_insn (gen_movsi (dest, source));
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operands[0] = dest;
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if (right)
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{
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operands[2] = GEN_INT (right);
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gen_shifty_hi_op (LSHIFTRT, operands);
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}
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if (first > 0)
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{
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operands[2] = GEN_INT (first);
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gen_shifty_hi_op (ASHIFT, operands);
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total_shift -= first;
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mask <<= first;
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}
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if (first >= 0)
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emit_insn (mask == 0xff
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? gen_zero_extendqisi2(dest, gen_rtx (SUBREG, QImode,
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dest, 0))
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: gen_zero_extendhisi2(dest, gen_rtx (SUBREG, HImode,
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dest, 0)));
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if (total_shift > 0)
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{
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operands[2] = GEN_INT (total_shift);
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gen_shifty_hi_op (ASHIFT, operands);
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}
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break;
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}
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case 4:
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shift_gen_fun = gen_shifty_op;
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case 2:
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case 3:
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/* Don't expand fine-grained when combining, because that will
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make the pattern fail. */
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if (rtx_equal_function_value_matters
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|| reload_in_progress || reload_completed)
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{
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rtx operands[3];
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if (right)
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{
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emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
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source = dest;
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}
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emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
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operands[0] = dest;
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operands[1] = dest;
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operands[2] = GEN_INT (total_shift);
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shift_gen_fun (ASHIFT, operands);
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break;
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}
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else
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{
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int neg = 0;
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if (kind != 4 && total_shift < 16)
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{
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neg = -ext_shift_amounts[total_shift][1];
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if (neg > 0)
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neg -= ext_shift_amounts[total_shift][2];
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else
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neg = 0;
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}
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emit_insn (gen_and_shl_scratch (dest, source,
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GEN_INT (right),
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GEN_INT (mask),
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GEN_INT (total_shift + neg),
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GEN_INT (neg)));
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emit_insn (gen_movsi (dest, dest));
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break;
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}
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}
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return 0;
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}
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/* Try to find a good way to implement the combiner pattern
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[(set (match_operand:SI 0 "register_operand" "=r")
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(sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "const_int_operand" "n")
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(match_operand:SI 3 "const_int_operand" "n")
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(const_int 0)))
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(clobber (reg:SI 18))]
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LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
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return 0 for simple left / right shift combination.
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return 1 for left shift / 8 bit sign extend / left shift.
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return 2 for left shift / 16 bit sign extend / left shift.
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return 3 for left shift / 8 bit sign extend / shift / sign extend.
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return 4 for left shift / 16 bit sign extend / shift / sign extend.
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return 5 for left shift / 16 bit sign extend / right shift
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return 6 for < 8 bit sign extend / left shift.
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return 7 for < 8 bit sign extend / left shift / single right shift.
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If COSTP is nonzero, assign the calculated cost to *COSTP. */
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int
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shl_sext_kind (left_rtx, size_rtx, costp)
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rtx left_rtx, size_rtx;
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int *costp;
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{
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int left, size, insize, ext;
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int cost, best_cost;
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int kind;
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left = INTVAL (left_rtx);
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size = INTVAL (size_rtx);
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insize = size - left;
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if (insize <= 0)
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abort ();
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/* Default to left / right shift. */
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kind = 0;
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best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
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if (size <= 16)
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{
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/* 16 bit shift / sign extend / 16 bit shift */
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cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
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if (cost < best_cost)
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{
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kind = 5;
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best_cost = cost;
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}
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}
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/* Try a plain sign extend between two shifts. */
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for (ext = 16; ext >= insize; ext -= 8)
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{
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if (ext <= size)
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{
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cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
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if (cost < best_cost)
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{
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kind = ext / 8U;
|
||||
best_cost = cost;
|
||||
}
|
||||
}
|
||||
if (size <= 16)
|
||||
{
|
||||
/* Maybe it's cheaper to do the second shift sloppy, and do a
|
||||
final sign extend? */
|
||||
cost = ext_shift_insns[ext - insize] + 1
|
||||
+ ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
|
||||
if (cost < best_cost)
|
||||
{
|
||||
kind = ext / 8U + 2;
|
||||
best_cost = cost;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Check if we can sign extend in r0 */
|
||||
if (insize < 8)
|
||||
{
|
||||
cost = 3 + shift_insns[left];
|
||||
if (cost < best_cost)
|
||||
{
|
||||
kind = 6;
|
||||
best_cost = cost;
|
||||
}
|
||||
/* Try the same with a final signed shift. */
|
||||
if (left < 31)
|
||||
{
|
||||
cost = 3 + ext_shift_insns[left + 1] + 1;
|
||||
if (cost < best_cost)
|
||||
{
|
||||
kind = 7;
|
||||
best_cost = cost;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (TARGET_SH3)
|
||||
{
|
||||
/* Try to use a dynamic shift. */
|
||||
cost = shift_insns[32 - insize] + 3;
|
||||
if (cost < best_cost)
|
||||
{
|
||||
kind = 0;
|
||||
best_cost = cost;
|
||||
}
|
||||
}
|
||||
if (costp)
|
||||
*costp = cost;
|
||||
return kind;
|
||||
}
|
||||
|
||||
/* Function to be used in the length attribute of the instructions
|
||||
implementing this pattern. */
|
||||
|
||||
int
|
||||
shl_sext_length (insn)
|
||||
rtx insn;
|
||||
{
|
||||
rtx set_src, left_rtx, size_rtx;
|
||||
int cost;
|
||||
|
||||
set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
|
||||
left_rtx = XEXP (XEXP (set_src, 0), 1);
|
||||
size_rtx = XEXP (set_src, 1);
|
||||
shl_sext_kind (left_rtx, size_rtx, &cost);
|
||||
return cost;
|
||||
}
|
||||
|
||||
/* Generate rtl for this pattern */
|
||||
|
||||
int
|
||||
gen_shl_sext (dest, left_rtx, size_rtx, source)
|
||||
rtx dest, left_rtx, size_rtx, source;
|
||||
{
|
||||
int kind;
|
||||
int left, size, insize;
|
||||
rtx operands[3];
|
||||
|
||||
kind = shl_sext_kind (left_rtx, size_rtx);
|
||||
left = INTVAL (left_rtx);
|
||||
size = INTVAL (size_rtx);
|
||||
insize = size - left;
|
||||
switch (kind)
|
||||
{
|
||||
case 1:
|
||||
case 2:
|
||||
case 3:
|
||||
case 4:
|
||||
{
|
||||
int ext = kind & 1 ? 8 : 16;
|
||||
int shift2 = size - ext;
|
||||
|
||||
/* Don't expand fine-grained when combining, because that will
|
||||
make the pattern fail. */
|
||||
if (! rtx_equal_function_value_matters
|
||||
&& ! reload_in_progress && ! reload_completed)
|
||||
{
|
||||
emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
|
||||
emit_insn (gen_movsi (dest, source));
|
||||
break;
|
||||
}
|
||||
if (dest != source)
|
||||
emit_insn (gen_movsi (dest, source));
|
||||
operands[0] = dest;
|
||||
operands[2] = GEN_INT (ext - insize);
|
||||
gen_shifty_hi_op (ASHIFT, operands);
|
||||
emit_insn (kind & 1
|
||||
? gen_extendqisi2(dest, gen_rtx (SUBREG, QImode, dest, 0))
|
||||
: gen_extendhisi2(dest, gen_rtx (SUBREG, HImode, dest, 0)));
|
||||
if (kind <= 2)
|
||||
{
|
||||
operands[2] = GEN_INT (shift2);
|
||||
gen_shifty_op (ASHIFT, operands);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (shift2 >= 0)
|
||||
{
|
||||
operands[2] = GEN_INT (shift2);
|
||||
gen_shifty_hi_op (ASHIFT, operands);
|
||||
}
|
||||
else
|
||||
{
|
||||
operands[2] = GEN_INT (-shift2);
|
||||
gen_shifty_hi_op (LSHIFTRT, operands);
|
||||
}
|
||||
emit_insn (size <= 8
|
||||
? gen_extendqisi2 (dest,
|
||||
gen_rtx (SUBREG, QImode, dest, 0))
|
||||
: gen_extendhisi2 (dest,
|
||||
gen_rtx (SUBREG, HImode, dest, 0)));
|
||||
}
|
||||
break;
|
||||
}
|
||||
case 5:
|
||||
emit_insn (gen_shl_sext_ext (dest, source, GEN_INT (16 - insize),
|
||||
GEN_INT (16)));
|
||||
emit_insn (gen_ashrsi3 (dest, dest, GEN_INT (16 - size)));
|
||||
break;
|
||||
case 6:
|
||||
case 7:
|
||||
/* Don't expand fine-grained when combining, because that will
|
||||
make the pattern fail. */
|
||||
if (! rtx_equal_function_value_matters
|
||||
&& ! reload_in_progress && ! reload_completed)
|
||||
{
|
||||
emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
|
||||
emit_insn (gen_movsi (dest, source));
|
||||
break;
|
||||
}
|
||||
emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
|
||||
emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
|
||||
emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
|
||||
operands[0] = dest;
|
||||
operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
|
||||
gen_shifty_op (ASHIFT, operands);
|
||||
if (kind == 7)
|
||||
emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* The SH cannot load a large constant into a register, constants have to
|
||||
come from a pc relative load. The reference of a pc relative load
|
||||
|
|
|
|||
Loading…
Reference in New Issue