re PR target/65240 (ICE (insn does not satisfy its constraints) on powerpc64le-linux-gnu)
[gcc] 2015-03-19 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/65240 * config/rs6000/predicates.md (easy_fp_constant): Remove special -ffast-math handling that kept non-0 constants live in the RTL until reload. Remove logic testing the number of instructions it took to create a constant in a GPR that was never used, due to a test for soft-float earlier. (memory_fp_constant): Delete, no longer used. * config/rs6000/rs6000.md (mov<MODE>_hardfloat): Remove alternatives for loading non-0 constants into GPRs for hard floating point that is no longer needed due to changes in easy_fp_constant. Add support for loading 0.0 into GPRs. (mov<mode>_hardfloat32): Likewise. (mov<mode>_hardfloat64): Likewise. (mov<mode>_64bit_dm): Likewise. (movtd_64bit_nodm): Likewise. (pre-reload move FP constant define_split): Delete define_split, since it is no longer used. (extenddftf2_internal): Remove GHF constraints that are not valid for extenddftf2. [gcc/testsuite] 2015-03-19 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/65240 * gcc/testsuite/g++.dg/pr65240.h: Add tests for PR 65240. * gcc/testsuite/g++.dg/pr65240-1.C: Likewise. * gcc/testsuite/g++.dg/pr65240-2.C: Likewise. * gcc/testsuite/g++.dg/pr65240-3.C: Likewise. * gcc/testsuite/g++.dg/pr65240-4.C: Likewise. From-SVN: r221524
This commit is contained in:
Michael Meissner
Michael Meissner
parent
ef0006ebdb
commit
8d9fb9bb35
@ -1,3 +1,26 @@
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2015-03-19 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/65240
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* config/rs6000/predicates.md (easy_fp_constant): Remove special
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-ffast-math handling that kept non-0 constants live in the RTL
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until reload. Remove logic testing the number of instructions it
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took to create a constant in a GPR that was never used, due to a
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test for soft-float earlier.
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(memory_fp_constant): Delete, no longer used.
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* config/rs6000/rs6000.md (mov<MODE>_hardfloat): Remove
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alternatives for loading non-0 constants into GPRs for hard
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floating point that is no longer needed due to changes in
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easy_fp_constant. Add support for loading 0.0 into GPRs.
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(mov<mode>_hardfloat32): Likewise.
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(mov<mode>_hardfloat64): Likewise.
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(mov<mode>_64bit_dm): Likewise.
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(movtd_64bit_nodm): Likewise.
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(pre-reload move FP constant define_split): Delete define_split,
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since it is no longer used.
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(extenddftf2_internal): Remove GHF constraints that are not valid
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for extenddftf2.
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2015-03-19 Jan Hubicka <hubicka@ucw.cz>
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PR ipa/65380
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@ -432,9 +432,6 @@
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(define_predicate "easy_fp_constant"
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(match_code "const_double")
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{
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long k[4];
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REAL_VALUE_TYPE rv;
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if (GET_MODE (op) != mode
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|| (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
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return 0;
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@ -446,8 +443,7 @@
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return 1;
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/* The constant 0.0 is easy under VSX. */
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if ((mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode)
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&& VECTOR_UNIT_VSX_P (DFmode) && op == CONST0_RTX (mode))
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if (TARGET_VSX && SCALAR_FLOAT_MODE_P (mode) && op == CONST0_RTX (mode))
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return 1;
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if (DECIMAL_FLOAT_MODE_P (mode))
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@ -464,82 +460,28 @@
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return 0;
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#endif
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/* If we have real FPRs, consider floating point constants hard (other than
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0.0 under VSX), so that the constant gets pushed to memory during the
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early RTL phases. This has the advantage that double precision constants
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that can be represented in single precision without a loss of precision
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will use single precision loads. */
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switch (mode)
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{
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case TFmode:
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if (TARGET_E500_DOUBLE)
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return 0;
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REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
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REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
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return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
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&& num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
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&& num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
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&& num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
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case DFmode:
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/* Force constants to memory before reload to utilize
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compress_float_constant.
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Avoid this when flag_unsafe_math_optimizations is enabled
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because RDIV division to reciprocal optimization is not able
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to regenerate the division. */
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if (TARGET_E500_DOUBLE
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|| (!reload_in_progress && !reload_completed
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&& !flag_unsafe_math_optimizations))
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return 0;
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REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
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REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
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return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
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&& num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
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case SFmode:
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/* Force constants to memory before reload to utilize
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compress_float_constant.
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Avoid this when flag_unsafe_math_optimizations is enabled
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because RDIV division to reciprocal optimization is not able
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to regenerate the division. */
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if (!reload_in_progress && !reload_completed
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&& !flag_unsafe_math_optimizations)
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return 0;
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return 0;
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REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
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REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
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case DImode:
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return (num_insns_constant (op, DImode) <= 2);
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return num_insns_constant_wide (k[0]) == 1;
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case SImode:
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return 1;
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case DImode:
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return (num_insns_constant (op, DImode) <= 2);
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case SImode:
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return 1;
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default:
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gcc_unreachable ();
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}
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})
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;; Return 1 if the operand must be loaded from memory. This is used by a
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;; define_split to insure constants get pushed to the constant pool before
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;; reload. If -ffast-math is used, easy_fp_constant will allow move insns to
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;; have constants in order not interfere with reciprocal estimation. However,
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;; with -mupper-regs support, these constants must be moved to the constant
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;; pool before register allocation.
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(define_predicate "memory_fp_constant"
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(match_code "const_double")
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{
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if (TARGET_VSX && op == CONST0_RTX (mode))
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return 0;
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if (!TARGET_HARD_FLOAT || !TARGET_FPRS
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|| (mode == SFmode && !TARGET_SINGLE_FLOAT)
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|| (mode == DFmode && !TARGET_DOUBLE_FLOAT))
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return 0;
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return 1;
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default:
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gcc_unreachable ();
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}
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})
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;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
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@ -8048,8 +8048,8 @@
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}")
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(define_insn "mov<mode>_hardfloat"
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[(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,<f32_vsx>,<f32_vsx>,<f32_lr>,<f32_sm>,<f32_av>,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
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(match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,j,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r,h,0,G,Fn"))]
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[(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,<f32_vsx>,<f32_vsx>,!r,<f32_lr>,<f32_sm>,<f32_av>,Z,?<f32_dm>,?r,*c*l,!r,*h")
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(match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,j,j,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r,h,0"))]
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"(gpc_reg_operand (operands[0], <MODE>mode)
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|| gpc_reg_operand (operands[1], <MODE>mode))
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&& (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
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@ -8060,6 +8060,7 @@
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fmr %0,%1
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xxlor %x0,%x1,%x1
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xxlxor %x0,%x0,%x0
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li %0,0
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<f32_li>
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<f32_si>
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<f32_lv>
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@ -8068,11 +8069,9 @@
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mfvsrwz %0,%x1
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mt%0 %1
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mf%1 %0
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nop
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#
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#"
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[(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*,*,*")
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(set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
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nop"
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[(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,integer,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*")
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(set_attr "length" "4")])
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(define_insn "*mov<mode>_softfloat"
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[(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
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@ -8186,9 +8185,12 @@
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;; since the D-form version of the memory instructions does not need a GPR for
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;; reloading.
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;; If we have FPR registers, rs6000_emit_move has moved all constants to memory,
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;; except for 0.0 which can be created on VSX with an xor instruction.
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(define_insn "*mov<mode>_hardfloat32"
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[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,!r,!r,!r")
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(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,G,H,F"))]
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[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
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(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,j,r,Y,r"))]
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"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
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&& (gpc_reg_operand (operands[0], <MODE>mode)
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|| gpc_reg_operand (operands[1], <MODE>mode))"
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@ -8203,11 +8205,9 @@
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#
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#
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#
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#
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#
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#"
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[(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,two,fp,fp,*")
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(set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
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[(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,two,store,load,two")
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(set_attr "length" "4,4,4,4,4,4,4,8,8,8,8")])
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(define_insn "*mov<mode>_softfloat32"
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[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
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@ -8225,8 +8225,8 @@
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; ld/std require word-aligned displacements -> 'Y' constraint.
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; List Y->r and r->Y before r->r for reload.
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(define_insn "*mov<mode>_hardfloat64"
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[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,<f64_dm>")
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(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,r,h,0,G,H,F,wg,r,<f64_dm>,r"))]
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[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,<f64_dm>")
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(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,j,r,Y,r,r,h,0,wg,r,<f64_dm>,r"))]
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"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
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&& (gpc_reg_operand (operands[0], <MODE>mode)
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|| gpc_reg_operand (operands[1], <MODE>mode))"
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@ -8238,21 +8238,19 @@
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stxsd%U0x %x1,%y0
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xxlor %x0,%x1,%x1
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xxlxor %x0,%x0,%x0
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li %0,0
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std%U0%X0 %1,%0
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ld%U1%X1 %0,%1
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mr %0,%1
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mt%0 %1
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mf%1 %0
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nop
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#
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#
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#
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mftgpr %0,%1
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mffgpr %0,%1
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mfvsrd %0,%x1
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mtvsrd %x0,%1"
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[(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,store,load,*,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr,mftgpr,mffgpr")
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(set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
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[(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,vecsimple,vecsimple,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
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(set_attr "length" "4")])
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(define_insn "*mov<mode>_softfloat64"
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[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
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@ -8289,7 +8287,7 @@
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(define_insn_and_split "*mov<mode>_64bit_dm"
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[(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r,r,wm")
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(match_operand:FMOVE128 1 "input_operand" "d,m,d,j,r,jYGHF,r,wm,r"))]
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(match_operand:FMOVE128 1 "input_operand" "d,m,d,j,r,jY,r,wm,r"))]
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"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
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&& (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
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&& (gpc_reg_operand (operands[0], <MODE>mode)
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@ -8302,7 +8300,7 @@
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(define_insn_and_split "*movtd_64bit_nodm"
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[(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r")
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(match_operand:TD 1 "input_operand" "d,m,d,j,r,jYGHF,r"))]
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(match_operand:TD 1 "input_operand" "d,m,d,j,r,jY,r"))]
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"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
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&& (gpc_reg_operand (operands[0], TDmode)
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|| gpc_reg_operand (operands[1], TDmode))"
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@ -8314,7 +8312,7 @@
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(define_insn_and_split "*mov<mode>_32bit"
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[(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,ws,Y,r,r")
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(match_operand:FMOVE128 1 "input_operand" "d,m,d,j,r,jYGHF,r"))]
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(match_operand:FMOVE128 1 "input_operand" "d,m,d,j,r,jY,r"))]
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"TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
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&& (gpc_reg_operand (operands[0], <MODE>mode)
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|| gpc_reg_operand (operands[1], <MODE>mode))"
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@ -8336,21 +8334,6 @@
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{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
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[(set_attr "length" "20,20,16")])
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;; If we are using -ffast-math, easy_fp_constant assumes all constants are
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;; 'easy' in order to allow for reciprocal estimation. Make sure the constant
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;; is in the constant pool before reload occurs. This simplifies accessing
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;; scalars in the traditional Altivec registers.
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(define_split
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[(set (match_operand:SFDF 0 "register_operand" "")
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(match_operand:SFDF 1 "memory_fp_constant" ""))]
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"TARGET_<MODE>_FPR && flag_unsafe_math_optimizations
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&& !reload_in_progress && !reload_completed && !lra_in_progress"
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[(set (match_dup 0) (match_dup 2))]
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{
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operands[2] = validize_mem (force_const_mem (<MODE>mode, operands[1]));
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})
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(define_expand "extenddftf2"
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[(set (match_operand:TF 0 "nonimmediate_operand" "")
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(float_extend:TF (match_operand:DF 1 "input_operand" "")))]
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@ -8382,7 +8365,7 @@
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(define_insn_and_split "*extenddftf2_internal"
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[(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
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(float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
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(float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rm")))
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(use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
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"!TARGET_IEEEQUAD
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&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
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@ -1,3 +1,12 @@
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2015-03-17 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/65240
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* gcc/testsuite/g++.dg/pr65240.h: Add tests for PR 65240.
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* gcc/testsuite/g++.dg/pr65240-1.C: Likewise.
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* gcc/testsuite/g++.dg/pr65240-2.C: Likewise.
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* gcc/testsuite/g++.dg/pr65240-3.C: Likewise.
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* gcc/testsuite/g++.dg/pr65240-4.C: Likewise.
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2015-03-19 Vladimir Makarov <vmakarov@redhat.com>
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PR rtl-optimization/63491
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9
gcc/testsuite/g++.dg/pr65240-1.C
Normal file
9
gcc/testsuite/g++.dg/pr65240-1.C
Normal file
@ -0,0 +1,9 @@
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/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
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/* { dg-require-effective-target powerpc_p8vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
|
||||
/* { dg-options "-mcpu=power8 -O3 -ffast-math -mcmodel=small -mno-fp-in-toc" } */
|
||||
|
||||
/* target/65240, compiler got a 'insn does not satisfy its constraints' error. */
|
||||
|
||||
#include "pr65240.h"
|
||||
9
gcc/testsuite/g++.dg/pr65240-2.C
Normal file
9
gcc/testsuite/g++.dg/pr65240-2.C
Normal file
@ -0,0 +1,9 @@
|
||||
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_p8vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
|
||||
/* { dg-options "-mcpu=power8 -O3 -ffast-math -mcmodel=small -mfp-in-toc" } */
|
||||
|
||||
/* target/65240, compiler got a 'insn does not satisfy its constraints' error. */
|
||||
|
||||
#include "pr65240.h"
|
||||
9
gcc/testsuite/g++.dg/pr65240-3.C
Normal file
9
gcc/testsuite/g++.dg/pr65240-3.C
Normal file
@ -0,0 +1,9 @@
|
||||
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_p8vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
|
||||
/* { dg-options "-mcpu=power8 -O3 -ffast-math -mcmodel=medium" } */
|
||||
|
||||
/* target/65240, compiler got a 'insn does not satisfy its constraints' error. */
|
||||
|
||||
#include "pr65240.h"
|
||||
9
gcc/testsuite/g++.dg/pr65240-4.C
Normal file
9
gcc/testsuite/g++.dg/pr65240-4.C
Normal file
@ -0,0 +1,9 @@
|
||||
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
|
||||
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
|
||||
/* { dg-require-effective-target powerpc_vsx_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
|
||||
/* { dg-options "-mcpu=power7 -O3 -ffast-math" } */
|
||||
|
||||
/* target/65240, compiler got a 'insn does not satisfy its constraints' error. */
|
||||
|
||||
#include "pr65240.h"
|
||||
5518
gcc/testsuite/g++.dg/pr65240.h
Normal file
5518
gcc/testsuite/g++.dg/pr65240.h
Normal file
File diff suppressed because it is too large
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Reference in New Issue
Block a user