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[GCC][AARCH64] Canonicalize aarch64 widening simd plus insns

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Committed on behalf of matthew.malcomson@arm.com

2018-07-24  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/aarch64/aarch64-simd.md
	(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>): Split into...
	(aarch64_<ANY_EXTEND:su>subw<mode>): ... This...
	(aarch64_<ANY_EXTEND:su>addw<mode>): ... And this.
	(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>_internal): Split into...
	(aarch64_<ANY_EXTEND:su>subw<mode>_internal): ... This...
	(aarch64_<ANY_EXTEND:su>addw<mode>_internal): ... And this.
	(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>_internal): Split into...
	(aarch64_<ANY_EXTEND:su>subw2<mode>_internal): ... This...
	(aarch64_<ANY_EXTEND:su>addw2<mode>_internal): ... And this.

	* gcc.target/aarch64/vect-su-add-sub.c: New.

From-SVN: r262949
This commit is contained in:
Matthew Malcomson 2018-07-24 15:37:52 +00:00 committed by Kyrylo Tkachov
parent ebac3c0236
commit 8da03df567
4 changed files with 124 additions and 22 deletions
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13
gcc/ChangeLog
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@ -1,3 +1,16 @@
2018-07-24 Matthew Malcomson <matthew.malcomson@arm.com>
* config/aarch64/aarch64-simd.md
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>): Split into...
(aarch64_<ANY_EXTEND:su>subw<mode>): ... This...
(aarch64_<ANY_EXTEND:su>addw<mode>): ... And this.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>_internal): Split into...
(aarch64_<ANY_EXTEND:su>subw<mode>_internal): ... This...
(aarch64_<ANY_EXTEND:su>addw<mode>_internal): ... And this.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>_internal): Split into...
(aarch64_<ANY_EXTEND:su>subw2<mode>_internal): ... This...
(aarch64_<ANY_EXTEND:su>addw2<mode>_internal): ... And this.
2018-07-24 Jakub Jelinek <jakub@redhat.com>
PR middle-end/86627

80
gcc/config/aarch64/aarch64-simd.md
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@ -3303,38 +3303,74 @@
DONE;
})
(define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>"
(define_insn "aarch64_<ANY_EXTEND:su>subw<mode>"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(ADDSUB:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "w")
(ANY_EXTEND:<VWIDE>
(match_operand:VD_BHSI 2 "register_operand" "w"))))]
(minus:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "w")
(ANY_EXTEND:<VWIDE>
(match_operand:VD_BHSI 2 "register_operand" "w"))))]
"TARGET_SIMD"
"<ANY_EXTEND:su><ADDSUB:optab>w\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
[(set_attr "type" "neon_<ADDSUB:optab>_widen")]
"<ANY_EXTEND:su>subw\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
[(set_attr "type" "neon_sub_widen")]
)
(define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>_internal"
(define_insn "aarch64_<ANY_EXTEND:su>subw<mode>_internal"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(ADDSUB:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "w")
(ANY_EXTEND:<VWIDE>
(vec_select:<VHALF>
(match_operand:VQW 2 "register_operand" "w")
(match_operand:VQW 3 "vect_par_cnst_lo_half" "")))))]
(minus:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "w")
(ANY_EXTEND:<VWIDE>
(vec_select:<VHALF>
(match_operand:VQW 2 "register_operand" "w")
(match_operand:VQW 3 "vect_par_cnst_lo_half" "")))))]
"TARGET_SIMD"
"<ANY_EXTEND:su><ADDSUB:optab>w\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vhalftype>"
[(set_attr "type" "neon_<ADDSUB:optab>_widen")]
"<ANY_EXTEND:su>subw\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vhalftype>"
[(set_attr "type" "neon_sub_widen")]
)
(define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>_internal"
(define_insn "aarch64_<ANY_EXTEND:su>subw2<mode>_internal"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(ADDSUB:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "w")
(ANY_EXTEND:<VWIDE>
(vec_select:<VHALF>
(match_operand:VQW 2 "register_operand" "w")
(match_operand:VQW 3 "vect_par_cnst_hi_half" "")))))]
(minus:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "w")
(ANY_EXTEND:<VWIDE>
(vec_select:<VHALF>
(match_operand:VQW 2 "register_operand" "w")
(match_operand:VQW 3 "vect_par_cnst_hi_half" "")))))]
"TARGET_SIMD"
"<ANY_EXTEND:su><ADDSUB:optab>w2\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
[(set_attr "type" "neon_<ADDSUB:optab>_widen")]
"<ANY_EXTEND:su>subw2\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
[(set_attr "type" "neon_sub_widen")]
)
(define_insn "aarch64_<ANY_EXTEND:su>addw<mode>"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(plus:<VWIDE>
(ANY_EXTEND:<VWIDE> (match_operand:VD_BHSI 2 "register_operand" "w"))
(match_operand:<VWIDE> 1 "register_operand" "w")))]
"TARGET_SIMD"
"<ANY_EXTEND:su>addw\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
[(set_attr "type" "neon_add_widen")]
)
(define_insn "aarch64_<ANY_EXTEND:su>addw<mode>_internal"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(plus:<VWIDE>
(ANY_EXTEND:<VWIDE>
(vec_select:<VHALF>
(match_operand:VQW 2 "register_operand" "w")
(match_operand:VQW 3 "vect_par_cnst_lo_half" "")))
(match_operand:<VWIDE> 1 "register_operand" "w")))]
"TARGET_SIMD"
"<ANY_EXTEND:su>addw\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vhalftype>"
[(set_attr "type" "neon_add_widen")]
)
(define_insn "aarch64_<ANY_EXTEND:su>addw2<mode>_internal"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(plus:<VWIDE>
(ANY_EXTEND:<VWIDE>
(vec_select:<VHALF>
(match_operand:VQW 2 "register_operand" "w")
(match_operand:VQW 3 "vect_par_cnst_hi_half" "")))
(match_operand:<VWIDE> 1 "register_operand" "w")))]
"TARGET_SIMD"
"<ANY_EXTEND:su>addw2\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
[(set_attr "type" "neon_add_widen")]
)
(define_expand "aarch64_saddw2<mode>"

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2018-07-24 Matthew Malcomson <matthew.malcomson@arm.com>
* gcc.target/aarch64/vect-su-add-sub.c: New.
2018-07-24 Jakub Jelinek <jakub@redhat.com>
PR middle-end/86627

49
gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c Normal file
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@ -0,0 +1,49 @@
/* { dg-do compile } */
/* { dg-options "-O3" } */
/* Ensure we use the signed/unsigned extend vectorized add and sub
instructions. */
#define N 1024
int a[N];
long c[N];
long d[N];
unsigned int ua[N];
unsigned long uc[N];
unsigned long ud[N];
void
add ()
{
for (int i = 0; i < N; i++)
d[i] = a[i] + c[i];
}
/* { dg-final { scan-assembler-times "\[ \t\]saddw2\[ \t\]+" 1 } } */
/* { dg-final { scan-assembler-times "\[ \t\]saddw\[ \t\]+" 1 } } */
void
subtract ()
{
for (int i = 0; i < N; i++)
d[i] = c[i] - a[i];
}
/* { dg-final { scan-assembler-times "\[ \t\]ssubw2\[ \t\]+" 1 } } */
/* { dg-final { scan-assembler-times "\[ \t\]ssubw\[ \t\]+" 1 } } */
void
uadd ()
{
for (int i = 0; i < N; i++)
ud[i] = ua[i] + uc[i];
}
/* { dg-final { scan-assembler-times "\[ \t\]uaddw2\[ \t\]+" 1 } } */
/* { dg-final { scan-assembler-times "\[ \t\]uaddw\[ \t\]+" 1 } } */
void
usubtract ()
{
for (int i = 0; i < N; i++)
ud[i] = uc[i] - ua[i];
}
/* { dg-final { scan-assembler-times "\[ \t\]usubw2\[ \t\]+" 1 } } */
/* { dg-final { scan-assembler-times "\[ \t\]usubw\[ \t\]+" 1 } } */