re PR bootstrap/59913 ([4.9 Regresion] bootstrap failure on arm-linux-gnueabihf)
2014-02-04 Vladimir Makarov <vmakarov@redhat.com> PR bootstrap/59913 * lra-constraints.c (need_for_split_p): Use more 3 reloads as threshold for pseudo splitting. (update_ebb_live_info): Process call argument hard registers and hard registers from insn definition too. (max_small_class_regs_num): New constant. (inherit_in_ebb): Update live hard regs through EBBs. Update reloads_num only for small register classes. Don't split for outputs of jumps. From-SVN: r207485
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Vladimir Makarov
Vladimir Makarov
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66f206041a
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8e9d68a93b
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@ -1,3 +1,15 @@
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2014-02-04 Vladimir Makarov <vmakarov@redhat.com>
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PR bootstrap/59913
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* lra-constraints.c (need_for_split_p): Use more 3 reloads as
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threshold for pseudo splitting.
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(update_ebb_live_info): Process call argument hard registers and
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hard registers from insn definition too.
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(max_small_class_regs_num): New constant.
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(inherit_in_ebb): Update live hard regs through EBBs. Update
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reloads_num only for small register classes. Don't split for
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outputs of jumps.
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2014-02-04 Markus Trippelsdorf <markus@trippelsdorf.de>
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PR ipa/60058
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@ -4583,7 +4583,7 @@ need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno)
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impossibility to find hard register for reload pseudo of
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small register class. */
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&& (usage_insns[regno].reloads_num
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+ (regno < FIRST_PSEUDO_REGISTER ? 0 : 2) < reloads_num)
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+ (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num)
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&& (regno < FIRST_PSEUDO_REGISTER
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/* For short living pseudos, spilling + inheritance can
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be considered a substitution for splitting.
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@ -4840,7 +4840,7 @@ static void
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update_ebb_live_info (rtx head, rtx tail)
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{
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unsigned int j;
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int regno;
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int i, regno;
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bool live_p;
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rtx prev_insn, set;
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bool remove_p;
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@ -4898,6 +4898,7 @@ update_ebb_live_info (rtx head, rtx tail)
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if (! NONDEBUG_INSN_P (curr_insn))
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continue;
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curr_id = lra_get_insn_recog_data (curr_insn);
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curr_static_id = curr_id->insn_static_data;
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remove_p = false;
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if ((set = single_set (curr_insn)) != NULL_RTX && REG_P (SET_DEST (set))
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&& (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER
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@ -4908,11 +4909,23 @@ update_ebb_live_info (rtx head, rtx tail)
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for (reg = curr_id->regs; reg != NULL; reg = reg->next)
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if (reg->type == OP_OUT && ! reg->subreg_p)
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bitmap_clear_bit (&live_regs, reg->regno);
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for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
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if (reg->type == OP_OUT && ! reg->subreg_p)
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bitmap_clear_bit (&live_regs, reg->regno);
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/* Mark each used value as live. */
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for (reg = curr_id->regs; reg != NULL; reg = reg->next)
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if (reg->type != OP_OUT
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&& bitmap_bit_p (&check_only_regs, reg->regno))
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bitmap_set_bit (&live_regs, reg->regno);
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for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
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if (reg->type != OP_OUT
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&& bitmap_bit_p (&check_only_regs, reg->regno))
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bitmap_set_bit (&live_regs, reg->regno);
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if (curr_id->arg_hard_regs != NULL)
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/* Make argument hard registers live. */
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for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
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if (bitmap_bit_p (&check_only_regs, regno))
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bitmap_set_bit (&live_regs, regno);
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/* It is quite important to remove dead move insns because it
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means removing dead store. We don't need to process them for
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constraints. */
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@ -5002,6 +5015,14 @@ get_live_on_other_edges (basic_block from, basic_block to, bitmap res)
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/* Used as a temporary results of some bitmap calculations. */
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static bitmap_head temp_bitmap;
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/* We split for reloads of small class of hard regs. The following
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defines how many hard regs the class should have to be qualified as
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small. The code is mostly oriented to x86/x86-64 architecture
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where some insns need to use only specific register or pair of
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registers and these register can live in RTL explicitly, e.g. for
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parameter passing. */
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static const int max_small_class_regs_num = 2;
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/* Do inheritance/split transformations in EBB starting with HEAD and
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finishing on TAIL. We process EBB insns in the reverse order.
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Return true if we did any inheritance/split transformation in the
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@ -5036,7 +5057,8 @@ inherit_in_ebb (rtx head, rtx tail)
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bitmap_clear (&check_only_regs);
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last_processed_bb = NULL;
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CLEAR_HARD_REG_SET (potential_reload_hard_regs);
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CLEAR_HARD_REG_SET (live_hard_regs);
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COPY_HARD_REG_SET (live_hard_regs, eliminable_regset);
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IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs);
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/* We don't process new insns generated in the loop. */
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for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn)
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{
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@ -5062,9 +5084,6 @@ inherit_in_ebb (rtx head, rtx tail)
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|| (find_reg_note (last_insn,
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REG_NORETURN, NULL_RTX) == NULL_RTX
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&& ! SIBLING_CALL_P (last_insn))));
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REG_SET_TO_HARD_REG_SET (live_hard_regs, df_get_live_out (curr_bb));
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IOR_HARD_REG_SET (live_hard_regs, eliminable_regset);
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IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs);
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CLEAR_HARD_REG_SET (potential_reload_hard_regs);
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EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
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{
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@ -5098,7 +5117,8 @@ inherit_in_ebb (rtx head, rtx tail)
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&& (cl = lra_get_allocno_class (dst_regno)) != NO_REGS)
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{
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/* 'reload_pseudo <- original_pseudo'. */
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reloads_num++;
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if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
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reloads_num++;
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update_reloads_num_p = false;
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succ_p = false;
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if (usage_insns[src_regno].check == curr_usage_insns_check
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@ -5122,7 +5142,8 @@ inherit_in_ebb (rtx head, rtx tail)
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&& (next_usage_insns
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= usage_insns[dst_regno].insns) != NULL_RTX)
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{
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reloads_num++;
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if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
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reloads_num++;
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update_reloads_num_p = false;
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/* 'original_pseudo <- reload_pseudo'. */
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if (! JUMP_P (curr_insn)
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@ -5287,6 +5308,7 @@ inherit_in_ebb (rtx head, rtx tail)
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before_p = (JUMP_P (curr_insn)
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|| (CALL_P (curr_insn) && reg->type == OP_IN));
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if (NONDEBUG_INSN_P (curr_insn)
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&& (! JUMP_P (curr_insn) || reg->type == OP_IN)
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&& split_if_necessary (src_regno, reg->biggest_mode,
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potential_reload_hard_regs,
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before_p, curr_insn, max_uid))
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@ -5294,7 +5316,7 @@ inherit_in_ebb (rtx head, rtx tail)
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if (reg->subreg_p)
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lra_risky_transformations_p = true;
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change_p = true;
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/* Invalidate. */
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/* Invalidate. */
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usage_insns[src_regno].check = 0;
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if (before_p)
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use_insn = PREV_INSN (curr_insn);
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@ -5344,7 +5366,8 @@ inherit_in_ebb (rtx head, rtx tail)
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&& reg_renumber[regno] < 0
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&& (cl = lra_get_allocno_class (regno)) != NO_REGS))
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{
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reloads_num++;
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if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
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reloads_num++;
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if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
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IOR_HARD_REG_SET (potential_reload_hard_regs,
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reg_class_contents[cl]);
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