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Add sync_compare_and_swapsi and sync_test_and_setsi.

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2013-06-16  David Holsgrove <david.holsgrove@xilinx.com>

	Add sync_compare_and_swapsi and sync_test_and_setsi.

	* gcc/config/microblaze/sync.md: New file.
	* gcc/config/microblaze/microblaze.md: Add UNSPEC_SYNC_CAS,
	UNSPEC_SYNC_XCHG and include sync.md.
	* gcc/config/microblaze/microblaze.c: Add print_operand 'y'.
	* gcc/config/microblaze/constraints.md: Add memory_contraint
	'Q' which is a single register.

From-SVN: r200443
This commit is contained in:
David Holsgrove 2013-06-26 23:55:52 +00:00 committed by Michael Eager
parent 33e84ed46b
commit 8eedc3ebe7
5 changed files with 93 additions and 0 deletions
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9
gcc/ChangeLog
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@ -1,3 +1,12 @@
2013-06-16 David Holsgrove <david.holsgrove@xilinx.com>
* gcc/config/microblaze/sync.md: New file.
* gcc/config/microblaze/microblaze.md: Add UNSPEC_SYNC_CAS,
UNSPEC_SYNC_XCHG and include sync.md.
* gcc/config/microblaze/microblaze.c: Add print_operand 'y'.
* gcc/config/microblaze/constraints.md: Add memory_contraint
'Q' which is a single register.
2013-06-26 Thomas Schwinge <thomas@codesourcery.com>
* config/i386/gnu.h [TARGET_LIBC_PROVIDES_SSP]

5
gcc/config/microblaze/constraints.md
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@ -70,3 +70,8 @@
"Double word operand."
(and (match_code "mem")
(match_test "double_memory_operand (op, GET_MODE (op))")))
(define_memory_constraint "Q"
"Memory operand which is a single register."
(and (match_code "mem")
(match_test "GET_CODE ( XEXP (op, 0)) == REG")))

10
gcc/config/microblaze/microblaze.c
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@ -2118,6 +2118,7 @@ microblaze_initial_elimination_offset (int from, int to)
't' print 't' for EQ, 'f' for NE
'm' Print 1<<operand.
'i' Print 'i' if MEM operand has immediate value
'y' Print 'y' if MEM operand is single register
'o' Print operand address+4
'?' Print 'd' if we use a branch with delay slot instead of normal branch.
'h' Print high word of const_double (int or float) value as hex
@ -2288,6 +2289,15 @@ print_operand (FILE * file, rtx op, int letter)
rtx op4 = adjust_address (op, GET_MODE (op), 4);
output_address (XEXP (op4, 0));
}
else if (letter == 'y')
{
rtx mem_reg = XEXP (op, 0);
if (GET_CODE (mem_reg) == REG)
{
register int regnum = REGNO (mem_reg);
fprintf (file, "%s", reg_names[regnum]);
}
}
else
output_address (XEXP (op, 0));

4
gcc/config/microblaze/microblaze.md
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@ -41,6 +41,8 @@
(UNSPEC_CMP 104) ;; signed compare
(UNSPEC_CMPU 105) ;; unsigned compare
(UNSPEC_TLS 106) ;; jump table
(UNSPEC_SYNC_CAS 107) ;; Represent atomic compare swap.
(UNSPEC_SYNC_XCHG 108) ;; Represent atomic exchange.
])
@ -2221,3 +2223,5 @@
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set_attr "length" "4")])
(include "sync.md")

65
gcc/config/microblaze/sync.md Normal file
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@ -0,0 +1,65 @@
;; Machine description for Xilinx MicroBlaze synchronization instructions.
;; Copyright (C) 2011-2013
;; Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_insn "sync_compare_and_swapsi"
[(set (match_operand:SI 0 "register_operand" "=&d") ;; retval
(match_operand:SI 1 "nonimmediate_operand" "+Q")) ;; mem
(set (match_dup 1)
(unspec
[(match_operand:SI 2 "register_operand" "d") ;; oldval
(match_operand:SI 3 "register_operand" "d")] ;; newval
UNSPEC_SYNC_CAS))
(clobber (match_scratch:SI 4 "=&d"))] ;; scratch
""
{
output_asm_insn ("addc \tr0,r0,r0", operands);
output_asm_insn ("lwx \t%0,%y1,r0", operands);
output_asm_insn ("addic\t%4,r0,0", operands);
output_asm_insn ("bnei \t%4,.-8", operands);
output_asm_insn ("cmp \t%4,%0,%2", operands);
output_asm_insn ("bnei \t%4,.+16", operands);
output_asm_insn ("swx \t%3,%y1,r0", operands);
output_asm_insn ("addic\t%4,r0,0", operands);
output_asm_insn ("bnei \t%4,.-28", operands);
return "";
}
)
(define_insn "sync_test_and_setsi"
[(set (match_operand:SI 0 "register_operand" "=&d") ;; retval
(match_operand:SI 1 "nonimmediate_operand" "+Q")) ;; mem
(set (match_dup 1)
(unspec
[(match_operand:SI 2 "register_operand" "d")] ;; value
UNSPEC_SYNC_XCHG))
(clobber (match_scratch:SI 3 "=&d"))] ;; scratch
""
{
output_asm_insn ("addc \tr0,r0,r0", operands);
output_asm_insn ("lwx \t%0,%y1,r0", operands);
output_asm_insn ("addic\t%3,r0,0", operands);
output_asm_insn ("bnei \t%3,.-8", operands);
output_asm_insn ("swx \t%2,%y1,r0", operands);
output_asm_insn ("addic\t%3,r0,0", operands);
output_asm_insn ("bnei \t%3,.-20", operands);
return "";
}
)