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rs6000.c (print_operand): Check (TARGET_SPE || TARGET_E500_DOUBLE), not TARGET_E500, for %y. 

* config/rs6000/rs6000.c (print_operand): Check (TARGET_SPE ||
	TARGET_E500_DOUBLE), not TARGET_E500, for %y.
	(rs6000_generate_compare, rs6000_emit_sCOND, output_cbranch,
	rs6000_emit_cmove): Don't check TARGET_E500.
	* config/rs6000/rs6000.md (bunordered, bordered, sunordered,
	sordered): Don't check TARGET_E500.

From-SVN: r120339
This commit is contained in:
Joseph Myers 2007-01-02 13:03:59 +00:00 committed by Joseph Myers
parent d8934cf1e3
commit 8ef65e3da8
3 changed files with 22 additions and 12 deletions
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9
gcc/ChangeLog
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@ -1,3 +1,12 @@
2007-01-02 Joseph Myers <joseph@codesourcery.com>
* config/rs6000/rs6000.c (print_operand): Check (TARGET_SPE ||
TARGET_E500_DOUBLE), not TARGET_E500, for %y.
(rs6000_generate_compare, rs6000_emit_sCOND, output_cbranch,
rs6000_emit_cmove): Don't check TARGET_E500.
* config/rs6000/rs6000.md (bunordered, bordered, sunordered,
sordered): Don't check TARGET_E500.
2007-01-01 Eric Christopher <echristo@apple.com> 2007-01-01 Eric Christopher <echristo@apple.com>
* config/mips/mips.c (mips_regno_mode_ok_for_base_p): Use * config/mips/mips.c (mips_regno_mode_ok_for_base_p): Use

15
gcc/config/rs6000/rs6000.c
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@ -1,6 +1,6 @@
/* Subroutines used for code generation on IBM RS/6000. /* Subroutines used for code generation on IBM RS/6000.
Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2001, 2002, 2003, 2004, 2005, 2006 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
Free Software Foundation, Inc. Free Software Foundation, Inc.
Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
@ -11016,7 +11016,8 @@ print_operand (FILE *file, rtx x, int code)
tmp = XEXP (x, 0); tmp = XEXP (x, 0);
/* Ugly hack because %y is overloaded. */ /* Ugly hack because %y is overloaded. */
if (TARGET_E500 && GET_MODE_SIZE (GET_MODE (x)) == 8) if ((TARGET_SPE || TARGET_E500_DOUBLE)
&& GET_MODE_SIZE (GET_MODE (x)) == 8)
{ {
/* Handle [reg]. */ /* Handle [reg]. */
if (GET_CODE (tmp) == REG) if (GET_CODE (tmp) == REG)
@ -11315,7 +11316,7 @@ rs6000_generate_compare (enum rtx_code code)
compare_result = gen_reg_rtx (comp_mode); compare_result = gen_reg_rtx (comp_mode);
/* E500 FP compare instructions on the GPRs. Yuck! */ /* E500 FP compare instructions on the GPRs. Yuck! */
if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
&& rs6000_compare_fp_p) && rs6000_compare_fp_p)
{ {
rtx cmp, or_result, compare_result2; rtx cmp, or_result, compare_result2;
@ -11508,7 +11509,7 @@ rs6000_generate_compare (enum rtx_code code)
under flag_finite_math_only we don't bother. */ under flag_finite_math_only we don't bother. */
if (rs6000_compare_fp_p if (rs6000_compare_fp_p
&& !flag_finite_math_only && !flag_finite_math_only
&& !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS) && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
&& (code == LE || code == GE && (code == LE || code == GE
|| code == UNEQ || code == LTGT || code == UNEQ || code == LTGT
|| code == UNGT || code == UNLT)) || code == UNGT || code == UNLT))
@ -11558,7 +11559,7 @@ rs6000_emit_sCOND (enum rtx_code code, rtx result)
condition_rtx = rs6000_generate_compare (code); condition_rtx = rs6000_generate_compare (code);
cond_code = GET_CODE (condition_rtx); cond_code = GET_CODE (condition_rtx);
if (TARGET_E500 && rs6000_compare_fp_p if (rs6000_compare_fp_p
&& !TARGET_FPRS && TARGET_HARD_FLOAT) && !TARGET_FPRS && TARGET_HARD_FLOAT)
{ {
rtx t; rtx t;
@ -11665,7 +11666,7 @@ output_cbranch (rtx op, const char *label, int reversed, rtx insn)
code = reverse_condition (code); code = reverse_condition (code);
} }
if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode) if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
{ {
/* The efscmp/tst* instructions twiddle bit 2, which maps nicely /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
to the GT bit. */ to the GT bit. */
@ -12081,7 +12082,7 @@ rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
return 0; return 0;
} }
else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS else if (TARGET_HARD_FLOAT && !TARGET_FPRS
&& SCALAR_FLOAT_MODE_P (compare_mode)) && SCALAR_FLOAT_MODE_P (compare_mode))
return 0; return 0;

10
gcc/config/rs6000/rs6000.md
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@ -1,6 +1,6 @@
;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
;; Free Software Foundation, Inc. ;; Free Software Foundation, Inc.
;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
@ -11421,12 +11421,12 @@
(define_expand "bunordered" (define_expand "bunordered"
[(use (match_operand 0 "" ""))] [(use (match_operand 0 "" ""))]
"! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
"{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
(define_expand "bordered" (define_expand "bordered"
[(use (match_operand 0 "" ""))] [(use (match_operand 0 "" ""))]
"! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
"{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
(define_expand "buneq" (define_expand "buneq"
@ -11555,12 +11555,12 @@
(define_expand "sunordered" (define_expand "sunordered"
[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
"! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
"{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }") "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
(define_expand "sordered" (define_expand "sordered"
[(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
"! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
"{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }") "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
(define_expand "suneq" (define_expand "suneq"