Revert [ARM] Remove neon-testgen.ml and generated tests.
From-SVN: r230296
This commit is contained in:
Christophe Lyon
parent
8014404589
commit
8f215e0f07
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@ -1,3 +1,13 @@
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2015-11-13 Christophe Lyon <christophe.lyon@linaro.org>
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Revert [ARM] Remove neon-testgen.ml and generated tests.
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2015-11-12 Christophe Lyon <christophe.lyon@linaro.org>
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[ARM] Remove neon-testgen.ml and generated tests.
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* config/arm/neon-testgen.ml: Remove.
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2015-11-13 Richard Biener <rguenther@suse.de>
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* tree-vect-loop.c (vect_analyze_loop_2): Add fatal parameter.
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@ -0,0 +1,324 @@
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(* Auto-generate ARM Neon intrinsics tests.
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Copyright (C) 2006-2015 Free Software Foundation, Inc.
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Contributed by CodeSourcery.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3, or (at your option) any later
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version.
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GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>.
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This is an O'Caml program. The O'Caml compiler is available from:
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http://caml.inria.fr/
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Or from your favourite OS's friendly packaging system. Tested with version
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3.09.2, though other versions will probably work too.
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Compile with:
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ocamlc -c neon.ml
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ocamlc -o neon-testgen neon.cmo neon-testgen.ml
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Run with:
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cd /path/to/gcc/testsuite/gcc.target/arm/neon
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/path/to/neon-testgen
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*)
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open Neon
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type c_type_flags = Pointer | Const
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(* Open a test source file. *)
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let open_test_file dir name =
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try
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open_out (dir ^ "/" ^ name ^ ".c")
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with Sys_error str ->
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failwith ("Could not create test source file " ^ name ^ ": " ^ str)
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(* Emit prologue code to a test source file. *)
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let emit_prologue chan test_name effective_target compile_test_optim =
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Printf.fprintf chan "/* Test the `%s' ARM Neon intrinsic. */\n" test_name;
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Printf.fprintf chan "/* This file was autogenerated by neon-testgen. */\n\n";
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Printf.fprintf chan "/* { dg-do assemble } */\n";
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Printf.fprintf chan "/* { dg-require-effective-target %s_ok } */\n"
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effective_target;
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Printf.fprintf chan "/* { dg-options \"-save-temps %s\" } */\n" compile_test_optim;
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Printf.fprintf chan "/* { dg-add-options %s } */\n" effective_target;
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Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n"
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(* Emit declarations of variables that are going to be passed
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to an intrinsic, together with one to take a returned value if needed. *)
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let emit_variables chan c_types features spaces =
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let emit () =
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ignore (
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List.fold_left (fun arg_number -> fun (flags, ty) ->
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let pointer_bit =
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if List.mem Pointer flags then "*" else ""
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in
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(* Const arguments to builtins are directly
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written in as constants. *)
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if not (List.mem Const flags) then
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Printf.fprintf chan "%s%s %sarg%d_%s;\n"
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spaces ty pointer_bit arg_number ty;
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arg_number + 1)
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0 (List.tl c_types))
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in
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match c_types with
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(_, return_ty) :: tys ->
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if return_ty <> "void" then begin
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(* The intrinsic returns a value. We need to do explicit register
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allocation for vget_low tests or they fail because of copy
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elimination. *)
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((if List.mem Fixed_vector_reg features then
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Printf.fprintf chan "%sregister %s out_%s asm (\"d18\");\n"
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spaces return_ty return_ty
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else if List.mem Fixed_core_reg features then
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Printf.fprintf chan "%sregister %s out_%s asm (\"r0\");\n"
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spaces return_ty return_ty
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else
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Printf.fprintf chan "%s%s out_%s;\n" spaces return_ty return_ty);
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emit ())
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end else
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(* The intrinsic does not return a value. *)
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emit ()
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| _ -> assert false
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(* Emit code to call an intrinsic. *)
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let emit_call chan const_valuator c_types name elt_ty =
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(if snd (List.hd c_types) <> "void" then
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Printf.fprintf chan " out_%s = " (snd (List.hd c_types))
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else
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Printf.fprintf chan " ");
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Printf.fprintf chan "%s_%s (" (intrinsic_name name) (string_of_elt elt_ty);
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let print_arg chan arg_number (flags, ty) =
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(* If the argument is of const type, then directly write in the
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constant now. *)
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if List.mem Const flags then
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match const_valuator with
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None ->
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if List.mem Pointer flags then
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Printf.fprintf chan "0"
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else
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Printf.fprintf chan "1"
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| Some f -> Printf.fprintf chan "%s" (string_of_int (f arg_number))
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else
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Printf.fprintf chan "arg%d_%s" arg_number ty
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in
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let rec print_args arg_number tys =
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match tys with
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[] -> ()
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| [ty] -> print_arg chan arg_number ty
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| ty::tys ->
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print_arg chan arg_number ty;
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Printf.fprintf chan ", ";
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print_args (arg_number + 1) tys
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in
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print_args 0 (List.tl c_types);
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Printf.fprintf chan ");\n"
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(* Emit epilogue code to a test source file. *)
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let emit_epilogue chan features regexps =
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let no_op = List.exists (fun feature -> feature = No_op) features in
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Printf.fprintf chan "}\n\n";
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if not no_op then
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List.iter (fun regexp ->
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Printf.fprintf chan
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"/* { dg-final { scan-assembler \"%s\" } } */\n" regexp)
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regexps
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else
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()
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(* Check a list of C types to determine which ones are pointers and which
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ones are const. *)
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let check_types tys =
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let tys' =
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List.map (fun ty ->
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let len = String.length ty in
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if len > 2 && String.get ty (len - 2) = ' '
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&& String.get ty (len - 1) = '*'
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then ([Pointer], String.sub ty 0 (len - 2))
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else ([], ty)) tys
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in
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List.map (fun (flags, ty) ->
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if String.length ty > 6 && String.sub ty 0 6 = "const "
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then (Const :: flags, String.sub ty 6 ((String.length ty) - 6))
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else (flags, ty)) tys'
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(* Work out what the effective target should be. *)
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let effective_target features =
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try
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match List.find (fun feature ->
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match feature with Requires_feature _ -> true
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| Requires_arch _ -> true
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| Requires_FP_bit 1 -> true
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| _ -> false)
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features with
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Requires_feature "FMA" -> "arm_neonv2"
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| Requires_feature "CRYPTO" -> "arm_crypto"
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| Requires_arch 8 -> "arm_v8_neon"
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| Requires_FP_bit 1 -> "arm_neon_fp16"
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| _ -> assert false
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with Not_found -> "arm_neon"
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(* Work out what the testcase optimization level should be, default to -O0. *)
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let compile_test_optim features =
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try
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match List.find (fun feature ->
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match feature with Compiler_optim _ -> true
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| _ -> false)
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features with
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Compiler_optim opt -> opt
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| _ -> assert false
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with Not_found -> "-O0"
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(* Given an intrinsic shape, produce a regexp that will match
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the right-hand sides of instructions generated by an intrinsic of
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that shape. *)
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let rec analyze_shape shape =
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let rec n_things n thing =
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match n with
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0 -> []
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| n -> thing :: (n_things (n - 1) thing)
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in
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let rec analyze_shape_elt elt =
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match elt with
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Dreg -> "\\[dD\\]\\[0-9\\]+"
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| Qreg -> "\\[qQ\\]\\[0-9\\]+"
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| Corereg -> "\\[rR\\]\\[0-9\\]+"
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| Immed -> "#\\[0-9\\]+"
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| VecArray (1, elt) ->
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let elt_regexp = analyze_shape_elt elt in
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"((\\\\\\{" ^ elt_regexp ^ "\\\\\\})|(" ^ elt_regexp ^ "))"
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| VecArray (n, elt) ->
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let elt_regexp = analyze_shape_elt elt in
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let alt1 = elt_regexp ^ "-" ^ elt_regexp in
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let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in
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"\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}"
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| (PtrTo elt | CstPtrTo elt) ->
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"\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\(:\\[0-9\\]+\\)?\\\\\\]"
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| Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
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| Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
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| All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]"
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| Alternatives (elts) -> "(" ^ (String.concat "|" (List.map analyze_shape_elt elts)) ^ ")"
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in
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match shape with
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All (n, elt) -> commas analyze_shape_elt (n_things n elt) ""
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| Long -> (analyze_shape_elt Qreg) ^ ", " ^ (analyze_shape_elt Dreg) ^
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", " ^ (analyze_shape_elt Dreg)
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| Long_noreg elt -> (analyze_shape_elt elt) ^ ", " ^ (analyze_shape_elt elt)
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| Wide -> (analyze_shape_elt Qreg) ^ ", " ^ (analyze_shape_elt Qreg) ^
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", " ^ (analyze_shape_elt Dreg)
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| Wide_noreg elt -> analyze_shape (Long_noreg elt)
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| Narrow -> (analyze_shape_elt Dreg) ^ ", " ^ (analyze_shape_elt Qreg) ^
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", " ^ (analyze_shape_elt Qreg)
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| Use_operands elts -> commas analyze_shape_elt (Array.to_list elts) ""
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| By_scalar Dreg ->
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analyze_shape (Use_operands [| Dreg; Dreg; Element_of_dreg |])
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| By_scalar Qreg ->
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analyze_shape (Use_operands [| Qreg; Qreg; Element_of_dreg |])
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| By_scalar _ -> assert false
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| Wide_lane ->
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analyze_shape (Use_operands [| Qreg; Dreg; Element_of_dreg |])
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| Wide_scalar ->
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analyze_shape (Use_operands [| Qreg; Dreg; Element_of_dreg |])
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| Pair_result elt ->
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let elt_regexp = analyze_shape_elt elt in
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elt_regexp ^ ", " ^ elt_regexp
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| Unary_scalar _ -> "FIXME Unary_scalar"
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| Binary_imm elt -> analyze_shape (Use_operands [| elt; elt; Immed |])
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| Narrow_imm -> analyze_shape (Use_operands [| Dreg; Qreg; Immed |])
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| Long_imm -> analyze_shape (Use_operands [| Qreg; Dreg; Immed |])
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(* Generate tests for one intrinsic. *)
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let test_intrinsic dir opcode features shape name munge elt_ty =
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(* Open the test source file. *)
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let test_name = name ^ (string_of_elt elt_ty) in
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let chan = open_test_file dir test_name in
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(* Work out what argument and return types the intrinsic has. *)
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let c_arity, new_elt_ty = munge shape elt_ty in
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let c_types = check_types (strings_of_arity c_arity) in
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(* Extract any constant valuator (a function specifying what constant
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values are to be written into the intrinsic call) from the features
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list. *)
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let const_valuator =
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try
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match (List.find (fun feature -> match feature with
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Const_valuator _ -> true
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| _ -> false) features) with
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Const_valuator f -> Some f
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| _ -> assert false
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with Not_found -> None
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in
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(* Work out what instruction name(s) to expect. *)
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let insns = get_insn_names features name in
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let no_suffix = (new_elt_ty = NoElts) in
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let insns =
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if no_suffix then insns
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else List.map (fun insn ->
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let suffix = string_of_elt_dots new_elt_ty in
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insn ^ "\\." ^ suffix) insns
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in
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(* Construct a regexp to match against the expected instruction name(s). *)
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let insn_regexp =
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match insns with
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[] -> assert false
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| [insn] -> insn
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| _ ->
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let rec calc_regexp insns cur_regexp =
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match insns with
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[] -> cur_regexp
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| [insn] -> cur_regexp ^ "(" ^ insn ^ "))"
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| insn::insns -> calc_regexp insns (cur_regexp ^ "(" ^ insn ^ ")|")
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in calc_regexp insns "("
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in
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(* Construct regexps to match against the instructions that this
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intrinsic expands to. Watch out for any writeback character and
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comments after the instruction. *)
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let regexps = List.map (fun regexp -> insn_regexp ^ "\\[ \t\\]+" ^ regexp ^
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"!?\\(\\[ \t\\]+@\\[a-zA-Z0-9 \\]+\\)?\\n")
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(analyze_all_shapes features shape analyze_shape)
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in
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let effective_target = effective_target features in
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let compile_test_optim = compile_test_optim features
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in
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(* Emit file and function prologues. *)
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emit_prologue chan test_name effective_target compile_test_optim;
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if (compare compile_test_optim "-O0") <> 0 then
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(* Emit variable declarations. *)
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emit_variables chan c_types features "";
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Printf.fprintf chan "void test_%s (void)\n{\n" test_name;
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if compare compile_test_optim "-O0" = 0 then
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(* Emit variable declarations. *)
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emit_variables chan c_types features " ";
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Printf.fprintf chan "\n";
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(* Emit the call to the intrinsic. *)
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emit_call chan const_valuator c_types name elt_ty;
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(* Emit the function epilogue and the DejaGNU scan-assembler directives. *)
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emit_epilogue chan features regexps;
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(* Close the test file. *)
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close_out chan
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(* Generate tests for one element of the "ops" table. *)
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let test_intrinsic_group dir (opcode, features, shape, name, munge, types) =
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List.iter (test_intrinsic dir opcode features shape name munge) types
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(* Program entry point. *)
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let _ =
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let directory = if Array.length Sys.argv <> 1 then Sys.argv.(1) else "." in
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List.iter (test_intrinsic_group directory) (reinterp @ reinterpq @ ops)
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,20 @@
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/* Test the `vRaddhns16' ARM Neon intrinsic. */
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/* This file was autogenerated by neon-testgen. */
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/* { dg-do assemble } */
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/* { dg-require-effective-target arm_neon_ok } */
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/* { dg-options "-save-temps -O0" } */
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/* { dg-add-options arm_neon } */
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#include "arm_neon.h"
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void test_vRaddhns16 (void)
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{
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int8x8_t out_int8x8_t;
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int16x8_t arg0_int16x8_t;
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int16x8_t arg1_int16x8_t;
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out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
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}
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/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
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|
|
@ -0,0 +1,20 @@
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/* Test the `vRaddhns32' ARM Neon intrinsic. */
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/* This file was autogenerated by neon-testgen. */
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/* { dg-do assemble } */
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/* { dg-require-effective-target arm_neon_ok } */
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/* { dg-options "-save-temps -O0" } */
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/* { dg-add-options arm_neon } */
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#include "arm_neon.h"
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void test_vRaddhns32 (void)
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{
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int16x4_t out_int16x4_t;
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int32x4_t arg0_int32x4_t;
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int32x4_t arg1_int32x4_t;
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out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
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}
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/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
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|
|
@ -0,0 +1,20 @@
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/* Test the `vRaddhns64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
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/* { dg-do assemble } */
|
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/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
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#include "arm_neon.h"
|
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|
||||
void test_vRaddhns64 (void)
|
||||
{
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int32x2_t out_int32x2_t;
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int64x2_t arg0_int64x2_t;
|
||||
int64x2_t arg1_int64x2_t;
|
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out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
|
||||
}
|
||||
|
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/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRaddhnu16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRaddhnu16 (void)
|
||||
{
|
||||
uint8x8_t out_uint8x8_t;
|
||||
uint16x8_t arg0_uint16x8_t;
|
||||
uint16x8_t arg1_uint16x8_t;
|
||||
|
||||
out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vraddhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRaddhnu32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRaddhnu32 (void)
|
||||
{
|
||||
uint16x4_t out_uint16x4_t;
|
||||
uint32x4_t arg0_uint32x4_t;
|
||||
uint32x4_t arg1_uint32x4_t;
|
||||
|
||||
out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vraddhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRaddhnu64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRaddhnu64 (void)
|
||||
{
|
||||
uint32x2_t out_uint32x2_t;
|
||||
uint64x2_t arg0_uint64x2_t;
|
||||
uint64x2_t arg1_uint64x2_t;
|
||||
|
||||
out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vraddhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRhaddQs16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRhaddQs16 (void)
|
||||
{
|
||||
int16x8_t out_int16x8_t;
|
||||
int16x8_t arg0_int16x8_t;
|
||||
int16x8_t arg1_int16x8_t;
|
||||
|
||||
out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRhaddQs32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRhaddQs32 (void)
|
||||
{
|
||||
int32x4_t out_int32x4_t;
|
||||
int32x4_t arg0_int32x4_t;
|
||||
int32x4_t arg1_int32x4_t;
|
||||
|
||||
out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRhaddQs8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRhaddQs8 (void)
|
||||
{
|
||||
int8x16_t out_int8x16_t;
|
||||
int8x16_t arg0_int8x16_t;
|
||||
int8x16_t arg1_int8x16_t;
|
||||
|
||||
out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRhaddQu16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRhaddQu16 (void)
|
||||
{
|
||||
uint16x8_t out_uint16x8_t;
|
||||
uint16x8_t arg0_uint16x8_t;
|
||||
uint16x8_t arg1_uint16x8_t;
|
||||
|
||||
out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRhaddQu32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRhaddQu32 (void)
|
||||
{
|
||||
uint32x4_t out_uint32x4_t;
|
||||
uint32x4_t arg0_uint32x4_t;
|
||||
uint32x4_t arg1_uint32x4_t;
|
||||
|
||||
out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRhaddQu8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRhaddQu8 (void)
|
||||
{
|
||||
uint8x16_t out_uint8x16_t;
|
||||
uint8x16_t arg0_uint8x16_t;
|
||||
uint8x16_t arg1_uint8x16_t;
|
||||
|
||||
out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRhadds16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRhadds16 (void)
|
||||
{
|
||||
int16x4_t out_int16x4_t;
|
||||
int16x4_t arg0_int16x4_t;
|
||||
int16x4_t arg1_int16x4_t;
|
||||
|
||||
out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrhadd\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRhadds32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRhadds32 (void)
|
||||
{
|
||||
int32x2_t out_int32x2_t;
|
||||
int32x2_t arg0_int32x2_t;
|
||||
int32x2_t arg1_int32x2_t;
|
||||
|
||||
out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrhadd\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRhadds8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRhadds8 (void)
|
||||
{
|
||||
int8x8_t out_int8x8_t;
|
||||
int8x8_t arg0_int8x8_t;
|
||||
int8x8_t arg1_int8x8_t;
|
||||
|
||||
out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrhadd\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRhaddu16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRhaddu16 (void)
|
||||
{
|
||||
uint16x4_t out_uint16x4_t;
|
||||
uint16x4_t arg0_uint16x4_t;
|
||||
uint16x4_t arg1_uint16x4_t;
|
||||
|
||||
out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrhadd\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRhaddu32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRhaddu32 (void)
|
||||
{
|
||||
uint32x2_t out_uint32x2_t;
|
||||
uint32x2_t arg0_uint32x2_t;
|
||||
uint32x2_t arg1_uint32x2_t;
|
||||
|
||||
out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrhadd\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRhaddu8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRhaddu8 (void)
|
||||
{
|
||||
uint8x8_t out_uint8x8_t;
|
||||
uint8x8_t arg0_uint8x8_t;
|
||||
uint8x8_t arg1_uint8x8_t;
|
||||
|
||||
out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrhadd\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshlQs16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshlQs16 (void)
|
||||
{
|
||||
int16x8_t out_int16x8_t;
|
||||
int16x8_t arg0_int16x8_t;
|
||||
int16x8_t arg1_int16x8_t;
|
||||
|
||||
out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshlQs32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshlQs32 (void)
|
||||
{
|
||||
int32x4_t out_int32x4_t;
|
||||
int32x4_t arg0_int32x4_t;
|
||||
int32x4_t arg1_int32x4_t;
|
||||
|
||||
out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshlQs64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshlQs64 (void)
|
||||
{
|
||||
int64x2_t out_int64x2_t;
|
||||
int64x2_t arg0_int64x2_t;
|
||||
int64x2_t arg1_int64x2_t;
|
||||
|
||||
out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshlQs8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshlQs8 (void)
|
||||
{
|
||||
int8x16_t out_int8x16_t;
|
||||
int8x16_t arg0_int8x16_t;
|
||||
int8x16_t arg1_int8x16_t;
|
||||
|
||||
out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshlQu16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshlQu16 (void)
|
||||
{
|
||||
uint16x8_t out_uint16x8_t;
|
||||
uint16x8_t arg0_uint16x8_t;
|
||||
int16x8_t arg1_int16x8_t;
|
||||
|
||||
out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshlQu32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshlQu32 (void)
|
||||
{
|
||||
uint32x4_t out_uint32x4_t;
|
||||
uint32x4_t arg0_uint32x4_t;
|
||||
int32x4_t arg1_int32x4_t;
|
||||
|
||||
out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshlQu64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshlQu64 (void)
|
||||
{
|
||||
uint64x2_t out_uint64x2_t;
|
||||
uint64x2_t arg0_uint64x2_t;
|
||||
int64x2_t arg1_int64x2_t;
|
||||
|
||||
out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshlQu8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshlQu8 (void)
|
||||
{
|
||||
uint8x16_t out_uint8x16_t;
|
||||
uint8x16_t arg0_uint8x16_t;
|
||||
int8x16_t arg1_int8x16_t;
|
||||
|
||||
out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshls16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshls16 (void)
|
||||
{
|
||||
int16x4_t out_int16x4_t;
|
||||
int16x4_t arg0_int16x4_t;
|
||||
int16x4_t arg1_int16x4_t;
|
||||
|
||||
out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshls32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshls32 (void)
|
||||
{
|
||||
int32x2_t out_int32x2_t;
|
||||
int32x2_t arg0_int32x2_t;
|
||||
int32x2_t arg1_int32x2_t;
|
||||
|
||||
out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshls64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshls64 (void)
|
||||
{
|
||||
int64x1_t out_int64x1_t;
|
||||
int64x1_t arg0_int64x1_t;
|
||||
int64x1_t arg1_int64x1_t;
|
||||
|
||||
out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshls8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshls8 (void)
|
||||
{
|
||||
int8x8_t out_int8x8_t;
|
||||
int8x8_t arg0_int8x8_t;
|
||||
int8x8_t arg1_int8x8_t;
|
||||
|
||||
out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshlu16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshlu16 (void)
|
||||
{
|
||||
uint16x4_t out_uint16x4_t;
|
||||
uint16x4_t arg0_uint16x4_t;
|
||||
int16x4_t arg1_int16x4_t;
|
||||
|
||||
out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshlu32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshlu32 (void)
|
||||
{
|
||||
uint32x2_t out_uint32x2_t;
|
||||
uint32x2_t arg0_uint32x2_t;
|
||||
int32x2_t arg1_int32x2_t;
|
||||
|
||||
out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshlu64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshlu64 (void)
|
||||
{
|
||||
uint64x1_t out_uint64x1_t;
|
||||
uint64x1_t arg0_uint64x1_t;
|
||||
int64x1_t arg1_int64x1_t;
|
||||
|
||||
out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRshlu8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshlu8 (void)
|
||||
{
|
||||
uint8x8_t out_uint8x8_t;
|
||||
uint8x8_t arg0_uint8x8_t;
|
||||
int8x8_t arg1_int8x8_t;
|
||||
|
||||
out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshl\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshrQ_ns16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshrQ_ns16 (void)
|
||||
{
|
||||
int16x8_t out_int16x8_t;
|
||||
int16x8_t arg0_int16x8_t;
|
||||
|
||||
out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshrQ_ns32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshrQ_ns32 (void)
|
||||
{
|
||||
int32x4_t out_int32x4_t;
|
||||
int32x4_t arg0_int32x4_t;
|
||||
|
||||
out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshrQ_ns64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshrQ_ns64 (void)
|
||||
{
|
||||
int64x2_t out_int64x2_t;
|
||||
int64x2_t arg0_int64x2_t;
|
||||
|
||||
out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshrQ_ns8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshrQ_ns8 (void)
|
||||
{
|
||||
int8x16_t out_int8x16_t;
|
||||
int8x16_t arg0_int8x16_t;
|
||||
|
||||
out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshrQ_nu16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshrQ_nu16 (void)
|
||||
{
|
||||
uint16x8_t out_uint16x8_t;
|
||||
uint16x8_t arg0_uint16x8_t;
|
||||
|
||||
out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshrQ_nu32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshrQ_nu32 (void)
|
||||
{
|
||||
uint32x4_t out_uint32x4_t;
|
||||
uint32x4_t arg0_uint32x4_t;
|
||||
|
||||
out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshrQ_nu64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshrQ_nu64 (void)
|
||||
{
|
||||
uint64x2_t out_uint64x2_t;
|
||||
uint64x2_t arg0_uint64x2_t;
|
||||
|
||||
out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshrQ_nu8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshrQ_nu8 (void)
|
||||
{
|
||||
uint8x16_t out_uint8x16_t;
|
||||
uint8x16_t arg0_uint8x16_t;
|
||||
|
||||
out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshr_ns16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshr_ns16 (void)
|
||||
{
|
||||
int16x4_t out_int16x4_t;
|
||||
int16x4_t arg0_int16x4_t;
|
||||
|
||||
out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshr_ns32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshr_ns32 (void)
|
||||
{
|
||||
int32x2_t out_int32x2_t;
|
||||
int32x2_t arg0_int32x2_t;
|
||||
|
||||
out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshr_ns64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshr_ns64 (void)
|
||||
{
|
||||
int64x1_t out_int64x1_t;
|
||||
int64x1_t arg0_int64x1_t;
|
||||
|
||||
out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshr_ns8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshr_ns8 (void)
|
||||
{
|
||||
int8x8_t out_int8x8_t;
|
||||
int8x8_t arg0_int8x8_t;
|
||||
|
||||
out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshr_nu16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshr_nu16 (void)
|
||||
{
|
||||
uint16x4_t out_uint16x4_t;
|
||||
uint16x4_t arg0_uint16x4_t;
|
||||
|
||||
out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshr_nu32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshr_nu32 (void)
|
||||
{
|
||||
uint32x2_t out_uint32x2_t;
|
||||
uint32x2_t arg0_uint32x2_t;
|
||||
|
||||
out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshr_nu64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshr_nu64 (void)
|
||||
{
|
||||
uint64x1_t out_uint64x1_t;
|
||||
uint64x1_t arg0_uint64x1_t;
|
||||
|
||||
out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshr_nu8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshr_nu8 (void)
|
||||
{
|
||||
uint8x8_t out_uint8x8_t;
|
||||
uint8x8_t arg0_uint8x8_t;
|
||||
|
||||
out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshr\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshrn_ns16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshrn_ns16 (void)
|
||||
{
|
||||
int8x8_t out_int8x8_t;
|
||||
int16x8_t arg0_int16x8_t;
|
||||
|
||||
out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshrn_ns32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshrn_ns32 (void)
|
||||
{
|
||||
int16x4_t out_int16x4_t;
|
||||
int32x4_t arg0_int32x4_t;
|
||||
|
||||
out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshrn_ns64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshrn_ns64 (void)
|
||||
{
|
||||
int32x2_t out_int32x2_t;
|
||||
int64x2_t arg0_int64x2_t;
|
||||
|
||||
out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshrn_nu16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshrn_nu16 (void)
|
||||
{
|
||||
uint8x8_t out_uint8x8_t;
|
||||
uint16x8_t arg0_uint16x8_t;
|
||||
|
||||
out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshrn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshrn_nu32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshrn_nu32 (void)
|
||||
{
|
||||
uint16x4_t out_uint16x4_t;
|
||||
uint32x4_t arg0_uint32x4_t;
|
||||
|
||||
out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshrn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* Test the `vRshrn_nu64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRshrn_nu64 (void)
|
||||
{
|
||||
uint32x2_t out_uint32x2_t;
|
||||
uint64x2_t arg0_uint64x2_t;
|
||||
|
||||
out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrshrn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsraQ_ns16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsraQ_ns16 (void)
|
||||
{
|
||||
int16x8_t out_int16x8_t;
|
||||
int16x8_t arg0_int16x8_t;
|
||||
int16x8_t arg1_int16x8_t;
|
||||
|
||||
out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsraQ_ns32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsraQ_ns32 (void)
|
||||
{
|
||||
int32x4_t out_int32x4_t;
|
||||
int32x4_t arg0_int32x4_t;
|
||||
int32x4_t arg1_int32x4_t;
|
||||
|
||||
out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsraQ_ns64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsraQ_ns64 (void)
|
||||
{
|
||||
int64x2_t out_int64x2_t;
|
||||
int64x2_t arg0_int64x2_t;
|
||||
int64x2_t arg1_int64x2_t;
|
||||
|
||||
out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsraQ_ns8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsraQ_ns8 (void)
|
||||
{
|
||||
int8x16_t out_int8x16_t;
|
||||
int8x16_t arg0_int8x16_t;
|
||||
int8x16_t arg1_int8x16_t;
|
||||
|
||||
out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsraQ_nu16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsraQ_nu16 (void)
|
||||
{
|
||||
uint16x8_t out_uint16x8_t;
|
||||
uint16x8_t arg0_uint16x8_t;
|
||||
uint16x8_t arg1_uint16x8_t;
|
||||
|
||||
out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsraQ_nu32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsraQ_nu32 (void)
|
||||
{
|
||||
uint32x4_t out_uint32x4_t;
|
||||
uint32x4_t arg0_uint32x4_t;
|
||||
uint32x4_t arg1_uint32x4_t;
|
||||
|
||||
out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsraQ_nu64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsraQ_nu64 (void)
|
||||
{
|
||||
uint64x2_t out_uint64x2_t;
|
||||
uint64x2_t arg0_uint64x2_t;
|
||||
uint64x2_t arg1_uint64x2_t;
|
||||
|
||||
out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsraQ_nu8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsraQ_nu8 (void)
|
||||
{
|
||||
uint8x16_t out_uint8x16_t;
|
||||
uint8x16_t arg0_uint8x16_t;
|
||||
uint8x16_t arg1_uint8x16_t;
|
||||
|
||||
out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsra_ns16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsra_ns16 (void)
|
||||
{
|
||||
int16x4_t out_int16x4_t;
|
||||
int16x4_t arg0_int16x4_t;
|
||||
int16x4_t arg1_int16x4_t;
|
||||
|
||||
out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsra_ns32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsra_ns32 (void)
|
||||
{
|
||||
int32x2_t out_int32x2_t;
|
||||
int32x2_t arg0_int32x2_t;
|
||||
int32x2_t arg1_int32x2_t;
|
||||
|
||||
out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsra_ns64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsra_ns64 (void)
|
||||
{
|
||||
int64x1_t out_int64x1_t;
|
||||
int64x1_t arg0_int64x1_t;
|
||||
int64x1_t arg1_int64x1_t;
|
||||
|
||||
out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.s64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsra_ns8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsra_ns8 (void)
|
||||
{
|
||||
int8x8_t out_int8x8_t;
|
||||
int8x8_t arg0_int8x8_t;
|
||||
int8x8_t arg1_int8x8_t;
|
||||
|
||||
out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsra_nu16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsra_nu16 (void)
|
||||
{
|
||||
uint16x4_t out_uint16x4_t;
|
||||
uint16x4_t arg0_uint16x4_t;
|
||||
uint16x4_t arg1_uint16x4_t;
|
||||
|
||||
out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsra_nu32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsra_nu32 (void)
|
||||
{
|
||||
uint32x2_t out_uint32x2_t;
|
||||
uint32x2_t arg0_uint32x2_t;
|
||||
uint32x2_t arg1_uint32x2_t;
|
||||
|
||||
out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsra_nu64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsra_nu64 (void)
|
||||
{
|
||||
uint64x1_t out_uint64x1_t;
|
||||
uint64x1_t arg0_uint64x1_t;
|
||||
uint64x1_t arg1_uint64x1_t;
|
||||
|
||||
out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.u64\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsra_nu8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsra_nu8 (void)
|
||||
{
|
||||
uint8x8_t out_uint8x8_t;
|
||||
uint8x8_t arg0_uint8x8_t;
|
||||
uint8x8_t arg1_uint8x8_t;
|
||||
|
||||
out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsra\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsubhns16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsubhns16 (void)
|
||||
{
|
||||
int8x8_t out_int8x8_t;
|
||||
int16x8_t arg0_int16x8_t;
|
||||
int16x8_t arg1_int16x8_t;
|
||||
|
||||
out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsubhns32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsubhns32 (void)
|
||||
{
|
||||
int16x4_t out_int16x4_t;
|
||||
int32x4_t arg0_int32x4_t;
|
||||
int32x4_t arg1_int32x4_t;
|
||||
|
||||
out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsubhns64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsubhns64 (void)
|
||||
{
|
||||
int32x2_t out_int32x2_t;
|
||||
int64x2_t arg0_int64x2_t;
|
||||
int64x2_t arg1_int64x2_t;
|
||||
|
||||
out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsubhnu16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsubhnu16 (void)
|
||||
{
|
||||
uint8x8_t out_uint8x8_t;
|
||||
uint16x8_t arg0_uint16x8_t;
|
||||
uint16x8_t arg1_uint16x8_t;
|
||||
|
||||
out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsubhn\.i16\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsubhnu32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsubhnu32 (void)
|
||||
{
|
||||
uint16x4_t out_uint16x4_t;
|
||||
uint32x4_t arg0_uint32x4_t;
|
||||
uint32x4_t arg1_uint32x4_t;
|
||||
|
||||
out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsubhn\.i32\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vRsubhnu64' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vRsubhnu64 (void)
|
||||
{
|
||||
uint32x2_t out_uint32x2_t;
|
||||
uint64x2_t arg0_uint64x2_t;
|
||||
uint64x2_t arg1_uint64x2_t;
|
||||
|
||||
out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vrsubhn\.i64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabaQs16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabaQs16 (void)
|
||||
{
|
||||
int16x8_t out_int16x8_t;
|
||||
int16x8_t arg0_int16x8_t;
|
||||
int16x8_t arg1_int16x8_t;
|
||||
int16x8_t arg2_int16x8_t;
|
||||
|
||||
out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabaQs32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabaQs32 (void)
|
||||
{
|
||||
int32x4_t out_int32x4_t;
|
||||
int32x4_t arg0_int32x4_t;
|
||||
int32x4_t arg1_int32x4_t;
|
||||
int32x4_t arg2_int32x4_t;
|
||||
|
||||
out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabaQs8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabaQs8 (void)
|
||||
{
|
||||
int8x16_t out_int8x16_t;
|
||||
int8x16_t arg0_int8x16_t;
|
||||
int8x16_t arg1_int8x16_t;
|
||||
int8x16_t arg2_int8x16_t;
|
||||
|
||||
out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabaQu16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabaQu16 (void)
|
||||
{
|
||||
uint16x8_t out_uint16x8_t;
|
||||
uint16x8_t arg0_uint16x8_t;
|
||||
uint16x8_t arg1_uint16x8_t;
|
||||
uint16x8_t arg2_uint16x8_t;
|
||||
|
||||
out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabaQu32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabaQu32 (void)
|
||||
{
|
||||
uint32x4_t out_uint32x4_t;
|
||||
uint32x4_t arg0_uint32x4_t;
|
||||
uint32x4_t arg1_uint32x4_t;
|
||||
uint32x4_t arg2_uint32x4_t;
|
||||
|
||||
out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabaQu8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabaQu8 (void)
|
||||
{
|
||||
uint8x16_t out_uint8x16_t;
|
||||
uint8x16_t arg0_uint8x16_t;
|
||||
uint8x16_t arg1_uint8x16_t;
|
||||
uint8x16_t arg2_uint8x16_t;
|
||||
|
||||
out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabals16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabals16 (void)
|
||||
{
|
||||
int32x4_t out_int32x4_t;
|
||||
int32x4_t arg0_int32x4_t;
|
||||
int16x4_t arg1_int16x4_t;
|
||||
int16x4_t arg2_int16x4_t;
|
||||
|
||||
out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vabal\.s16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabals32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabals32 (void)
|
||||
{
|
||||
int64x2_t out_int64x2_t;
|
||||
int64x2_t arg0_int64x2_t;
|
||||
int32x2_t arg1_int32x2_t;
|
||||
int32x2_t arg2_int32x2_t;
|
||||
|
||||
out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vabal\.s32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabals8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabals8 (void)
|
||||
{
|
||||
int16x8_t out_int16x8_t;
|
||||
int16x8_t arg0_int16x8_t;
|
||||
int8x8_t arg1_int8x8_t;
|
||||
int8x8_t arg2_int8x8_t;
|
||||
|
||||
out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vabal\.s8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabalu16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabalu16 (void)
|
||||
{
|
||||
uint32x4_t out_uint32x4_t;
|
||||
uint32x4_t arg0_uint32x4_t;
|
||||
uint16x4_t arg1_uint16x4_t;
|
||||
uint16x4_t arg2_uint16x4_t;
|
||||
|
||||
out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vabal\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabalu32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabalu32 (void)
|
||||
{
|
||||
uint64x2_t out_uint64x2_t;
|
||||
uint64x2_t arg0_uint64x2_t;
|
||||
uint32x2_t arg1_uint32x2_t;
|
||||
uint32x2_t arg2_uint32x2_t;
|
||||
|
||||
out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vabal\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabalu8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabalu8 (void)
|
||||
{
|
||||
uint16x8_t out_uint16x8_t;
|
||||
uint16x8_t arg0_uint16x8_t;
|
||||
uint8x8_t arg1_uint8x8_t;
|
||||
uint8x8_t arg2_uint8x8_t;
|
||||
|
||||
out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vabal\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabas16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabas16 (void)
|
||||
{
|
||||
int16x4_t out_int16x4_t;
|
||||
int16x4_t arg0_int16x4_t;
|
||||
int16x4_t arg1_int16x4_t;
|
||||
int16x4_t arg2_int16x4_t;
|
||||
|
||||
out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vaba\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabas32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabas32 (void)
|
||||
{
|
||||
int32x2_t out_int32x2_t;
|
||||
int32x2_t arg0_int32x2_t;
|
||||
int32x2_t arg1_int32x2_t;
|
||||
int32x2_t arg2_int32x2_t;
|
||||
|
||||
out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vaba\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabas8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabas8 (void)
|
||||
{
|
||||
int8x8_t out_int8x8_t;
|
||||
int8x8_t arg0_int8x8_t;
|
||||
int8x8_t arg1_int8x8_t;
|
||||
int8x8_t arg2_int8x8_t;
|
||||
|
||||
out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vaba\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabau16' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabau16 (void)
|
||||
{
|
||||
uint16x4_t out_uint16x4_t;
|
||||
uint16x4_t arg0_uint16x4_t;
|
||||
uint16x4_t arg1_uint16x4_t;
|
||||
uint16x4_t arg2_uint16x4_t;
|
||||
|
||||
out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vaba\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabau32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabau32 (void)
|
||||
{
|
||||
uint32x2_t out_uint32x2_t;
|
||||
uint32x2_t arg0_uint32x2_t;
|
||||
uint32x2_t arg1_uint32x2_t;
|
||||
uint32x2_t arg2_uint32x2_t;
|
||||
|
||||
out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vaba\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* Test the `vabau8' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabau8 (void)
|
||||
{
|
||||
uint8x8_t out_uint8x8_t;
|
||||
uint8x8_t arg0_uint8x8_t;
|
||||
uint8x8_t arg1_uint8x8_t;
|
||||
uint8x8_t arg2_uint8x8_t;
|
||||
|
||||
out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vaba\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* Test the `vabdQf32' ARM Neon intrinsic. */
|
||||
/* This file was autogenerated by neon-testgen. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_neon_ok } */
|
||||
/* { dg-options "-save-temps -O0" } */
|
||||
/* { dg-add-options arm_neon } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
void test_vabdQf32 (void)
|
||||
{
|
||||
float32x4_t out_float32x4_t;
|
||||
float32x4_t arg0_float32x4_t;
|
||||
float32x4_t arg1_float32x4_t;
|
||||
|
||||
out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vabd\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue