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re PR bootstrap/45177 (cc1 runs out of memory building libgcc in ARM cross-compiler) 

PR bootstrap/45177
	* config/arm/arm.c (multiple_operation_profitable_p): Move xscale
	test here from arm_gen_load_multiple_1.
	(arm_gen_load_multiple_1, arm_gen_store_multiple_1): Use
	multiple_operation_profitable_p.

From-SVN: r163077
This commit is contained in:
Bernd Schmidt 2010-08-10 18:45:10 +00:00 committed by Bernd Schmidt
parent c1510a4900
commit 8f4c6e28cf
2 changed files with 40 additions and 32 deletions
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gcc/ChangeLog
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@ -1,3 +1,11 @@
2010-08-10 Bernd Schmidt <bernds@codesourcery.com>
PR bootstrap/45177
* config/arm/arm.c (multiple_operation_profitable_p): Move xscale
test here from arm_gen_load_multiple_1.
(arm_gen_load_multiple_1, arm_gen_store_multiple_1): Use
multiple_operation_profitable_p.
2010-08-10 Nathan Froyd <froydnj@codesourcery.com>
* tree-ssa-prec. (init_pre): Call alloc_aux_for_blocks.

64
gcc/config/arm/arm.c
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@ -9289,6 +9289,36 @@ multiple_operation_profitable_p (bool is_store ATTRIBUTE_UNUSED,
if (nops == 2 && arm_ld_sched && add_offset != 0)
return false;
/* XScale has load-store double instructions, but they have stricter
alignment requirements than load-store multiple, so we cannot
use them.
For XScale ldm requires 2 + NREGS cycles to complete and blocks
the pipeline until completion.
NREGS CYCLES
1 3
2 4
3 5
4 6
An ldr instruction takes 1-3 cycles, but does not block the
pipeline.
NREGS CYCLES
1 1-3
2 2-6
3 3-9
4 4-12
Best case ldr will always win. However, the more ldr instructions
we issue, the less likely we are to be able to schedule them well.
Using ldr instructions also increases code size.
As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
for counts of 3 or 4 regs. */
if (nops <= 2 && arm_tune_xscale && !optimize_size)
return false;
return true;
}
@ -9641,35 +9671,7 @@ arm_gen_load_multiple_1 (int count, int *regs, rtx *mems, rtx basereg,
int i = 0, j;
rtx result;
/* XScale has load-store double instructions, but they have stricter
alignment requirements than load-store multiple, so we cannot
use them.
For XScale ldm requires 2 + NREGS cycles to complete and blocks
the pipeline until completion.
NREGS CYCLES
1 3
2 4
3 5
4 6
An ldr instruction takes 1-3 cycles, but does not block the
pipeline.
NREGS CYCLES
1 1-3
2 2-6
3 3-9
4 4-12
Best case ldr will always win. However, the more ldr instructions
we issue, the less likely we are to be able to schedule them well.
Using ldr instructions also increases code size.
As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
for counts of 3 or 4 regs. */
if (arm_tune_xscale && count <= 2 && ! optimize_size)
if (!multiple_operation_profitable_p (false, count, 0))
{
rtx seq;
@ -9721,9 +9723,7 @@ arm_gen_store_multiple_1 (int count, int *regs, rtx *mems, rtx basereg,
if (GET_CODE (basereg) == PLUS)
basereg = XEXP (basereg, 0);
/* See arm_gen_load_multiple_1 for discussion of
the pros/cons of ldm/stm usage for XScale. */
if (arm_tune_xscale && count <= 2 && ! optimize_size)
if (!multiple_operation_profitable_p (false, count, 0))
{
rtx seq;