constraints.md (Ya): New internal constraint.
* config/i386/constraints.md (Ya): New internal constraint. * config/i386/i386.md (zero_extendsidi2): Remove expansion. (*zero_extendsidi2_rex64): Add x,x alternative. (*zero_extendsidi2): Ditto. Add o,0 alternative. Remove flags reg clobber. Adjust corresponding splits. (zero_extend<mode>si2): Macroize expander from zero_extendhisi2 and zero_extendqisi2 expanders using SWI12 mode iterator. (zero_extend<mode>si2_and): Macroize insn from zero_extendhisi2_and and zero_extendqisi2_and. Merge corresponding splitters. (*zero_extend<mode>si2): Macroize insn from *zero_extendhisi2_movzbl and *zero_extendqisi2_movzbl. (*zero_extend*2_movzbl_and): Remove insn patterns. (zero_extendqihi2_and): Merge corresponding splitter. (*zero_extendqihi2): Rename from *zero_extendqihi2_movzbl. (*zero_extend*2_movzbl_and): Remove insn patterns. (*anddi_1): Split TYPE_IMOVX instructions. (*andsi_1): Use Ya for alternative 2. Split TYPE_IMOVX instructions. (*andhi_1): Ditto. (and->zext splitter): Add splitter pattern. (zero extend with andsi3 splitter): Adjust zero_extend pattern. From-SVN: r184891
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
d4ce363568
commit
904eea2c55
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@ -1,3 +1,27 @@
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2012-03-04 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/constraints.md (Ya): New internal constraint.
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* config/i386/i386.md (zero_extendsidi2): Remove expansion.
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(*zero_extendsidi2_rex64): Add x,x alternative.
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(*zero_extendsidi2): Ditto. Add o,0 alternative.
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Remove flags reg clobber. Adjust corresponding splits.
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(zero_extend<mode>si2): Macroize expander from zero_extendhisi2 and
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zero_extendqisi2 expanders using SWI12 mode iterator.
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(zero_extend<mode>si2_and): Macroize insn from
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zero_extendhisi2_and and zero_extendqisi2_and. Merge corresponding
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splitters.
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(*zero_extend<mode>si2): Macroize insn from
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*zero_extendhisi2_movzbl and *zero_extendqisi2_movzbl.
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(*zero_extend*2_movzbl_and): Remove insn patterns.
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(zero_extendqihi2_and): Merge corresponding splitter.
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(*zero_extendqihi2): Rename from *zero_extendqihi2_movzbl.
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(*zero_extend*2_movzbl_and): Remove insn patterns.
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(*anddi_1): Split TYPE_IMOVX instructions.
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(*andsi_1): Use Ya for alternative 2. Split TYPE_IMOVX instructions.
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(*andhi_1): Ditto.
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(and->zext splitter): Add splitter pattern.
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(zero extend with andsi3 splitter): Adjust zero_extend pattern.
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2012-03-04 Sandra Loosemore <sandra@codesourcery.com>
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* doc/invoke.texi (C++ Dialect Options): Minor copy-edits to
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@ -89,6 +89,7 @@
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;; z First SSE register.
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;; i SSE2 inter-unit moves enabled
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;; m MMX inter-unit moves enabled
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;; a Integer register when zero extensions with AND are disabled
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;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled
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;; d Integer register when integer DFmode moves are enabled
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;; x Integer register when integer XFmode moves are enabled
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@ -108,6 +109,11 @@
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"TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
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"@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.")
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(define_register_constraint "Ya"
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"TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)
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? NO_REGS : GENERAL_REGS"
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"@internal Any integer register when zero extensions with AND are disabled.")
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(define_register_constraint "Yd"
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"(TARGET_64BIT
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|| (TARGET_INTEGER_DFMODE_MOVES && optimize_function_for_speed_p (cfun)))
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@ -3371,20 +3371,14 @@
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(define_expand "zero_extendsidi2"
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[(set (match_operand:DI 0 "nonimmediate_operand" "")
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
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""
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{
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if (!TARGET_64BIT)
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{
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emit_insn (gen_zero_extendsidi2_1 (operands[0], operands[1]));
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DONE;
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}
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})
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))])
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(define_insn "*zero_extendsidi2_rex64"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*x")
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=r,o,?*Ym,?*y,?*Yi,!*x")
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(zero_extend:DI
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(match_operand:SI 1 "nonimmediate_operand" "rm,0,r ,m ,r ,m")))]
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(match_operand:SI 1 "nonimmediate_operand"
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"rm,0,r ,m ,r ,m*x")))]
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"TARGET_64BIT"
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"@
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mov{l}\t{%1, %k0|%k0, %1}
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@ -3393,24 +3387,17 @@
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movd\t{%1, %0|%0, %1}
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%vmovd\t{%1, %0|%0, %1}
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%vmovd\t{%1, %0|%0, %1}"
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[(set_attr "type" "imovx,imov,mmxmov,mmxmov,ssemov,ssemov")
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[(set_attr "isa" "*,*,*,*,*,sse2")
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(set_attr "type" "imovx,multi,mmxmov,mmxmov,ssemov,ssemov")
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(set_attr "prefix" "orig,*,orig,orig,maybe_vex,maybe_vex")
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(set_attr "prefix_0f" "0,*,*,*,*,*")
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(set_attr "mode" "SI,DI,DI,DI,TI,TI")])
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(set_attr "mode" "SI,SI,DI,DI,TI,TI")])
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(define_split
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[(set (match_operand:DI 0 "memory_operand" "")
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(zero_extend:DI (match_dup 0)))]
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"TARGET_64BIT"
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[(set (match_dup 4) (const_int 0))]
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"split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
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;; %%% Kill me once multi-word ops are sane.
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(define_insn "zero_extendsidi2_1"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*x")
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(zero_extend:DI
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(match_operand:SI 1 "nonimmediate_operand" "0,rm,r ,r ,m ,r ,m")))
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(clobber (reg:CC FLAGS_REG))]
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(define_insn "*zero_extendsidi2"
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=ro,?r,?o,?*Ym,?*y,?*Yi,!*x")
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
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"0 ,rm,r ,r ,m ,r ,m*x")))]
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"!TARGET_64BIT"
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"@
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#
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@ -3425,20 +3412,27 @@
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(set_attr "prefix" "*,*,*,orig,orig,maybe_vex,maybe_vex")
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(set_attr "mode" "SI,SI,SI,DI,DI,TI,TI")])
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(define_split
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[(set (match_operand:DI 0 "memory_operand" "")
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(zero_extend:DI (match_operand:SI 1 "memory_operand" "")))]
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"reload_completed"
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[(set (match_dup 4) (const_int 0))]
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"split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
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(define_split
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[(set (match_operand:DI 0 "register_operand" "")
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(zero_extend:DI (match_operand:SI 1 "register_operand" "")))
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(clobber (reg:CC FLAGS_REG))]
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(zero_extend:DI (match_operand:SI 1 "register_operand" "")))]
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"!TARGET_64BIT && reload_completed
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&& !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))
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&& true_regnum (operands[0]) == true_regnum (operands[1])"
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[(set (match_dup 4) (const_int 0))]
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"split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
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(define_split
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[(set (match_operand:DI 0 "nonimmediate_operand" "")
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(zero_extend:DI (match_operand:SI 1 "general_operand" "")))
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(clobber (reg:CC FLAGS_REG))]
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
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"!TARGET_64BIT && reload_completed
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))
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&& !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))"
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[(set (match_dup 3) (match_dup 1))
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(set (match_dup 4) (const_int 0))]
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@ -3453,112 +3447,100 @@
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[(set_attr "type" "imovx")
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(set_attr "mode" "SI")])
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(define_expand "zero_extendhisi2"
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(define_expand "zero_extend<mode>si2"
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[(set (match_operand:SI 0 "register_operand" "")
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(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
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(zero_extend:SI (match_operand:SWI12 1 "nonimmediate_operand" "")))]
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""
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{
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if (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
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{
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operands[1] = force_reg (HImode, operands[1]);
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emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
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operands[1] = force_reg (<MODE>mode, operands[1]);
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emit_insn (gen_zero_extend<mode>si2_and (operands[0], operands[1]));
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DONE;
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}
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})
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(define_insn_and_split "zero_extendhisi2_and"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
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(define_insn_and_split "zero_extend<mode>si2_and"
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[(set (match_operand:SI 0 "register_operand" "=r,?&<r>")
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(zero_extend:SI
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(match_operand:SWI12 1 "nonimmediate_operand" "0,<r>m")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
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"#"
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"&& reload_completed"
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[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
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[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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""
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{
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if (true_regnum (operands[0]) != true_regnum (operands[1]))
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{
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ix86_expand_clear (operands[0]);
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gcc_assert (!TARGET_PARTIAL_REG_STALL);
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emit_insn (gen_movstrict<mode>
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(gen_lowpart (<MODE>mode, operands[0]), operands[1]));
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DONE;
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}
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operands[2] = GEN_INT (GET_MODE_MASK (<MODE>mode));
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}
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[(set_attr "type" "alu1")
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(set_attr "mode" "SI")])
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(define_insn "*zero_extendhisi2_movzwl"
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(define_insn "*zero_extend<mode>si2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
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"!TARGET_ZERO_EXTEND_WITH_AND
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|| optimize_function_for_size_p (cfun)"
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"movz{wl|x}\t{%1, %0|%0, %1}"
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(zero_extend:SI
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(match_operand:SWI12 1 "nonimmediate_operand" "<r>m")))]
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"!(TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))"
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"movz{<imodesuffix>l|x}\t{%1, %0|%0, %1}"
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[(set_attr "type" "imovx")
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(set_attr "mode" "SI")])
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(define_expand "zero_extendqi<mode>2"
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[(parallel
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[(set (match_operand:SWI24 0 "register_operand" "")
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(zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "")))
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(clobber (reg:CC FLAGS_REG))])])
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(define_expand "zero_extendqihi2"
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[(set (match_operand:HI 0 "register_operand" "")
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
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""
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{
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if (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
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{
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operands[1] = force_reg (QImode, operands[1]);
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emit_insn (gen_zero_extendqihi2_and (operands[0], operands[1]));
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DONE;
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}
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})
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(define_insn "*zero_extendqi<mode>2_and"
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[(set (match_operand:SWI24 0 "register_operand" "=r,?&q")
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(zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
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(define_insn_and_split "zero_extendqihi2_and"
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[(set (match_operand:HI 0 "register_operand" "=r,?&q")
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
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"#"
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[(set_attr "type" "alu1")
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(set_attr "mode" "<MODE>")])
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;; When source and destination does not overlap, clear destination
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;; first and then do the movb
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(define_split
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[(set (match_operand:SWI24 0 "register_operand" "")
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(zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "")))
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(clobber (reg:CC FLAGS_REG))]
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"reload_completed
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&& (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
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&& ANY_QI_REG_P (operands[0])
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&& (ANY_QI_REG_P (operands[1]) || MEM_P (operands[1]))
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&& !reg_overlap_mentioned_p (operands[0], operands[1])"
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[(set (strict_low_part (match_dup 2)) (match_dup 1))]
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"&& reload_completed"
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[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[2] = gen_lowpart (QImode, operands[0]);
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ix86_expand_clear (operands[0]);
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})
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if (true_regnum (operands[0]) != true_regnum (operands[1]))
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{
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ix86_expand_clear (operands[0]);
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(define_insn "*zero_extendqi<mode>2_movzbl_and"
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[(set (match_operand:SWI24 0 "register_operand" "=r,r")
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(zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun)"
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"#"
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[(set_attr "type" "imovx,alu1")
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(set_attr "mode" "<MODE>")])
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gcc_assert (!TARGET_PARTIAL_REG_STALL);
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emit_insn (gen_movstrictqi
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(gen_lowpart (QImode, operands[0]), operands[1]));
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DONE;
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}
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;; For the movzbl case strip only the clobber
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(define_split
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[(set (match_operand:SWI24 0 "register_operand" "")
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(zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "")))
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(clobber (reg:CC FLAGS_REG))]
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"reload_completed
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&& (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))
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&& (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
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[(set (match_dup 0)
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(zero_extend:SWI24 (match_dup 1)))])
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operands[0] = gen_lowpart (SImode, operands[0]);
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}
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[(set_attr "type" "alu1")
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(set_attr "mode" "SI")])
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; zero extend to SImode to avoid partial register stalls
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(define_insn "*zero_extendqi<mode>2_movzbl"
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[(set (match_operand:SWI24 0 "register_operand" "=r")
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(zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "qm")))]
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"reload_completed
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&& (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))"
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(define_insn "*zero_extendqihi2"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
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"!(TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))"
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"movz{bl|x}\t{%1, %k0|%k0, %1}"
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[(set_attr "type" "imovx")
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(set_attr "mode" "SI")])
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;; Rest is handled by single and.
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(define_split
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[(set (match_operand:SWI24 0 "register_operand" "")
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(zero_extend:SWI24 (match_operand:QI 1 "register_operand" "")))
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(clobber (reg:CC FLAGS_REG))]
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"reload_completed
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&& true_regnum (operands[0]) == true_regnum (operands[1])"
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[(parallel [(set (match_dup 0) (and:SWI24 (match_dup 0) (const_int 255)))
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(clobber (reg:CC FLAGS_REG))])])
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;; Sign extension instructions
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@ -7674,28 +7656,7 @@
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switch (get_attr_type (insn))
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{
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case TYPE_IMOVX:
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{
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enum machine_mode mode;
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gcc_assert (CONST_INT_P (operands[2]));
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if (INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffffffff)
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mode = SImode;
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else if (INTVAL (operands[2]) == 0xffff)
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mode = HImode;
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else
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{
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gcc_assert (INTVAL (operands[2]) == 0xff);
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mode = QImode;
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}
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operands[1] = gen_lowpart (mode, operands[1]);
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if (mode == SImode)
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return "mov{l}\t{%1, %k0|%k0, %1}";
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else if (mode == HImode)
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return "movz{wl|x}\t{%1, %k0|%k0, %1}";
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else
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return "movz{bl|x}\t{%1, %k0|%k0, %1}";
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}
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return "#";
|
||||
|
||||
default:
|
||||
gcc_assert (rtx_equal_p (operands[0], operands[1]));
|
||||
|
|
@ -7717,7 +7678,7 @@
|
|||
(set_attr "mode" "SI,DI,DI,SI")])
|
||||
|
||||
(define_insn "*andsi_1"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,Ya")
|
||||
(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
|
||||
(match_operand:SI 2 "x86_64_general_operand" "re,rm,L")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
|
|
@ -7726,24 +7687,7 @@
|
|||
switch (get_attr_type (insn))
|
||||
{
|
||||
case TYPE_IMOVX:
|
||||
{
|
||||
enum machine_mode mode;
|
||||
|
||||
gcc_assert (CONST_INT_P (operands[2]));
|
||||
if (INTVAL (operands[2]) == 0xffff)
|
||||
mode = HImode;
|
||||
else
|
||||
{
|
||||
gcc_assert (INTVAL (operands[2]) == 0xff);
|
||||
mode = QImode;
|
||||
}
|
||||
|
||||
operands[1] = gen_lowpart (mode, operands[1]);
|
||||
if (mode == HImode)
|
||||
return "movz{wl|x}\t{%1, %0|%0, %1}";
|
||||
else
|
||||
return "movz{bl|x}\t{%1, %0|%0, %1}";
|
||||
}
|
||||
return "#";
|
||||
|
||||
default:
|
||||
gcc_assert (rtx_equal_p (operands[0], operands[1]));
|
||||
|
|
@ -7774,7 +7718,7 @@
|
|||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "*andhi_1"
|
||||
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
|
||||
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,Ya")
|
||||
(and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
|
||||
(match_operand:HI 2 "general_operand" "rn,rm,L")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
|
|
@ -7783,13 +7727,10 @@
|
|||
switch (get_attr_type (insn))
|
||||
{
|
||||
case TYPE_IMOVX:
|
||||
gcc_assert (CONST_INT_P (operands[2]));
|
||||
gcc_assert (INTVAL (operands[2]) == 0xff);
|
||||
return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
|
||||
return "#";
|
||||
|
||||
default:
|
||||
gcc_assert (rtx_equal_p (operands[0], operands[1]));
|
||||
|
||||
return "and{w}\t{%2, %0|%0, %2}";
|
||||
}
|
||||
}
|
||||
|
|
@ -7828,6 +7769,44 @@
|
|||
[(set_attr "type" "alu1")
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:SWI248 0 "register_operand" "")
|
||||
(and:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "")
|
||||
(match_operand:SWI248 2 "const_int_operand" "")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"reload_completed
|
||||
&& true_regnum (operands[0]) != true_regnum (operands[1])"
|
||||
[(const_int 0)]
|
||||
{
|
||||
enum machine_mode mode;
|
||||
|
||||
if (INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffffffff)
|
||||
mode = SImode;
|
||||
else if (INTVAL (operands[2]) == 0xffff)
|
||||
mode = HImode;
|
||||
else
|
||||
{
|
||||
gcc_assert (INTVAL (operands[2]) == 0xff);
|
||||
mode = QImode;
|
||||
}
|
||||
|
||||
operands[1] = gen_lowpart (mode, operands[1]);
|
||||
|
||||
if (mode == SImode)
|
||||
emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
|
||||
else
|
||||
{
|
||||
rtx (*insn) (rtx, rtx);
|
||||
|
||||
/* Zero extend to SImode to avoid partial register stalls. */
|
||||
operands[0] = gen_lowpart (SImode, operands[0]);
|
||||
|
||||
insn = (mode == HImode) ? gen_zero_extendhisi2 : gen_zero_extendqisi2;
|
||||
emit_insn (insn (operands[0], operands[1]));
|
||||
}
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_split
|
||||
[(set (match_operand 0 "register_operand" "")
|
||||
(and (match_dup 0)
|
||||
|
|
@ -11175,18 +11154,17 @@
|
|||
ix86_expand_clear (operands[3]);
|
||||
})
|
||||
|
||||
;; Similar, but match zero_extendhisi2_and, which adds a clobber.
|
||||
;; Similar, but match zero extend with andsi3.
|
||||
|
||||
(define_peephole2
|
||||
[(set (reg FLAGS_REG) (match_operand 0 "" ""))
|
||||
(set (match_operand:QI 1 "register_operand" "")
|
||||
(match_operator:QI 2 "ix86_comparison_operator"
|
||||
[(reg FLAGS_REG) (const_int 0)]))
|
||||
(parallel [(set (match_operand 3 "q_regs_operand" "")
|
||||
(zero_extend (match_dup 1)))
|
||||
(parallel [(set (match_operand:SI 3 "q_regs_operand" "")
|
||||
(and:SI (match_dup 3) (const_int 255)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"(peep2_reg_dead_p (3, operands[1])
|
||||
|| operands_match_p (operands[1], operands[3]))
|
||||
"REGNO (operands[1]) == REGNO (operands[3])
|
||||
&& ! reg_overlap_mentioned_p (operands[3], operands[0])"
|
||||
[(set (match_dup 4) (match_dup 0))
|
||||
(set (strict_low_part (match_dup 5))
|
||||
|
|
|
|||
Loading…
Reference in New Issue