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Fix misoptimization of mask and shift. 

PR target/21684
* config/mcore/mcore.h (SHIFT_COUNT_TRUNCATED): Define to 0.

Co-Authored-By: Kevin Winchester <winchester@amirix.com>

From-SVN: r103228
This commit is contained in:
James E Wilson 2005-08-17 14:43:49 -07:00 committed by Jim Wilson
parent 97b51fd08e
commit 90e0c734fa
2 changed files with 10 additions and 6 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2005-08-17 James E Wilson <wilson@specifix.com>
Kevin Winchester <winchester@amirix.com>
PR target/21684
* config/mcore/mcore.h (SHIFT_COUNT_TRUNCATED): Define to 0.
2005-08-17 Uros Bizjak <uros@kss-loka.si>
PR target/23268

10
gcc/config/mcore/mcore.h
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@ -820,12 +820,10 @@ extern const enum reg_class reg_class_from_letter[];
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES
/* Immediate shift counts are truncated by the output routines (or was it
the assembler?). Shift counts in a register are truncated by ARM. Note
that the native compiler puts too large (> 32) immediate shift counts
into a register and shifts by the register, letting the ARM decide what
to do instead of doing that itself. */
#define SHIFT_COUNT_TRUNCATED 1
/* Shift counts are truncated to 6-bits (0 to 63) instead of the expected
5-bits, so we can not define SHIFT_COUNT_TRUNCATED to true for this
target. */
#define SHIFT_COUNT_TRUNCATED 0
/* All integers have the same format so truncation is easy. */
#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1