Index: ChangeLog
2005-04-21 Geoffrey Keating <geoffk@apple.com> * config/rs6000/rs6000-protos.h (rs6000_emit_sync): New. * config/rs6000/rs6000.c (rs6000_emit_vector_compare): Use gen_rtx_* not gen_rtx_fmt_*. (rs6000_emit_vector_select): Likewise. (rs6000_emit_sync): New. * config/rs6000/rs6000.md (GPR, INT, INT1): New mode macros. (larx, stcx, cmp): New mode substitutions. (UNSPEC_SYNC, UNSPEC_SYNC_OP, UNSPEC_SYNC_SWAP, UNSPEC_LWSYNC, UNSPEC_ISYNC): New constants. (rlwinm): Give name. (memory_barrier, isync, lwsync): New insns. (sync_compare_and_swap<mode>, sync_lock_test_and_set<mode>): New insn. (sync_lock_release<mode>): New expander. (sync_add<mode>, sync_sub<mode>, sync_ior<mode>, sync_and<mode>, sync_xor<mode>, sync_nand<mode>, sync_old_add<mode>, sync_old_sub<mode>, sync_old_ior<mode>, sync_old_and<mode>, sync_old_xor<mode>, sync_old_nand<mode>, sync_new_add<mode>, sync_new_sub<mode>, sync_new_ior<mode>, sync_new_and<mode>, sync_new_xor<mode>, sync_new_nand<mode>): New expanders. (sync_add<mode>_internal, sync_addshort_internal, sync_sub<mode>_internal, sync_andsi_internal, sync_anddi_internal, sync_boolsi_internal, sync_booldi_internal, sync_boolc<mode>_internal, sync_boolc<mode>_internal2, sync_boolcc<mode>_internal): New insns. * doc/md.texi (Standard Names): sync_compare_and_swap's operand 0 is the memory before, not after, the operation. Clarify barrier requirements. Index: testsuite/ChangeLog 2005-04-21 Geoffrey Keating <geoffk@apple.com> * lib/target-supports.exp (check_effective_target_sync_int_long): Add powerpc*. From-SVN: r98527
This commit is contained in:
Geoffrey Keating
Geoffrey Keating
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commit
915167f5a5
@ -1,3 +1,33 @@
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2005-04-21 Geoffrey Keating <geoffk@apple.com>
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* config/rs6000/rs6000-protos.h (rs6000_emit_sync): New.
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* config/rs6000/rs6000.c (rs6000_emit_vector_compare): Use
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gen_rtx_* not gen_rtx_fmt_*.
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(rs6000_emit_vector_select): Likewise.
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(rs6000_emit_sync): New.
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* config/rs6000/rs6000.md (GPR, INT, INT1): New mode macros.
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(larx, stcx, cmp): New mode substitutions.
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(UNSPEC_SYNC, UNSPEC_SYNC_OP, UNSPEC_SYNC_SWAP, UNSPEC_LWSYNC,
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UNSPEC_ISYNC): New constants.
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(rlwinm): Give name.
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(memory_barrier, isync, lwsync): New insns.
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(sync_compare_and_swap<mode>, sync_lock_test_and_set<mode>): New insn.
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(sync_lock_release<mode>): New expander.
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(sync_add<mode>, sync_sub<mode>, sync_ior<mode>, sync_and<mode>,
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sync_xor<mode>, sync_nand<mode>, sync_old_add<mode>,
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sync_old_sub<mode>, sync_old_ior<mode>, sync_old_and<mode>,
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sync_old_xor<mode>, sync_old_nand<mode>, sync_new_add<mode>,
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sync_new_sub<mode>, sync_new_ior<mode>, sync_new_and<mode>,
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sync_new_xor<mode>, sync_new_nand<mode>): New expanders.
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(sync_add<mode>_internal, sync_addshort_internal,
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sync_sub<mode>_internal, sync_andsi_internal, sync_anddi_internal,
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sync_boolsi_internal, sync_booldi_internal, sync_boolc<mode>_internal,
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sync_boolc<mode>_internal2, sync_boolcc<mode>_internal): New insns.
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* doc/md.texi (Standard Names): sync_compare_and_swap's operand 0
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is the memory before, not after, the operation. Clarify
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barrier requirements.
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2005-04-21 Nathan Sidwell <nathan@codesourcery.com>
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* cfghooks.h (struct cfg_hooks): Reword comments to avoid 'abort'.
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@ -80,6 +80,8 @@ extern rtx rs6000_emit_set_const (rtx, enum machine_mode, rtx, int);
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extern int rs6000_emit_cmove (rtx, rtx, rtx, rtx);
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extern int rs6000_emit_vector_cond_expr (rtx, rtx, rtx, rtx, rtx, rtx);
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extern void rs6000_emit_minmax (rtx, enum rtx_code, rtx, rtx);
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extern void rs6000_emit_sync (enum rtx_code, enum machine_mode,
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rtx, rtx, rtx, rtx, bool);
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extern void output_toc (FILE *, rtx, int, enum machine_mode);
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extern void rs6000_initialize_trampoline (rtx, rtx, rtx);
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extern rtx rs6000_longcall_ref (rtx);
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@ -10620,12 +10620,10 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
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}
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}
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emit_insn (gen_rtx_fmt_ee (SET,
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VOIDmode,
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mask,
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gen_rtx_fmt_Ei (UNSPEC, dest_mode,
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gen_rtvec (2, op0, op1),
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vec_cmp_insn)));
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emit_insn (gen_rtx_SET (VOIDmode, mask,
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gen_rtx_UNSPEC (dest_mode,
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gen_rtvec (2, op0, op1),
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vec_cmp_insn)));
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if (dmode != dest_mode)
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{
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rtx temp = gen_reg_rtx (dest_mode);
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@ -10676,10 +10674,10 @@ rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
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/* For each vector element, select op1 when mask is 1 otherwise
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select op2. */
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t = gen_rtx_fmt_ee (SET, VOIDmode, temp,
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gen_rtx_fmt_Ei (UNSPEC, dest_mode,
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gen_rtvec (3, op2, op1, mask),
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vsel_insn_index));
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t = gen_rtx_SET (VOIDmode, temp,
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gen_rtx_UNSPEC (dest_mode,
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gen_rtvec (3, op2, op1, mask),
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vsel_insn_index));
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emit_insn (t);
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emit_move_insn (dest, temp);
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return;
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@ -10960,6 +10958,183 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
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emit_move_insn (dest, target);
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}
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/* Emit instructions to perform a load-reserved/store-conditional operation.
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The operation performed is an atomic
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(set M (CODE:MODE M OP))
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If not NULL, BEFORE is atomically set to M before the operation, and
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AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
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If SYNC_P then a memory barrier is emitted before the operation.
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Either OP or M may be wrapped in a NOT operation. */
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void
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rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
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rtx m, rtx op, rtx before_param, rtx after_param,
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bool sync_p)
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{
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enum machine_mode used_mode;
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rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
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rtx used_m;
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rtvec vec;
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HOST_WIDE_INT imask = GET_MODE_MASK (mode);
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rtx shift = NULL_RTX;
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if (sync_p)
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emit_insn (gen_memory_barrier ());
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if (GET_CODE (m) == NOT)
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used_m = XEXP (m, 0);
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else
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used_m = m;
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/* If this is smaller than SImode, we'll have to use SImode with
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adjustments. */
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if (mode == QImode || mode == HImode)
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{
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rtx newop, oldop;
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if (MEM_ALIGN (used_m) >= 32)
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{
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int ishift = 0;
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if (BYTES_BIG_ENDIAN)
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ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
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shift = GEN_INT (ishift);
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}
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else
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{
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rtx addrSI, aligned_addr;
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addrSI = force_reg (SImode, gen_lowpart_common (SImode,
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XEXP (used_m, 0)));
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shift = gen_reg_rtx (SImode);
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emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
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GEN_INT (0x18)));
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aligned_addr = expand_binop (Pmode, and_optab,
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XEXP (used_m, 0),
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GEN_INT (-4), NULL_RTX,
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1, OPTAB_LIB_WIDEN);
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used_m = change_address (used_m, SImode, aligned_addr);
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set_mem_align (used_m, 32);
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/* It's safe to keep the old alias set of USED_M, because
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the operation is atomic and only affects the original
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USED_M. */
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if (GET_CODE (m) == NOT)
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m = gen_rtx_NOT (SImode, used_m);
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else
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m = used_m;
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}
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if (GET_CODE (op) == NOT)
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{
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oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
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oldop = gen_rtx_NOT (SImode, oldop);
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}
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else
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oldop = lowpart_subreg (SImode, op, mode);
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switch (code)
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{
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case IOR:
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case XOR:
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newop = expand_binop (SImode, and_optab,
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oldop, GEN_INT (imask), NULL_RTX,
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1, OPTAB_LIB_WIDEN);
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emit_insn (gen_ashlsi3 (newop, newop, shift));
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break;
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case AND:
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newop = expand_binop (SImode, ior_optab,
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oldop, GEN_INT (~imask), NULL_RTX,
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1, OPTAB_LIB_WIDEN);
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emit_insn (gen_ashlsi3 (newop, newop, shift));
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break;
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case PLUS:
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{
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rtx mask;
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newop = expand_binop (SImode, and_optab,
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oldop, GEN_INT (imask), NULL_RTX,
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1, OPTAB_LIB_WIDEN);
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emit_insn (gen_ashlsi3 (newop, newop, shift));
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mask = gen_reg_rtx (SImode);
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emit_move_insn (mask, GEN_INT (imask));
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emit_insn (gen_ashlsi3 (mask, mask, shift));
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newop = gen_rtx_AND (SImode, gen_rtx_PLUS (SImode, m, newop),
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mask);
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newop = gen_rtx_IOR (SImode, newop,
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gen_rtx_AND (SImode,
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gen_rtx_NOT (SImode, mask),
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m));
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break;
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}
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default:
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gcc_unreachable ();
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}
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op = newop;
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used_mode = SImode;
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before = gen_reg_rtx (used_mode);
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after = gen_reg_rtx (used_mode);
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}
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else
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{
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used_mode = mode;
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before = before_param;
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after = after_param;
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if (before == NULL_RTX)
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before = gen_reg_rtx (used_mode);
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if (after == NULL_RTX)
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after = gen_reg_rtx (used_mode);
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}
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if (code == PLUS && used_mode != mode)
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the_op = op; /* Computed above. */
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else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
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the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
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else
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the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
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set_after = gen_rtx_SET (VOIDmode, after, the_op);
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set_before = gen_rtx_SET (VOIDmode, before, used_m);
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set_atomic = gen_rtx_SET (VOIDmode, used_m,
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gen_rtx_UNSPEC (used_mode, gen_rtvec (1, the_op),
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UNSPEC_SYNC_OP));
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cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
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if (code == PLUS && used_mode != mode)
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vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
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gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
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else
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vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
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emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
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/* Shift and mask the return values properly. */
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if (used_mode != mode && before_param)
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{
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emit_insn (gen_lshrsi3 (before, before, shift));
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convert_move (before_param, before, 1);
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}
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if (used_mode != mode && after_param)
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{
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emit_insn (gen_lshrsi3 (after, after, shift));
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convert_move (after_param, after, 1);
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}
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/* The previous sequence will end with a branch that's dependent on
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the conditional store, so placing an isync will ensure that no
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other instructions (especially, no load or store instructions)
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can start before the atomic operation completes. */
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if (sync_p)
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emit_insn (gen_isync ());
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}
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/* Emit instructions to move SRC to DST. Called by splitters for
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multi-register moves. It will emit at most one instruction for
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each register that is accessed; that is, it won't emit li/lis pairs
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@ -52,6 +52,11 @@
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(UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
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(UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
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(UNSPEC_STFIWX 32)
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(UNSPEC_SYNC 33)
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(UNSPEC_SYNC_OP 34)
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(UNSPEC_SYNC_SWAP 35)
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(UNSPEC_LWSYNC 36)
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(UNSPEC_ISYNC 37)
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])
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;;
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@ -108,10 +113,28 @@
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(include "darwin.md")
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;; This mode macro allows :P to be used for patterns that operate on
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;; pointer-sized quantities. Exactly one of the two alternatives will match.
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;; Mode macros
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; This mode macro allows :GPR to be used to indicate the allowable size
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; of whole values in GPRs.
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(define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
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; Any supported integer mode
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(define_mode_macro INT [QI HI SI DI TI])
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; Any supported integer mode that fits in one register
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(define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
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; This mode macro allows :P to be used for patterns that operate on
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; pointer-sized quantities. Exactly one of the two alternatives will match.
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(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
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; Various instructions that come in SI and DI forms.
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(define_mode_attr larx [(SI "lwarx") (DI "ldarx")])
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(define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")])
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(define_mode_attr cmp [(SI "cmpw") (DI "cmpd")])
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;; Start with fixed-point load and store insns. Here we put only the more
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;; complex forms. Basic data transfer is done later.
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@ -3742,7 +3765,7 @@
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(const_int 0)))]
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"")
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(define_insn ""
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(define_insn "rlwinm"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "const_int_operand" "i"))
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@ -14733,6 +14756,433 @@
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return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
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}"
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[(set_attr "type" "load")])
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; Atomic instructions
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(define_insn "memory_barrier"
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[(set (mem:BLK (match_scratch 0 "X"))
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(unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_SYNC))]
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""
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"{ics|sync}")
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(define_insn "sync_compare_and_swap<mode>"
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[(set (match_operand:GPR 1 "memory_operand" "+Z")
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(unspec:GPR [(match_dup 1)
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(match_operand:GPR 2 "reg_or_short_operand" "rI")
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(match_operand:GPR 3 "gpc_reg_operand" "r")]
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UNSPEC_SYNC_SWAP))
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(set (match_operand:GPR 0 "gpc_reg_operand" "=&r") (match_dup 1))
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(set (mem:BLK (match_scratch 5 "X"))
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(unspec:BLK [(mem:BLK (match_scratch 6 "X"))] UNSPEC_SYNC))
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(clobber (match_scratch:CC 4 "=&x"))]
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"TARGET_POWERPC"
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"sync\n0:\t<larx> %0,%y1\n\t<cmp>%I2 %0,%2\n\tbne- 1f\n\t<stcx> %3,%y1\n\tbne- 0b\n\t1:\tisync"
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[(set_attr "length" "28")])
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(define_expand "sync_add<mode>"
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[(use (match_operand:INT1 0 "memory_operand" ""))
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(use (match_operand:INT1 1 "add_operand" ""))]
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"TARGET_POWERPC"
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"
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{
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rs6000_emit_sync (PLUS, <MODE>mode, operands[0], operands[1],
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NULL_RTX, NULL_RTX, true);
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DONE;
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}")
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(define_expand "sync_sub<mode>"
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[(use (match_operand:GPR 0 "memory_operand" ""))
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(use (match_operand:GPR 1 "gpc_reg_operand" ""))]
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"TARGET_POWERPC"
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"
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{
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rs6000_emit_sync (MINUS, <MODE>mode, operands[0], operands[1],
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NULL_RTX, NULL_RTX, true);
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DONE;
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}")
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(define_expand "sync_ior<mode>"
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[(use (match_operand:INT1 0 "memory_operand" ""))
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(use (match_operand:INT1 1 "logical_operand" ""))]
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"TARGET_POWERPC"
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"
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{
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rs6000_emit_sync (IOR, <MODE>mode, operands[0], operands[1],
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NULL_RTX, NULL_RTX, true);
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DONE;
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}")
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(define_expand "sync_and<mode>"
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[(use (match_operand:INT1 0 "memory_operand" ""))
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(use (match_operand:INT1 1 "and_operand" ""))]
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"TARGET_POWERPC"
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"
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{
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rs6000_emit_sync (AND, <MODE>mode, operands[0], operands[1],
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NULL_RTX, NULL_RTX, true);
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DONE;
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}")
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(define_expand "sync_xor<mode>"
|
||||
[(use (match_operand:INT1 0 "memory_operand" ""))
|
||||
(use (match_operand:INT1 1 "logical_operand" ""))]
|
||||
"TARGET_POWERPC"
|
||||
"
|
||||
{
|
||||
rs6000_emit_sync (XOR, <MODE>mode, operands[0], operands[1],
|
||||
NULL_RTX, NULL_RTX, true);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "sync_nand<mode>"
|
||||
[(use (match_operand:INT1 0 "memory_operand" ""))
|
||||
(use (match_operand:INT1 1 "gpc_reg_operand" ""))]
|
||||
"TARGET_POWERPC"
|
||||
"
|
||||
{
|
||||
rs6000_emit_sync (AND, <MODE>mode,
|
||||
gen_rtx_NOT (<MODE>mode, operands[0]),
|
||||
operands[1],
|
||||
NULL_RTX, NULL_RTX, true);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "sync_old_add<mode>"
|
||||
[(use (match_operand:INT1 0 "gpc_reg_operand" ""))
|
||||
(use (match_operand:INT1 1 "memory_operand" ""))
|
||||
(use (match_operand:INT1 2 "add_operand" ""))]
|
||||
"TARGET_POWERPC"
|
||||
"
|
||||
{
|
||||
rs6000_emit_sync (PLUS, <MODE>mode, operands[1], operands[2],
|
||||
operands[0], NULL_RTX, true);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "sync_old_sub<mode>"
|
||||
[(use (match_operand:GPR 0 "gpc_reg_operand" ""))
|
||||
(use (match_operand:GPR 1 "memory_operand" ""))
|
||||
(use (match_operand:GPR 2 "gpc_reg_operand" ""))]
|
||||
"TARGET_POWERPC"
|
||||
"
|
||||
{
|
||||
rs6000_emit_sync (MINUS, <MODE>mode, operands[1], operands[2],
|
||||
operands[0], NULL_RTX, true);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "sync_old_ior<mode>"
|
||||
[(use (match_operand:INT1 0 "gpc_reg_operand" ""))
|
||||
(use (match_operand:INT1 1 "memory_operand" ""))
|
||||
(use (match_operand:INT1 2 "logical_operand" ""))]
|
||||
"TARGET_POWERPC"
|
||||
"
|
||||
{
|
||||
rs6000_emit_sync (IOR, <MODE>mode, operands[1], operands[2],
|
||||
operands[0], NULL_RTX, true);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "sync_old_and<mode>"
|
||||
[(use (match_operand:INT1 0 "gpc_reg_operand" ""))
|
||||
(use (match_operand:INT1 1 "memory_operand" ""))
|
||||
(use (match_operand:INT1 2 "and_operand" ""))]
|
||||
"TARGET_POWERPC"
|
||||
"
|
||||
{
|
||||
rs6000_emit_sync (AND, <MODE>mode, operands[1], operands[2],
|
||||
operands[0], NULL_RTX, true);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "sync_old_xor<mode>"
|
||||
[(use (match_operand:INT1 0 "gpc_reg_operand" ""))
|
||||
(use (match_operand:INT1 1 "memory_operand" ""))
|
||||
(use (match_operand:INT1 2 "logical_operand" ""))]
|
||||
"TARGET_POWERPC"
|
||||
"
|
||||
{
|
||||
rs6000_emit_sync (XOR, <MODE>mode, operands[1], operands[2],
|
||||
operands[0], NULL_RTX, true);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "sync_old_nand<mode>"
|
||||
[(use (match_operand:INT1 0 "gpc_reg_operand" ""))
|
||||
(use (match_operand:INT1 1 "memory_operand" ""))
|
||||
(use (match_operand:INT1 2 "gpc_reg_operand" ""))]
|
||||
"TARGET_POWERPC"
|
||||
"
|
||||
{
|
||||
rs6000_emit_sync (AND, <MODE>mode,
|
||||
gen_rtx_NOT (<MODE>mode, operands[1]),
|
||||
operands[2],
|
||||
operands[0], NULL_RTX, true);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "sync_new_add<mode>"
|
||||
[(use (match_operand:INT1 0 "gpc_reg_operand" ""))
|
||||
(use (match_operand:INT1 1 "memory_operand" ""))
|
||||
(use (match_operand:INT1 2 "add_operand" ""))]
|
||||
"TARGET_POWERPC"
|
||||
"
|
||||
{
|
||||
rs6000_emit_sync (PLUS, <MODE>mode, operands[1], operands[2],
|
||||
NULL_RTX, operands[0], true);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "sync_new_sub<mode>"
|
||||
[(use (match_operand:GPR 0 "gpc_reg_operand" ""))
|
||||
(use (match_operand:GPR 1 "memory_operand" ""))
|
||||
(use (match_operand:GPR 2 "gpc_reg_operand" ""))]
|
||||
"TARGET_POWERPC"
|
||||
"
|
||||
{
|
||||
rs6000_emit_sync (MINUS, <MODE>mode, operands[1], operands[2],
|
||||
NULL_RTX, operands[0], true);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "sync_new_ior<mode>"
|
||||
[(use (match_operand:INT1 0 "gpc_reg_operand" ""))
|
||||
(use (match_operand:INT1 1 "memory_operand" ""))
|
||||
(use (match_operand:INT1 2 "logical_operand" ""))]
|
||||
"TARGET_POWERPC"
|
||||
"
|
||||
{
|
||||
rs6000_emit_sync (IOR, <MODE>mode, operands[1], operands[2],
|
||||
NULL_RTX, operands[0], true);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "sync_new_and<mode>"
|
||||
[(use (match_operand:INT1 0 "gpc_reg_operand" ""))
|
||||
(use (match_operand:INT1 1 "memory_operand" ""))
|
||||
(use (match_operand:INT1 2 "and_operand" ""))]
|
||||
"TARGET_POWERPC"
|
||||
"
|
||||
{
|
||||
rs6000_emit_sync (AND, <MODE>mode, operands[1], operands[2],
|
||||
NULL_RTX, operands[0], true);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "sync_new_xor<mode>"
|
||||
[(use (match_operand:INT1 0 "gpc_reg_operand" ""))
|
||||
(use (match_operand:INT1 1 "memory_operand" ""))
|
||||
(use (match_operand:INT1 2 "logical_operand" ""))]
|
||||
"TARGET_POWERPC"
|
||||
"
|
||||
{
|
||||
rs6000_emit_sync (XOR, <MODE>mode, operands[1], operands[2],
|
||||
NULL_RTX, operands[0], true);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "sync_new_nand<mode>"
|
||||
[(use (match_operand:INT1 0 "gpc_reg_operand" ""))
|
||||
(use (match_operand:INT1 1 "memory_operand" ""))
|
||||
(use (match_operand:INT1 2 "gpc_reg_operand" ""))]
|
||||
"TARGET_POWERPC"
|
||||
"
|
||||
{
|
||||
rs6000_emit_sync (AND, <MODE>mode,
|
||||
gen_rtx_NOT (<MODE>mode, operands[1]),
|
||||
operands[2],
|
||||
NULL_RTX, operands[0], true);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
; the sync_*_internal patterns all have these operands:
|
||||
; 0 - memory location
|
||||
; 1 - operand
|
||||
; 2 - value in memory after operation
|
||||
; 3 - value in memory immediately before operation
|
||||
|
||||
(define_insn "*sync_add<mode>_internal"
|
||||
[(set (match_operand:GPR 2 "gpc_reg_operand" "=&r,&r")
|
||||
(plus:GPR (match_operand:GPR 0 "memory_operand" "+Z,Z")
|
||||
(match_operand:GPR 1 "add_operand" "rI,L")))
|
||||
(set (match_operand:GPR 3 "gpc_reg_operand" "=&b,&b") (match_dup 0))
|
||||
(set (match_dup 0)
|
||||
(unspec:GPR [(plus:GPR (match_dup 0) (match_dup 1))]
|
||||
UNSPEC_SYNC_OP))
|
||||
(clobber (match_scratch:CC 4 "=&x,&x"))]
|
||||
"TARGET_POWERPC"
|
||||
"@
|
||||
0:\t<larx> %3,%y0\n\tadd%I1 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- 0b
|
||||
0:\t<larx> %3,%y0\n\taddis %2,%3,%v1\n\t<stcx> %2,%y0\n\tbne- 0b"
|
||||
[(set_attr "length" "16,16")])
|
||||
|
||||
(define_insn "*sync_addshort_internal"
|
||||
[(set (match_operand:SI 2 "gpc_reg_operand" "=&r")
|
||||
(ior:SI (and:SI (plus:SI (match_operand:SI 0 "memory_operand" "+Z")
|
||||
(match_operand:SI 1 "add_operand" "rI"))
|
||||
(match_operand:SI 4 "gpc_reg_operand" "r"))
|
||||
(and:SI (not:SI (match_dup 4)) (match_dup 0))))
|
||||
(set (match_operand:SI 3 "gpc_reg_operand" "=&b") (match_dup 0))
|
||||
(set (match_dup 0)
|
||||
(unspec:SI [(ior:SI (and:SI (plus:SI (match_dup 0) (match_dup 1))
|
||||
(match_dup 4))
|
||||
(and:SI (not:SI (match_dup 4)) (match_dup 0)))]
|
||||
UNSPEC_SYNC_OP))
|
||||
(clobber (match_scratch:CC 5 "=&x"))
|
||||
(clobber (match_scratch:SI 6 "=&r"))]
|
||||
"TARGET_POWERPC"
|
||||
"0:\tlwarx %3,%y0\n\tadd%I1 %2,%3,%1\n\tandc %6,%3,%4\n\tand %2,%2,%4\n\tor %2,%2,%6\n\tstwcx. %2,%y0\n\tbne- 0b"
|
||||
[(set_attr "length" "28")])
|
||||
|
||||
(define_insn "*sync_sub<mode>_internal"
|
||||
[(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
|
||||
(minus:GPR (match_operand:GPR 0 "memory_operand" "+Z")
|
||||
(match_operand:GPR 1 "gpc_reg_operand" "r")))
|
||||
(set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
|
||||
(set (match_dup 0)
|
||||
(unspec:GPR [(minus:GPR (match_dup 0) (match_dup 1))]
|
||||
UNSPEC_SYNC_OP))
|
||||
(clobber (match_scratch:CC 4 "=&x"))]
|
||||
"TARGET_POWERPC"
|
||||
"0:\t<larx> %3,%y0\n\tsubf %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- 0b"
|
||||
[(set_attr "length" "16")])
|
||||
|
||||
(define_insn "*sync_andsi_internal"
|
||||
[(set (match_operand:SI 2 "gpc_reg_operand" "=&r,&r,&r,&r")
|
||||
(and:SI (match_operand:SI 0 "memory_operand" "+Z,Z,Z,Z")
|
||||
(match_operand:SI 1 "and_operand" "r,T,K,L")))
|
||||
(set (match_operand:SI 3 "gpc_reg_operand" "=&b,&b,&b,&b") (match_dup 0))
|
||||
(set (match_dup 0)
|
||||
(unspec:SI [(and:SI (match_dup 0) (match_dup 1))]
|
||||
UNSPEC_SYNC_OP))
|
||||
(clobber (match_scratch:CC 4 "=&x,&x,&x,&x"))]
|
||||
"TARGET_POWERPC"
|
||||
"@
|
||||
0:\tlwarx %3,%y0\n\tand %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- 0b
|
||||
0:\tlwarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstwcx. %2,%y0\n\tbne- 0b
|
||||
0:\tlwarx %3,%y0\n\tandi. %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- 0b
|
||||
0:\tlwarx %3,%y0\n\tandis. %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- 0b"
|
||||
[(set_attr "length" "16,16,16,16")])
|
||||
|
||||
(define_insn "*sync_anddi_internal"
|
||||
[(set (match_operand:DI 2 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
|
||||
(and:DI (match_operand:DI 0 "memory_operand" "+Z,Z,Z,Z,Z")
|
||||
(match_operand:DI 1 "and_operand" "r,S,T,K,J")))
|
||||
(set (match_operand:DI 3 "gpc_reg_operand" "=&b,&b,&b,&b,&b") (match_dup 0))
|
||||
(set (match_dup 0)
|
||||
(unspec:DI [(and:DI (match_dup 0) (match_dup 1))]
|
||||
UNSPEC_SYNC_OP))
|
||||
(clobber (match_scratch:CC 4 "=&x,&x,&x,&x,&x"))]
|
||||
"TARGET_POWERPC64"
|
||||
"@
|
||||
0:\tldarx %3,%y0\n\tand %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- 0b
|
||||
0:\tldarx %3,%y0\n\trldic%B1 %2,%3,0,%S1\n\tstdcx. %2,%y0\n\tbne- 0b
|
||||
0:\tldarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstdcx. %2,%y0\n\tbne- 0b
|
||||
0:\tldarx %3,%y0\n\tandi. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- 0b
|
||||
0:\tldarx %3,%y0\n\tandis. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- 0b"
|
||||
[(set_attr "length" "16,16,16,16,16")])
|
||||
|
||||
(define_insn "*sync_boolsi_internal"
|
||||
[(set (match_operand:SI 2 "gpc_reg_operand" "=&r,&r,&r")
|
||||
(match_operator:SI 4 "boolean_or_operator"
|
||||
[(match_operand:SI 0 "memory_operand" "+Z,Z,Z")
|
||||
(match_operand:SI 1 "logical_operand" "r,K,L")]))
|
||||
(set (match_operand:SI 3 "gpc_reg_operand" "=&b,&b,&b") (match_dup 0))
|
||||
(set (match_dup 0) (unspec:SI [(match_dup 4)] UNSPEC_SYNC_OP))
|
||||
(clobber (match_scratch:CC 5 "=&x,&x,&x"))]
|
||||
"TARGET_POWERPC"
|
||||
"@
|
||||
0:\tlwarx %3,%y0\n\t%q4 %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- 0b
|
||||
0:\tlwarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- 0b
|
||||
0:\tlwarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- 0b"
|
||||
[(set_attr "length" "16,16,16")])
|
||||
|
||||
(define_insn "*sync_booldi_internal"
|
||||
[(set (match_operand:DI 2 "gpc_reg_operand" "=&r,&r,&r")
|
||||
(match_operator:DI 4 "boolean_or_operator"
|
||||
[(match_operand:DI 0 "memory_operand" "+Z,Z,Z")
|
||||
(match_operand:DI 1 "logical_operand" "r,K,JF")]))
|
||||
(set (match_operand:DI 3 "gpc_reg_operand" "=&b,&b,&b") (match_dup 0))
|
||||
(set (match_dup 0) (unspec:DI [(match_dup 4)] UNSPEC_SYNC_OP))
|
||||
(clobber (match_scratch:CC 5 "=&x,&x,&x"))]
|
||||
"TARGET_POWERPC64"
|
||||
"@
|
||||
0:\tldarx %3,%y0\n\t%q4 %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- 0b
|
||||
0:\tldarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- 0b
|
||||
0:\tldarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstdcx. %2,%y0\n\tbne- 0b"
|
||||
[(set_attr "length" "16,16,16")])
|
||||
|
||||
(define_insn "*sync_boolc<mode>_internal"
|
||||
[(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
|
||||
(match_operator:GPR 4 "boolean_operator"
|
||||
[(not:GPR (match_operand:GPR 0 "memory_operand" "+Z"))
|
||||
(match_operand:GPR 1 "gpc_reg_operand" "r")]))
|
||||
(set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
|
||||
(set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
|
||||
(clobber (match_scratch:CC 5 "=&x"))]
|
||||
"TARGET_POWERPC"
|
||||
"0:\t<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- 0b"
|
||||
[(set_attr "length" "16")])
|
||||
|
||||
(define_insn "*sync_boolc<mode>_internal2"
|
||||
[(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
|
||||
(match_operator:GPR 4 "boolean_operator"
|
||||
[(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
|
||||
(match_operand:GPR 0 "memory_operand" "+Z")]))
|
||||
(set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
|
||||
(set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
|
||||
(clobber (match_scratch:CC 5 "=&x"))]
|
||||
"TARGET_POWERPC"
|
||||
"0:\t<larx> %3,%y0\n\t%q4 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- 0b"
|
||||
[(set_attr "length" "16")])
|
||||
|
||||
(define_insn "*sync_boolcc<mode>_internal"
|
||||
[(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
|
||||
(match_operator:GPR 4 "boolean_operator"
|
||||
[(not:GPR (match_operand:GPR 0 "memory_operand" "+Z"))
|
||||
(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))]))
|
||||
(set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
|
||||
(set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
|
||||
(clobber (match_scratch:CC 5 "=&x"))]
|
||||
"TARGET_POWERPC"
|
||||
"0:\t<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- 0b"
|
||||
[(set_attr "length" "16")])
|
||||
|
||||
(define_insn "isync"
|
||||
[(set (mem:BLK (match_scratch 0 "X"))
|
||||
(unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_ISYNC))]
|
||||
"TARGET_POWERPC"
|
||||
"isync")
|
||||
|
||||
(define_insn "sync_lock_test_and_set<mode>"
|
||||
[(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
|
||||
(match_operand:GPR 1 "memory_operand" "+Z"))
|
||||
(set (match_dup 1) (unspec:GPR [(match_operand:GPR 2 "gpc_reg_operand" "r")]
|
||||
UNSPEC_SYNC_OP))
|
||||
(clobber (match_scratch:CC 3 "=&x"))
|
||||
(set (mem:BLK (match_scratch 4 "X"))
|
||||
(unspec:BLK [(mem:BLK (match_scratch 5 "X"))] UNSPEC_ISYNC))]
|
||||
"TARGET_POWERPC"
|
||||
"0:\t<larx> %0,%y1\n\t<stcx> %2,%y1\n\tbne- 0b\n\tisync"
|
||||
[(set_attr "length" "16")])
|
||||
|
||||
(define_expand "sync_lock_release<mode>"
|
||||
[(use (match_operand:INT 0 "memory_operand"))]
|
||||
""
|
||||
"
|
||||
{
|
||||
emit_insn (gen_lwsync ());
|
||||
emit_move_insn (operands[0], CONST0_RTX (<MODE>mode));
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_insn "lwsync"
|
||||
[(set (mem:BLK (match_scratch 0 "X"))
|
||||
(unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_LWSYNC))]
|
||||
""
|
||||
"lwsync")
|
||||
|
||||
|
||||
|
||||
(include "altivec.md")
|
||||
(include "spe.md")
|
||||
|
||||
@ -3952,14 +3952,16 @@ operation. Operand 1 is the memory on which the atomic operation is
|
||||
performed. Operand 2 is the ``old'' value to be compared against the
|
||||
current contents of the memory location. Operand 3 is the ``new'' value
|
||||
to store in the memory if the compare succeeds. Operand 0 is the result
|
||||
of the operation; it should contain the current contents of the memory
|
||||
after the operation. If the compare succeeds, this should obviously be
|
||||
a copy of operand 3.
|
||||
of the operation; it should contain the contents of the memory
|
||||
before the operation. If the compare succeeds, this should obviously be
|
||||
a copy of operand 2.
|
||||
|
||||
This pattern must show that both operand 0 and operand 1 are modified.
|
||||
|
||||
This pattern must issue any memory barrier instructions such that the
|
||||
pattern as a whole acts as a full barrier.
|
||||
This pattern must issue any memory barrier instructions such that all
|
||||
memory operations before the atomic operation occur before the atomic
|
||||
operation and all memory operations after the atomic operation occur
|
||||
after the atomic operation.
|
||||
|
||||
@cindex @code{sync_compare_and_swap_cc@var{mode}} instruction pattern
|
||||
@item @samp{sync_compare_and_swap_cc@var{mode}}
|
||||
@ -3991,8 +3993,10 @@ Operand 1 is the second operand to the binary operator.
|
||||
|
||||
The ``nand'' operation is @code{op0 & ~op1}.
|
||||
|
||||
This pattern must issue any memory barrier instructions such that the
|
||||
pattern as a whole acts as a full barrier.
|
||||
This pattern must issue any memory barrier instructions such that all
|
||||
memory operations before the atomic operation occur before the atomic
|
||||
operation and all memory operations after the atomic operation occur
|
||||
after the atomic operation.
|
||||
|
||||
If these patterns are not defined, the operation will be constructed
|
||||
from a compare-and-swap operation, if defined.
|
||||
@ -4013,8 +4017,10 @@ Operand 0 is the result value, operand 1 is the memory on which the
|
||||
atomic operation is performed, and operand 2 is the second operand
|
||||
to the binary operator.
|
||||
|
||||
This pattern must issue any memory barrier instructions such that the
|
||||
pattern as a whole acts as a full barrier.
|
||||
This pattern must issue any memory barrier instructions such that all
|
||||
memory operations before the atomic operation occur before the atomic
|
||||
operation and all memory operations after the atomic operation occur
|
||||
after the atomic operation.
|
||||
|
||||
If these patterns are not defined, the operation will be constructed
|
||||
from a compare-and-swap operation, if defined.
|
||||
@ -4052,7 +4058,8 @@ an atomic test-and-set bit operation. The result operand should contain
|
||||
The true contents of the memory operand are implementation defined.
|
||||
|
||||
This pattern must issue any memory barrier instructions such that the
|
||||
pattern as a whole acts as an acquire barrier.
|
||||
pattern as a whole acts as an acquire barrier, that is all memory
|
||||
operations after the pattern do not occur until the lock is acquired.
|
||||
|
||||
If this pattern is not defined, the operation will be constructed from
|
||||
a compare-and-swap operation, if defined.
|
||||
@ -4065,7 +4072,8 @@ This pattern, if defined, releases a lock set by
|
||||
that contains the lock.
|
||||
|
||||
This pattern must issue any memory barrier instructions such that the
|
||||
pattern as a whole acts as a release barrier.
|
||||
pattern as a whole acts as a release barrier, that is the lock is
|
||||
released only after all previous memory operations have completed.
|
||||
|
||||
If this pattern is not defined, then a @code{memory_barrier} pattern
|
||||
will be emitted, followed by a store of zero to the memory operand.
|
||||
|
||||
@ -1,3 +1,8 @@
|
||||
2005-04-21 Geoffrey Keating <geoffk@apple.com>
|
||||
|
||||
* lib/target-supports.exp (check_effective_target_sync_int_long):
|
||||
Add powerpc*.
|
||||
|
||||
2005-04-21 Richard Sandiford <rsandifo@redhat.com>
|
||||
|
||||
* gcc.target/mips/branch-1.c: New test.
|
||||
|
||||
@ -883,10 +883,13 @@ proc check_effective_target_sync_int_long { } {
|
||||
verbose "check_effective_target_sync_int_long: using cached result" 2
|
||||
} else {
|
||||
set et_sync_int_long_saved 0
|
||||
# This is intentionally powerpc but not rs6000, rs6000 doesn't have the
|
||||
# load-reserved/store-conditional instructions.
|
||||
if { [istarget ia64-*-*]
|
||||
|| [istarget i?86-*-*]
|
||||
|| [istarget x86_64-*-*]
|
||||
|| [istarget alpha*-*-*] } {
|
||||
|| [istarget alpha*-*-*]
|
||||
|| [istarget powerpc*-*-*] } {
|
||||
set et_sync_int_long_saved 1
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user