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builtins.c, [...]: Fix comment typos. 

* builtins.c, config/arm/arm.c, config/i386/cygwin.h,
	config/i386/i386.c, config/ia64/ia64.c, config/s390/fixdfdi.h,
	config/sh/sh.c, config/sh/sh.h, df-scan.c, except.c,
	haifa-sched.c, optabs.c, rtl.h, sched-deps.c, sched-int.h,
	sched-rgn.c, tree-inline.h, tree-ssa-dom.c,
	tree-ssa-loop-prefetch.c, tree-ssa-operands.c,
	tree-vect-patterns.c, tree-vrp.c: Fix comment typos.  Follow
	spelling convensions.
	* config/ia64/ia64.opt, doc/contrib.texi, doc/invoke.texi,
	doc/passes.texi, doc/tm.texi, doc/tree-ssa.texi: Fix comment
	typos.  Follow spelling conventions.

From-SVN: r112782
This commit is contained in:
Kazu Hirata 2006-04-08 17:01:17 +00:00 committed by Kazu Hirata
parent b82feea52f
commit 917f1b7ea3
29 changed files with 94 additions and 80 deletions
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14
gcc/ChangeLog
View File

@ -1,3 +1,17 @@
2006-04-08 Kazu Hirata <kazu@codesourcery.com>
* builtins.c, config/arm/arm.c, config/i386/cygwin.h,
config/i386/i386.c, config/ia64/ia64.c, config/s390/fixdfdi.h,
config/sh/sh.c, config/sh/sh.h, df-scan.c, except.c,
haifa-sched.c, optabs.c, rtl.h, sched-deps.c, sched-int.h,
sched-rgn.c, tree-inline.h, tree-ssa-dom.c,
tree-ssa-loop-prefetch.c, tree-ssa-operands.c,
tree-vect-patterns.c, tree-vrp.c: Fix comment typos. Follow
spelling convensions.
* config/ia64/ia64.opt, doc/contrib.texi, doc/invoke.texi,
doc/passes.texi, doc/tm.texi, doc/tree-ssa.texi: Fix comment
typos. Follow spelling conventions.
2006-04-07 DJ Delorie <dj@redhat.com>
* config/m32c/m32c.c (m32c_function_arg): Structures are always

2
gcc/builtins.c
View File

@ -278,7 +278,7 @@ get_pointer_alignment (tree exp, unsigned int max_align)
inner = max_align;
while (handled_component_p (exp))
{
/* Fields in a structure can be packed, honour DECL_ALIGN
/* Fields in a structure can be packed, honor DECL_ALIGN
of the FIELD_DECL. For all other references the conservative
alignment is the element type alignment. */
if (TREE_CODE (exp) == COMPONENT_REF)

2
gcc/config/arm/arm.c
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@ -8003,7 +8003,7 @@ push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
/* If an entry requires 8-byte alignment then assume all constant pools
require 4 bytes of padding. Trying to do this later on a per-pool
basis is awkward becuse existing pool entries have to be modified. */
basis is awkward because existing pool entries have to be modified. */
if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
minipool_pad = 4;

2
gcc/config/i386/cygwin.h
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@ -235,6 +235,6 @@ while (0)
/* Every program on cygwin links against cygwin1.dll which contains
the pthread routines. There is no need to explicitly link them
and the -pthread flag is not recognised. */
and the -pthread flag is not recognized. */
#undef GOMP_SELF_SPECS
#define GOMP_SELF_SPECS ""

2
gcc/config/i386/i386.c
View File

@ -16372,7 +16372,7 @@ ix86_preferred_reload_class (rtx x, enum reg_class class)
if (x == CONST0_RTX (mode))
return class;
/* Force constants into memory if we are loading a (non-zero) constant into
/* Force constants into memory if we are loading a (nonzero) constant into
an MMX or SSE register. This is because there are no MMX/SSE instructions
to load from a constant. */
if (CONSTANT_P (x)

2
gcc/config/ia64/ia64.c
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@ -8306,7 +8306,7 @@ ia64_ld_address_bypass_p (rtx producer, rtx consumer)
if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
mem = XVECEXP (mem, 0, 0);
else if (GET_CODE (mem) == IF_THEN_ELSE)
/* ??? Is this bypass neccessary for ld.c? */
/* ??? Is this bypass necessary for ld.c? */
{
gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR);
mem = XEXP (mem, 1);

4
gcc/config/ia64/ia64.opt
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@ -134,11 +134,11 @@ Print information about speculative motions.
msched-prefer-non-data-spec-insns
Common Report Var(mflag_sched_prefer_non_data_spec_insns) Init(0)
If set, data speculative instructions will be choosen for schedule only if there are no other choices at the moment
If set, data speculative instructions will be chosen for schedule only if there are no other choices at the moment
msched-prefer-non-control-spec-insns
Common Report Var(mflag_sched_prefer_non_control_spec_insns) Init(0)
If set, control speculative instructions will be choosen for schedule only if there are no other choices at the moment
If set, control speculative instructions will be chosen for schedule only if there are no other choices at the moment
msched-count-spec-in-critical-path
Common Report Var(mflag_sched_count_spec_in_critical_path) Init(0)

4
gcc/config/s390/fixdfdi.h
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@ -74,7 +74,7 @@ __fixunstfdi (long double a1)
if (exp <= -PRECISION)
return 0;
/* NaN: All exponent bits set and a non-zero fraction. */
/* NaN: All exponent bits set and a nonzero fraction. */
if ((EXPD(dl1) == 0x7fff) && !FRACD_ZERO_P (dl1))
return 0x0ULL;
@ -146,7 +146,7 @@ __fixtfdi (long double a1)
if (exp <= -PRECISION)
return 0;
/* NaN: All exponent bits set and a non-zero fraction. */
/* NaN: All exponent bits set and a nonzero fraction. */
if ((EXPD(dl1) == 0x7fff) && !FRACD_ZERO_P (dl1))
return 0x8000000000000000ULL;

2
gcc/config/sh/sh.c
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@ -6818,7 +6818,7 @@ sh_va_start (tree valist, rtx nextarg)
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
}
/* TYPE is a RECORD_TYPE. If there is only a single non-zero-sized
/* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
member, return it. */
static tree
find_sole_member (tree type)

4
gcc/config/sh/sh.h
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@ -507,8 +507,8 @@ enum sh_divide_strategy_e {
SH_DIV_INV_CALL2,
SH_DIV_INV_FP,
/* SH1 .. SH4 strategies. Because of the small number of registers
available, the compiler uses knowledge of the actual et of registers
being clobbed by the different functions called. */
available, the compiler uses knowledge of the actual set of registers
being clobbered by the different functions called. */
SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */

2
gcc/df-scan.c
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@ -1603,7 +1603,7 @@ df_bb_refs_record (struct dataflow *dflow, basic_block bb)
DF_REF_ARTIFICIAL | DF_REF_AT_TOP);
#endif
/* The following code (down thru the arg_pointer seting APPEARS
/* The following code (down thru the arg_pointer setting APPEARS
to be necessary because there is nothing that actually
describes what the exception handling code may actually need
to keep alive. */

4
gcc/doc/contrib.texi
View File

@ -1300,7 +1300,7 @@ Ingo Proetel for @code{Image}, @code{Logger} and @code{URLClassLoader}
updates.
@item
Olga Rodimina for @code{MenuSelectionManager} implemenation.
Olga Rodimina for @code{MenuSelectionManager} implementation.
@item
Jan Roehrich for @code{BasicTreeUI} and @code{JTree} fixes.
@ -1324,7 +1324,7 @@ Christian Thalinger for 64-bit cleanups, Configuration and VM
interface fixes and @code{CACAO} integration, @code{fdlibm} updates.
@item
Gael Thomas for @code{VMClassLoader} boot packages support sugestions.
Gael Thomas for @code{VMClassLoader} boot packages support suggestions.
@item
Andreas Tobler for Darwin and Solaris testing and fixing, @code{Qt4}

8
gcc/doc/invoke.texi
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@ -9170,7 +9170,7 @@ Intel PentiumMMX CPU based on Pentium core with MMX instruction set support.
Intel PentiumPro CPU@.
@item i686
Same as @code{generic}, but when used as @code{march} option, PentiumPro
instruction set will be used, so the code will run on all i686 familly chips.
instruction set will be used, so the code will run on all i686 family chips.
@item pentium2
Intel Pentium2 CPU based on PentiumPro core with MMX instruction set support.
@item pentium3, pentium3m
@ -9844,7 +9844,7 @@ The default is 'disable'.
@itemx -msched-prefer-non-data-spec-insns
@opindex -mno-sched-prefer-non-data-spec-insns
@opindex -msched-prefer-non-data-spec-insns
If enabled, data speculative instructions will be choosen for schedule
If enabled, data speculative instructions will be chosen for schedule
only if there are no other choices at the moment. This will make
the use of the data speculation much more conservative.
The default is 'disable'.
@ -9853,7 +9853,7 @@ The default is 'disable'.
@itemx -msched-prefer-non-control-spec-insns
@opindex -mno-sched-prefer-non-control-spec-insns
@opindex -msched-prefer-non-control-spec-insns
If enabled, control speculative instructions will be choosen for schedule
If enabled, control speculative instructions will be chosen for schedule
only if there are no other choices at the moment. This will make
the use of the control speculation much more conservative.
The default is 'disable'.
@ -9862,7 +9862,7 @@ The default is 'disable'.
@itemx -msched-count-spec-in-critical-path
@opindex -mno-sched-count-spec-in-critical-path
@opindex -msched-count-spec-in-critical-path
If enabled, speculative depedencies will be considered during
If enabled, speculative dependencies will be considered during
computation of the instructions priorities. This will make the use of the
speculation a bit more conservative.
The default is 'disable'.

2
gcc/doc/passes.texi
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@ -202,7 +202,7 @@ declarations of static variables whose lifetimes extend to the entire
program. The pass is located in @file{tree-mudflap.c} and is described
by @code{pass_mudflap_1}.
@item OpenMP lowerering
@item OpenMP lowering
If OpenMP generation (@option{-fopenmp}) is enabled, this pass lowers
OpenMP constructs into GIMPLE.

12
gcc/doc/tm.texi
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@ -4191,7 +4191,7 @@ be because the function prologue moves it to a different place.
the context of the called function, and @code{0} in the context of
the caller.
If @var{incoming} is non-zero and the address is to be found on the
If @var{incoming} is nonzero and the address is to be found on the
stack, return a @code{mem} which refers to the frame pointer. If
@var{incoming} is @code{2}, the result is being used to fetch the
structure value address at the beginning of a function. If you need
@ -6024,7 +6024,7 @@ This hook is a modified version of @samp{TARGET_SCHED_ADJUST_COST}. Instead
of passing dependence as a second parameter, it passes a type of that
dependence. This is useful to calculate cost of dependence between insns
not having the corresponding link. If @samp{TARGET_SCHED_ADJUST_COST_2} is
definded it is used instead of @samp{TARGET_SCHED_ADJUST_COST}.
defined it is used instead of @samp{TARGET_SCHED_ADJUST_COST}.
@end deftypefn
@deftypefn {Target Hook} void TARGET_SCHED_H_I_D_EXTENDED (void)
@ -6046,7 +6046,7 @@ the generated speculative pattern.
@deftypefn {Target Hook} int TARGET_SCHED_NEEDS_BLOCK_P (rtx @var{insn})
This hook is called by the insn scheduler during generation of recovery code
for @var{insn}. It should return non-zero, if the corresponding check
for @var{insn}. It should return nonzero, if the corresponding check
instruction should branch to recovery code, or zero otherwise.
@end deftypefn
@ -6056,7 +6056,7 @@ check instruction. If @var{mutate_p} is zero, then @var{insn} is a
speculative instruction for which the check should be generated.
@var{label} is either a label of a basic block, where recovery code should
be emitted, or a null pointer, when requested check doesn't branch to
recovery code (a simple check). If @var{mutate_p} is non-zero, then
recovery code (a simple check). If @var{mutate_p} is nonzero, then
a pattern for a branchy check corresponding to a simple check denoted by
@var{insn} should be generated. In this case @var{label} can't be null.
@end deftypefn
@ -6067,7 +6067,7 @@ This hook is used as a workaround for
called on the first instruction of the ready list. The hook is used to
discard speculative instruction that stand first in the ready list from
being scheduled on the current cycle. For non-speculative instructions,
the hook should always return non-zero. For example, in the ia64 backend
the hook should always return nonzero. For example, in the ia64 backend
the hook is used to cancel data speculative insns when the ALAT table
is nearly full.
@end deftypefn
@ -6077,7 +6077,7 @@ This hook is used by the insn scheduler to find out what features should be
enabled/used. @var{flags} initially may have either the SCHED_RGN or SCHED_EBB
bit set. This denotes the scheduler pass for which the data should be
provided. The target backend should modify @var{flags} by modifying
the bits correponding to the following features: USE_DEPS_LIST, USE_GLAT,
the bits corresponding to the following features: USE_DEPS_LIST, USE_GLAT,
DETACH_LIFE_INFO, and DO_SPECULATION. For the DO_SPECULATION feature
an additional structure @var{spec_info} should be filled by the target.
The structure describes speculation types that can be used in the scheduler.

2
gcc/doc/tree-ssa.texi
View File

@ -1392,7 +1392,7 @@ mainly because the set of virtual operands for a statement may change at
what some would consider unexpected times. In general, any time you
have modified a statement that has virtual operands, you should verify
whether the list of virtual operands has changed, and if so, mark the
newly exposed symbols by callnig @code{mark_new_vars_to_rename}.
newly exposed symbols by calling @code{mark_new_vars_to_rename}.
There is one additional caveat to preserving virtual SSA form. When the
entire set of virtual operands may be eliminated due to better

4
gcc/except.c
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@ -858,7 +858,7 @@ current_function_has_exception_handlers (void)
}
/* A subroutine of duplicate_eh_regions. Search the region tree under O
for the miniumum and maximum region numbers. Update *MIN and *MAX. */
for the minimum and maximum region numbers. Update *MIN and *MAX. */
static void
duplicate_eh_regions_0 (eh_region o, int *min, int *max)
@ -912,7 +912,7 @@ duplicate_eh_regions_1 (eh_region old, eh_region outer, int eh_offset)
return ret;
}
/* Duplicate the EH regions of IFUN, rootted at COPY_REGION, into current
/* Duplicate the EH regions of IFUN, rooted at COPY_REGION, into current
function and root the tree below OUTER_REGION. Remap labels using MAP
callback. The special case of COPY_REGION of 0 means all regions. */

40
gcc/haifa-sched.c
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@ -217,7 +217,7 @@ static spec_info_t spec_info;
Used to determine, if we need to fix INSN_TICKs. */
static bool added_recovery_block_p;
/* Counters of different types of speculative isntructions. */
/* Counters of different types of speculative instructions. */
static int nr_begin_data, nr_be_in_data, nr_begin_control, nr_be_in_control;
/* Pointers to GLAT data. See init_glat for more information. */
@ -977,7 +977,7 @@ ready_lastpos (struct ready_list *ready)
}
/* Add an element INSN to the ready list so that it ends up with the
lowest/highest priority dependending on FIRST_P. */
lowest/highest priority depending on FIRST_P. */
HAIFA_INLINE static void
ready_add (struct ready_list *ready, rtx insn, bool first_p)
@ -1598,7 +1598,7 @@ find_insn_reg_weight (basic_block bb)
find_insn_reg_weight1 (insn);
}
/* Calculate INSN_REG_WEIGHT for single insntruction.
/* Calculate INSN_REG_WEIGHT for single instruction.
Separated from find_insn_reg_weight because of need
to initialize new instruction in generate_recovery_code. */
static void
@ -2034,7 +2034,7 @@ static int cached_issue_rate = 0;
make this function tries different samples of ready insns. READY
is current queue `ready'. Global array READY_TRY reflects what
insns are already issued in this try. MAX_POINTS is the sum of points
of all instructions in READY. The function stops immediatelly,
of all instructions in READY. The function stops immediately,
if it reached the such a solution, that all instruction can be issued.
INDEX will contain index of the best insn in READY. The following
function is used only for first cycle multipass scheduling. */
@ -2463,7 +2463,7 @@ schedule_block (basic_block *target_bb, int rgn_n_insns1)
continue;
}
/* DECISSION is made. */
/* DECISION is made. */
if (TODO_SPEC (insn) & SPECULATIVE)
generate_recovery_code (insn);
@ -2472,7 +2472,7 @@ schedule_block (basic_block *target_bb, int rgn_n_insns1)
/* This is used to to switch basic blocks by request
from scheduler front-end (actually, sched-ebb.c only).
This is used to process blocks with single fallthru
edge. If successing block has jump, it [jump] will try
edge. If succeeding block has jump, it [jump] will try
move at the end of current bb, thus corrupting CFG. */
|| current_sched_info->advance_target_bb (*target_bb, insn))
{
@ -2869,7 +2869,7 @@ sched_finish (void)
}
/* Fix INSN_TICKs of the instructions in the current block as well as
INSN_TICKs of their dependants.
INSN_TICKs of their dependents.
HEAD and TAIL are the begin and the end of the current scheduled block. */
static void
fix_inter_tick (rtx head, rtx tail)
@ -3116,7 +3116,7 @@ fix_tick_ready (rtx next)
tick = INSN_TICK (next);
/* if tick is not equal to INVALID_TICK, then update
INSN_TICK of NEXT with the most recent resolved dependence
cost. Overwise, recalculate from scratch. */
cost. Otherwise, recalculate from scratch. */
full_p = tick == INVALID_TICK;
do
{
@ -3163,7 +3163,7 @@ change_queue_index (rtx next, int delay)
/* We have nothing to do. */
return;
/* Remove NEXT from whereever it is now. */
/* Remove NEXT from wherever it is now. */
if (i == QUEUE_READY)
ready_remove_insn (next);
else if (i >= 0)
@ -3318,7 +3318,7 @@ process_insn_depend_be_in_spec (rtx link, rtx twin, ds_t fs)
{
gcc_assert (!(ds & BE_IN_SPEC));
if (/* If this dep can be overcomed with 'begin speculation'. */
if (/* If this dep can be overcome with 'begin speculation'. */
ds & BEGIN_SPEC)
/* Then we have a choice: keep the dep 'begin speculative'
or transform it into 'be in speculative'. */
@ -3421,7 +3421,7 @@ add_to_speculative_block (rtx insn)
twins = alloc_INSN_LIST (twin, twins);
/* Add dependences between TWIN and all apropriate
/* Add dependences between TWIN and all appropriate
instructions from REC. */
do
{
@ -3696,7 +3696,7 @@ create_check_block_twin (rtx insn, bool mutate_p)
gcc_assert (ORIG_PAT (insn));
/* Initialize TWIN (twin is a dublicate of original instruction
/* Initialize TWIN (twin is a duplicate of original instruction
in the recovery block). */
if (rec != EXIT_BLOCK_PTR)
{
@ -3896,7 +3896,7 @@ create_check_block_twin (rtx insn, bool mutate_p)
add_back_forw_dep (check, insn, REG_DEP_TRUE, DEP_TRUE | DEP_OUTPUT);
if (!mutate_p)
/* Fix priorities. If MUTATE_P is nonzero, this is not neccessary,
/* Fix priorities. If MUTATE_P is nonzero, this is not necessary,
because it'll be done later in add_to_speculative_block. */
{
clear_priorities (twin);
@ -3906,7 +3906,7 @@ create_check_block_twin (rtx insn, bool mutate_p)
/* Removes dependency between instructions in the recovery block REC
and usual region instructions. It keeps inner dependences so it
won't be neccessary to recompute them. */
won't be necessary to recompute them. */
static void
fix_recovery_deps (basic_block rec)
{
@ -4065,7 +4065,7 @@ dump_new_block_header (int i, basic_block bb, rtx head, rtx tail)
/* Unlink basic block notes and labels and saves them, so they
can be easily restored. We unlink basic block notes in EBB to
provide back-compatability with the previous code, as target backends
provide back-compatibility with the previous code, as target backends
assume, that there'll be only instructions between
current_sched_info->{head and tail}. We restore these notes as soon
as we can.
@ -4308,8 +4308,8 @@ move_succs (VEC(edge,gc) **succsp, basic_block to)
/* Initialize GLAT (global_live_at_{start, end}) structures.
GLAT structures are used to substitute global_live_{start, end}
regsets during scheduling. This is neccessary to use such functions as
split_block (), as they assume consistancy of register live information. */
regsets during scheduling. This is necessary to use such functions as
split_block (), as they assume consistency of register live information. */
static void
init_glat (void)
{
@ -4530,7 +4530,7 @@ debug_spec_status (ds_t s)
}
/* Helper function for check_cfg.
Return non-zero, if edge vector pointed to by EL has edge with TYPE in
Return nonzero, if edge vector pointed to by EL has edge with TYPE in
its flags. */
static int
has_edge_p (VEC(edge,gc) *el, int type)
@ -4631,7 +4631,7 @@ check_cfg (rtx head, rtx tail)
gcc_assert (bb == 0);
}
/* Perform few consistancy checks of flags in different data structures. */
/* Perform a few consistency checks of flags in different data structures. */
static void
check_sched_flags (void)
{
@ -4650,7 +4650,7 @@ check_sched_flags (void)
/* Check global_live_at_{start, end} regsets.
If FATAL_P is TRUE, then abort execution at the first failure.
Overwise, print diagnostics to STDERR (this mode is for calling
Otherwise, print diagnostics to STDERR (this mode is for calling
from debugger). */
void
check_reg_live (bool fatal_p)

2
gcc/optabs.c
View File

@ -3710,7 +3710,7 @@ prepare_cmp_insn (rtx *px, rtx *py, enum rtx_code *pcomparison, rtx size,
to the modified comparison. For signed comparisons compare the
result against 1 in the biased case, and zero in the unbiased
case. For unsigned comparisons always compare against 1 after
biasing the unbased result by adding 1. This gives us a way to
biasing the unbiased result by adding 1. This gives us a way to
represent LTU. */
*px = result;
*pmode = word_mode;

2
gcc/rtl.h
View File

@ -361,7 +361,7 @@ struct rtvec_def GTY(()) {
/* Predicate yielding nonzero iff X is an rtx for a memory location. */
#define MEM_P(X) (GET_CODE (X) == MEM)
/* Prediacte yielding nonzero iff X is an rtx for a constant integer. */
/* Predicate yielding nonzero iff X is an rtx for a constant integer. */
#define CONST_INT_P(X) (GET_CODE (X) == CONST_INT)
/* Predicate yielding nonzero iff X is a label insn. */

4
gcc/sched-deps.c
View File

@ -227,7 +227,7 @@ sched_insns_conditions_mutex_p (rtx insn1, rtx insn2)
/* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the
LOG_LINKS of INSN, if it is not already there. DEP_TYPE indicates the
type of dependence that this link represents. DS, if non-zero,
type of dependence that this link represents. DS, if nonzero,
indicates speculations, through which this dependence can be overcome.
MEM1 and MEM2, if non-null, corresponds to memory locations in case of
data speculation. The function returns a value indicating if an old entry
@ -2187,7 +2187,7 @@ check_dep_status (enum reg_note dt, ds_t ds, bool relaxed_p)
gcc_assert ((ds & DEP_TYPES) == DEP_TRUE);
}
/* Check that true and anti depencies can't have other speculative
/* Check that true and anti dependencies can't have other speculative
statuses. */
if (ds & DEP_TRUE)
gcc_assert (ds & (BEGIN_DATA | BE_IN_SPEC));

16
gcc/sched-int.h
View File

@ -321,7 +321,7 @@ struct haifa_insn_data
(e.g. add_dependence was invoked with (insn == elem)). */
unsigned int has_internal_dep : 1;
/* What speculations are neccessary to apply to schedule the instruction. */
/* What speculations are necessary to apply to schedule the instruction. */
ds_t todo_spec;
/* What speculations were already applied. */
ds_t done_spec;
@ -359,7 +359,7 @@ extern regset *glat_start, *glat_end;
#define RECOVERY_BLOCK(INSN) (h_i_d[INSN_UID (INSN)].recovery_block)
#define ORIG_PAT(INSN) (h_i_d[INSN_UID (INSN)].orig_pat)
/* DEP_STATUS of the link incapsulates information, that is needed for
/* DEP_STATUS of the link encapsulates information, that is needed for
speculative scheduling. Namely, it is 4 integers in the range
[0, MAX_DEP_WEAK] and 3 bits.
The integers correspond to the probability of the dependence to *not*
@ -374,7 +374,7 @@ extern regset *glat_start, *glat_end;
to know just the major type of all the dependence between two instructions,
as only true dependence can be overcome.
There also is the 4-th bit in the DEP_STATUS (HARD_DEP), that is reserved
for using to describe instruction's status. It is set whenever instuction
for using to describe instruction's status. It is set whenever instruction
has at least one dependence, that cannot be overcome.
See also: check_dep_status () in sched-deps.c . */
#define DEP_STATUS(LINK) XINT (LINK, 2)
@ -421,27 +421,27 @@ enum SPEC_TYPES_OFFSETS {
/* The following defines provide numerous constants used to distinguish between
different types of speculative dependencies. */
/* Dependence can be overcomed with generation of new data speculative
/* Dependence can be overcome with generation of new data speculative
instruction. */
#define BEGIN_DATA (((ds_t) DEP_WEAK_MASK) << BEGIN_DATA_BITS_OFFSET)
/* This dependence is to the instruction in the recovery block, that was
formed to recover after data-speculation failure.
Thus, this dependence can overcomed with generating of the copy of
Thus, this dependence can overcome with generating of the copy of
this instruction in the recovery block. */
#define BE_IN_DATA (((ds_t) DEP_WEAK_MASK) << BE_IN_DATA_BITS_OFFSET)
/* Dependence can be overcomed with generation of new control speculative
/* Dependence can be overcome with generation of new control speculative
instruction. */
#define BEGIN_CONTROL (((ds_t) DEP_WEAK_MASK) << BEGIN_CONTROL_BITS_OFFSET)
/* This dependence is to the instruction in the recovery block, that was
formed to recover after control-speculation failure.
Thus, this dependence can overcomed with generating of the copy of
Thus, this dependence can be be overcome with generating of the copy of
this instruction in the recovery block. */
#define BE_IN_CONTROL (((ds_t) DEP_WEAK_MASK) << BE_IN_CONTROL_BITS_OFFSET)
/* Few convinient combinations. */
/* A few convenient combinations. */
#define BEGIN_SPEC (BEGIN_DATA | BEGIN_CONTROL)
#define DATA_SPEC (BEGIN_DATA | BE_IN_DATA)
#define CONTROL_SPEC (BEGIN_CONTROL | BE_IN_CONTROL)

12
gcc/sched-rgn.c
View File

@ -1146,7 +1146,7 @@ extend_rgns (int *degree, int *idxp, sbitmap header, int *loop_hdr)
(We don't count single block regions here).
By default we do at most 2 iterations.
This can be overriden with max-sched-extend-regions-iters parameter:
This can be overridden with max-sched-extend-regions-iters parameter:
0 - disable region extension,
N > 0 - do at most N iterations. */
@ -2038,7 +2038,7 @@ can_schedule_ready_p (rtx insn)
return 1;
}
/* Updates counter and other information. Splitted from can_schedule_ready_p ()
/* Updates counter and other information. Split from can_schedule_ready_p ()
because when we schedule insn speculatively then insn passed to
can_schedule_ready_p () differs from the one passed to
begin_schedule_ready (). */
@ -2752,7 +2752,7 @@ schedule_region (int rgn)
compute_dom_prob_ps (bb);
/* Cleanup ->aux used for EDGE_TO_BIT mapping. */
/* We don't need them anymore. But we want to avoid dublication of
/* We don't need them anymore. But we want to avoid duplication of
aux fields in the newly created edges. */
FOR_EACH_BB (block)
{
@ -2952,7 +2952,7 @@ schedule_insns (void)
init_regions ();
/* EBB_HEAD is a region-scope sctructure. But we realloc it for
/* EBB_HEAD is a region-scope structure. But we realloc it for
each region to save time/memory/something else. */
ebb_head = 0;
@ -2996,7 +2996,7 @@ schedule_insns (void)
liveness. */
for (rgn = 0; rgn < nr_regions; rgn++)
if (RGN_NR_BLOCKS (rgn) > 1
/* Or the only block of this region has been splitted. */
/* Or the only block of this region has been split. */
|| RGN_HAS_REAL_EBB (rgn)
/* New blocks (e.g. recovery blocks) should be processed
as parts of large regions. */
@ -3159,7 +3159,7 @@ add_block1 (basic_block bb, basic_block after)
/* ebb_head[i] - VALID. */
/* Source position: ebb_head[i]
Destination posistion: ebb_head[i] + 1
Destination position: ebb_head[i] + 1
Last position:
RGN_BLOCKS (nr_regions) - 1
Number of elements to copy: (last_position) - (source_position) + 1

4
gcc/tree-inline.h
View File

@ -64,10 +64,10 @@ typedef struct copy_body_data
int eh_region_offset;
/* We use the same mechanism do all sorts of different things. Rather
than enumerating the different cases, we categorize the behaviour
than enumerating the different cases, we categorize the behavior
in the various situations. */
/* Indicate the desired behaviour wrt call graph edges. We can either
/* Indicate the desired behavior wrt call graph edges. We can either
duplicate the edge (inlining, cloning), move the edge (versioning,
parallelization), or move the edges of the clones (saving). */
enum copy_body_cge_which {

6
gcc/tree-ssa-dom.c
View File

@ -2328,7 +2328,7 @@ propagate_rhs_into_lhs (tree stmt, tree lhs, tree rhs, bitmap interesting_names)
}
}
/* T is either a PHI node (potentally a degenerate PHI node) or
/* T is either a PHI node (potentially a degenerate PHI node) or
a statement that is a trivial copy or constant initialization.
Attempt to eliminate T by propagating its RHS into all uses of
@ -2446,7 +2446,7 @@ eliminate_degenerate_phis (void)
time behavior with bitmaps rather than sbitmaps. */
interesting_names = BITMAP_ALLOC (NULL);
/* First phase. Elimiante degenerate PHIs via a domiantor
/* First phase. Eliminate degenerate PHIs via a dominator
walk of the CFG.
Experiments have indicated that we generally get better
@ -2457,7 +2457,7 @@ eliminate_degenerate_phis (void)
calculate_dominance_info (CDI_DOMINATORS);
eliminate_degenerate_phis_1 (ENTRY_BLOCK_PTR, interesting_names);
/* Second phase. Eliminate second order degnerate PHIs as well
/* Second phase. Eliminate second order degenerate PHIs as well
as trivial copies or constant initializations identified by
the first phase or this phase. Basically we keep iterating
until our set of INTERESTING_NAMEs is empty. */

2
gcc/tree-ssa-loop-prefetch.c
View File

@ -810,7 +810,7 @@ anything_to_prefetch_p (struct mem_ref_group *groups)
/* Issue prefetches for the reference REF into loop as decided before.
HEAD is the number of iterations to prefetch ahead. UNROLL_FACTOR
is the factor by thet LOOP was unrolled. */
is the factor by which LOOP was unrolled. */
static void
issue_prefetch_ref (struct mem_ref *ref, unsigned unroll_factor, unsigned ahead)

6
gcc/tree-ssa-operands.c
View File

@ -412,7 +412,7 @@ set_virtual_use_link (use_operand_p ptr, tree stmt)
} while (0)
/* Initializes immediate use at USE_PTR to value VAL, and links it to the list
of immeditate uses. STMT is the current statement. */
of immediate uses. STMT is the current statement. */
#define INITIALIZE_USE(USE_PTR, VAL, STMT) \
do \
@ -492,7 +492,7 @@ add_mustdef_op (tree stmt, tree op, mustdef_optype_p *last)
}
/* Takes elements from build_defs and turns them into def operands of STMT.
TODO -- Given that def operands list is not neccessarily sorted, merging
TODO -- Given that def operands list is not necessarily sorted, merging
the operands this way does not make much sense.
-- Make build_defs VEC of tree *. */
@ -579,7 +579,7 @@ finalize_ssa_defs (tree stmt)
}
/* Takes elements from build_uses and turns them into use operands of STMT.
TODO -- Given that use operands list is not neccessarily sorted, merging
TODO -- Given that use operands list is not necessarily sorted, merging
the operands this way does not make much sense.
-- Make build_uses VEC of tree *. */

2
gcc/tree-vect-patterns.c
View File

@ -357,7 +357,7 @@ vect_recog_widen_mult_pattern (tree last_stmt ATTRIBUTE_UNUSED,
where type 'TYPE' is at least double the size of type 'type', i.e - we're
summing elements of type 'type' into an accumulator of type 'TYPE'. This is
a sepcial case of a reduction computation.
a special case of a reduction computation.
Input:

6
gcc/tree-vrp.c
View File

@ -1116,7 +1116,7 @@ extract_range_from_assert (value_range_t *vr_p, tree expr)
}
/* Case 3a, the anti-range extends into the low
part of the real range. Thus creating a new
low for the real reange. */
low for the real range. */
else if ((compare_values (anti_max, real_min) == 1
|| compare_values (anti_max, real_min) == 0)
&& compare_values (anti_max, real_max) == -1)
@ -1129,7 +1129,7 @@ extract_range_from_assert (value_range_t *vr_p, tree expr)
}
/* Case 3b, the anti-range extends into the high
part of the real range. Thus creating a new
higher for the real reange. */
higher for the real range. */
else if (compare_values (anti_min, real_min) == 1
&& (compare_values (anti_min, real_max) == -1
|| compare_values (anti_min, real_max) == 0))
@ -2981,7 +2981,7 @@ find_assert_locations (basic_block bb)
it, create a new assertion location node for OP. */
if (infer_value_range (stmt, op, &comp_code, &value))
{
/* If we are able to infer a non-zero value range for OP,
/* If we are able to infer a nonzero value range for OP,
then walk backwards through the use-def chain to see if OP
was set via a typecast.