[AArch64] Rewrite the vdup_lane intrinsics in C
gcc/ * config/aarch64/aarch64-simd-builtins.def (dup_lane_scalar): Remove. * config/aarch64/aarch64-simd.md (aarch64_simd_dup): Add 'w->w' alternative. (aarch64_dup_lane<mode>): Allow for VALL. (aarch64_dup_lane_scalar<mode>): Remove. (aarch64_dup_lane_<vswap_width_name><mode>): New. (aarch64_get_lane_signed<mode>): Add w->w altenative. (aarch64_get_lane_unsigned<mode>): Likewise. (aarch64_get_lane<mode>): Likewise. * config/aarch64/aarch64.c (aarch64_evpc_dup): New. (aarch64_expand_vec_perm_const_1): Use aarch64_evpc_dup. * config/aarch64/iterators.md (VSWAP_WIDTH): New. (VCON): Change container of V2SF. (vswap_width_name): Likewise. * config/aarch64/arm_neon.h (__aarch64_vdup_lane_any): New. (__aarch64_vdup<q>_lane<q>_<fpsu><8,16,32,64>): Likewise. (vdup<q>_n_<psuf><8,16,32,64>): Convert to C implementation. (vdup<q>_lane<q>_<fpsu><8,16,32,64>): Likewise. gcc/testsuite/ * gcc.target/aarch64/scalar_intrinsics.c (vdup<bhsd>_lane<su><8,16,32,64>): Force values to SIMD registers. From-SVN: r202180
This commit is contained in:
James Greenhalgh
James Greenhalgh
parent
d617d2d806
commit
91bd4114a7
@ -1,3 +1,26 @@
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2013-09-02 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-simd-builtins.def
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(dup_lane_scalar): Remove.
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* config/aarch64/aarch64-simd.md
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(aarch64_simd_dup): Add 'w->w' alternative.
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(aarch64_dup_lane<mode>): Allow for VALL.
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(aarch64_dup_lane_scalar<mode>): Remove.
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(aarch64_dup_lane_<vswap_width_name><mode>): New.
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(aarch64_get_lane_signed<mode>): Add w->w altenative.
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(aarch64_get_lane_unsigned<mode>): Likewise.
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(aarch64_get_lane<mode>): Likewise.
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* config/aarch64/aarch64.c (aarch64_evpc_dup): New.
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(aarch64_expand_vec_perm_const_1): Use aarch64_evpc_dup.
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* config/aarch64/iterators.md (VSWAP_WIDTH): New.
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(VCON): Change container of V2SF.
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(vswap_width_name): Likewise.
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* config/aarch64/arm_neon.h
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(__aarch64_vdup_lane_any): New.
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(__aarch64_vdup<q>_lane<q>_<fpsu><8,16,32,64>): Likewise.
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(vdup<q>_n_<psuf><8,16,32,64>): Convert to C implementation.
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(vdup<q>_lane<q>_<fpsu><8,16,32,64>): Likewise.
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2013-09-02 Eric Botcazou <ebotcazou@adacore.com>
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PR middle-end/56382
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@ -336,24 +336,13 @@
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})
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(define_insn "aarch64_simd_dup<mode>"
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[(set (match_operand:VDQ 0 "register_operand" "=w")
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(vec_duplicate:VDQ (match_operand:<VEL> 1 "register_operand" "r")))]
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[(set (match_operand:VDQ 0 "register_operand" "=w, w")
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(vec_duplicate:VDQ (match_operand:<VEL> 1 "register_operand" "r, w")))]
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"TARGET_SIMD"
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"dup\\t%0.<Vtype>, %<vw>1"
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[(set_attr "simd_type" "simd_dupgp")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "aarch64_dup_lane<mode>"
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(vec_duplicate:VDQ_I
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(vec_select:<VEL>
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(match_operand:<VCON> 1 "register_operand" "w")
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(parallel [(match_operand:SI 2 "immediate_operand" "i")])
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)))]
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"TARGET_SIMD"
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"dup\\t%<v>0<Vmtype>, %1.<Vetype>[%2]"
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[(set_attr "simd_type" "simd_dup")
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"@
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dup\\t%0.<Vtype>, %<vw>1
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dup\\t%0.<Vtype>, %1.<Vetype>[0]"
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[(set_attr "simd_type" "simd_dupgp, simd_dup")
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(set_attr "simd_mode" "<MODE>")]
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)
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@ -366,6 +355,32 @@
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "aarch64_dup_lane<mode>"
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[(set (match_operand:VALL 0 "register_operand" "=w")
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(vec_duplicate:VALL
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(vec_select:<VEL>
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(match_operand:VALL 1 "register_operand" "w")
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(parallel [(match_operand:SI 2 "immediate_operand" "i")])
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)))]
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"TARGET_SIMD"
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"dup\\t%0.<Vtype>, %1.<Vetype>[%2]"
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[(set_attr "simd_type" "simd_dup")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "aarch64_dup_lane_<vswap_width_name><mode>"
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[(set (match_operand:VALL 0 "register_operand" "=w")
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(vec_duplicate:VALL
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(vec_select:<VEL>
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(match_operand:<VSWAP_WIDTH> 1 "register_operand" "w")
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(parallel [(match_operand:SI 2 "immediate_operand" "i")])
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)))]
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"TARGET_SIMD"
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"dup\\t%0.<Vtype>, %1.<Vetype>[%2]"
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[(set_attr "simd_type" "simd_dup")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_simd_mov<mode>"
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[(set (match_operand:VD 0 "aarch64_simd_nonimmediate_operand"
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"=w, Utv, w, ?r, ?w, ?r, w")
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@ -7931,6 +7931,55 @@ aarch64_evpc_zip (struct expand_vec_perm_d *d)
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return true;
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}
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static bool
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aarch64_evpc_dup (struct expand_vec_perm_d *d)
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{
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rtx (*gen) (rtx, rtx, rtx);
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rtx out = d->target;
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rtx in0;
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enum machine_mode vmode = d->vmode;
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unsigned int i, elt, nelt = d->nelt;
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rtx lane;
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/* TODO: This may not be big-endian safe. */
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if (BYTES_BIG_ENDIAN)
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return false;
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elt = d->perm[0];
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for (i = 1; i < nelt; i++)
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{
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if (elt != d->perm[i])
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return false;
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}
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/* The generic preparation in aarch64_expand_vec_perm_const_1
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swaps the operand order and the permute indices if it finds
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d->perm[0] to be in the second operand. Thus, we can always
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use d->op0 and need not do any extra arithmetic to get the
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correct lane number. */
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in0 = d->op0;
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lane = GEN_INT (elt);
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switch (vmode)
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{
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case V16QImode: gen = gen_aarch64_dup_lanev16qi; break;
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case V8QImode: gen = gen_aarch64_dup_lanev8qi; break;
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case V8HImode: gen = gen_aarch64_dup_lanev8hi; break;
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case V4HImode: gen = gen_aarch64_dup_lanev4hi; break;
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case V4SImode: gen = gen_aarch64_dup_lanev4si; break;
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case V2SImode: gen = gen_aarch64_dup_lanev2si; break;
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case V2DImode: gen = gen_aarch64_dup_lanev2di; break;
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case V4SFmode: gen = gen_aarch64_dup_lanev4sf; break;
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case V2SFmode: gen = gen_aarch64_dup_lanev2sf; break;
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case V2DFmode: gen = gen_aarch64_dup_lanev2df; break;
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default:
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return false;
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}
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emit_insn (gen (out, in0, lane));
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return true;
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}
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static bool
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aarch64_evpc_tbl (struct expand_vec_perm_d *d)
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{
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@ -7988,6 +8037,8 @@ aarch64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
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return true;
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else if (aarch64_evpc_trn (d))
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return true;
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else if (aarch64_evpc_dup (d))
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return true;
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return aarch64_evpc_tbl (d);
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}
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return false;
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File diff suppressed because it is too large
Load Diff
@ -383,7 +383,7 @@
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(V4HI "V8HI") (V8HI "V8HI")
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(V2SI "V4SI") (V4SI "V4SI")
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(DI "V2DI") (V2DI "V2DI")
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(V2SF "V2SF") (V4SF "V4SF")
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(V2SF "V4SF") (V4SF "V4SF")
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(V2DF "V2DF") (SI "V4SI")
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(HI "V8HI") (QI "V16QI")])
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@ -527,6 +527,20 @@
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(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")])
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(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")])
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(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
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(V4HI "V8HI") (V8HI "V4HI")
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(V2SI "V4SI") (V4SI "V2SI")
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(DI "V2DI") (V2DI "DI")
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(V2SF "V4SF") (V4SF "V2SF")
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(DF "V2DF") (V2DF "DF")])
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(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
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(V4HI "to_128") (V8HI "to_64")
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(V2SI "to_128") (V4SI "to_64")
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(DI "to_128") (V2DI "to_64")
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(V2SF "to_128") (V4SF "to_64")
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(DF "to_128") (V2DF "to_64")])
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;; -------------------------------------------------------------------
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;; Code Iterators
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;; -------------------------------------------------------------------
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@ -1,3 +1,8 @@
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2013-09-02 James Greenhalgh <james.greenhalgh@arm.com>
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* gcc.target/aarch64/scalar_intrinsics.c
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(vdup<bhsd>_lane<su><8,16,32,64>): Force values to SIMD registers.
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2013-09-02 Richard Biener <rguenther@suse.de>
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PR middle-end/57511
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@ -198,13 +198,21 @@ test_vcltzd_s64 (int64x1_t a)
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int8x1_t
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test_vdupb_lane_s8 (int8x16_t a)
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{
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return vdupb_lane_s8 (a, 2);
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int8x1_t res;
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force_simd (a);
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res = vdupb_laneq_s8 (a, 2);
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force_simd (res);
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return res;
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}
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uint8x1_t
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test_vdupb_lane_u8 (uint8x16_t a)
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{
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return vdupb_lane_u8 (a, 2);
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uint8x1_t res;
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force_simd (a);
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res = vdupb_laneq_u8 (a, 2);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "aarch64_get_lanev8hi" 2 } } */
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@ -212,13 +220,21 @@ test_vdupb_lane_u8 (uint8x16_t a)
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int16x1_t
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test_vduph_lane_s16 (int16x8_t a)
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{
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return vduph_lane_s16 (a, 2);
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int16x1_t res;
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force_simd (a);
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res = vduph_laneq_s16 (a, 2);
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force_simd (res);
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return res;
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}
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uint16x1_t
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test_vduph_lane_u16 (uint16x8_t a)
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{
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return vduph_lane_u16 (a, 2);
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uint16x1_t res;
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force_simd (a);
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res = vduph_laneq_u16 (a, 2);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "aarch64_get_lanev4si" 2 } } */
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@ -226,13 +242,21 @@ test_vduph_lane_u16 (uint16x8_t a)
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int32x1_t
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test_vdups_lane_s32 (int32x4_t a)
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{
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return vdups_lane_s32 (a, 2);
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int32x1_t res;
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force_simd (a);
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res = vdups_laneq_s32 (a, 2);
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force_simd (res);
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return res;
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}
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uint32x1_t
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test_vdups_lane_u32 (uint32x4_t a)
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{
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return vdups_lane_u32 (a, 2);
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uint32x1_t res;
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force_simd (a);
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res = vdups_laneq_u32 (a, 2);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "aarch64_get_lanev2di" 2 } } */
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@ -240,13 +264,21 @@ test_vdups_lane_u32 (uint32x4_t a)
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int64x1_t
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test_vdupd_lane_s64 (int64x2_t a)
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{
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return vdupd_lane_s64 (a, 1);
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int64x1_t res;
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force_simd (a);
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res = vdupd_laneq_s64 (a, 1);
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force_simd (res);
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return res;
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}
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uint64x1_t
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test_vdupd_lane_u64 (uint64x2_t a)
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{
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return vdupd_lane_u64 (a, 1);
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uint64x1_t res;
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force_simd (a);
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res = vdupd_laneq_u64 (a, 1);
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force_simd (res);
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return res;
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}
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/* { dg-final { scan-assembler-times "\\tcmtst\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
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