re PR target/58314 (SH4 error: 'asm' operand requires impossible reload)
PR target/58314 PR target/50751 * config/sh/sh.c (max_mov_insn_displacement, disp_addr_displacement): Prefix function names with 'sh_'. Make them non-static. * config/sh/sh-protos.h (sh_disp_addr_displacement, sh_max_mov_insn_displacement): Add declarations. * config/sh/constraints.md (Q): Reject QImode. (Sdd): Use match_code "mem". (Snd): Fix erroneous matching of non-memory operands. * config/sh/predicates.md (short_displacement_mem_operand): New predicate. (general_movsrc_operand): Disallow PC relative QImode loads. * config/sh/sh.md (*mov<mode>_reg_reg): Remove it. (*movqi, *movhi): Merge both insns into... (*mov<mode>): ... this new insn. Replace generic 'm' constraints with 'Snd' and 'Sdd' constraints. Calculate insn length dynamically based on the operand types. From-SVN: r205390
This commit is contained in:
Oleg Endo
parent
8d590b9cb3
commit
91f65b12bb
@ -1,3 +1,23 @@
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2013-11-26 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/58314
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PR target/50751
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* config/sh/sh.c (max_mov_insn_displacement, disp_addr_displacement):
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Prefix function names with 'sh_'. Make them non-static.
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* config/sh/sh-protos.h (sh_disp_addr_displacement,
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sh_max_mov_insn_displacement): Add declarations.
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* config/sh/constraints.md (Q): Reject QImode.
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(Sdd): Use match_code "mem".
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(Snd): Fix erroneous matching of non-memory operands.
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* config/sh/predicates.md (short_displacement_mem_operand): New
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predicate.
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(general_movsrc_operand): Disallow PC relative QImode loads.
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* config/sh/sh.md (*mov<mode>_reg_reg): Remove it.
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(*movqi, *movhi): Merge both insns into...
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(*mov<mode>): ... this new insn. Replace generic 'm' constraints with
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'Snd' and 'Sdd' constraints. Calculate insn length dynamically based
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on the operand types.
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2013-11-26 Joern Rennecke <joern.rennecke@embecosm.com>
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* config/epiphany/epiphany.c (epiphany_expand_prologue):
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@ -221,6 +221,7 @@
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(define_constraint "Q"
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"A pc relative load operand."
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(and (match_code "mem")
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(match_test "GET_MODE (op) != QImode")
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(match_test "IS_PC_RELATIVE_LOAD_ADDR_P (XEXP (op, 0))")))
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(define_constraint "Bsc"
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@ -295,13 +296,15 @@
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(define_memory_constraint "Sdd"
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"A memory reference that uses displacement addressing."
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(and (match_test "MEM_P (op) && GET_CODE (XEXP (op, 0)) == PLUS")
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(and (match_code "mem")
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(match_test "GET_CODE (XEXP (op, 0)) == PLUS")
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(match_test "REG_P (XEXP (XEXP (op, 0), 0))")
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(match_test "CONST_INT_P (XEXP (XEXP (op, 0), 1))")))
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(define_memory_constraint "Snd"
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"A memory reference that excludes displacement addressing."
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(match_test "! satisfies_constraint_Sdd (op)"))
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(and (match_code "mem")
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(match_test "! satisfies_constraint_Sdd (op)")))
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(define_memory_constraint "Sbv"
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"A memory reference, as used in SH2A bclr.b, bset.b, etc."
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@ -421,6 +421,12 @@
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XEXP (XEXP (op, 0), 1),
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TARGET_SH2A, true)")))
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;; Returns true if OP is a displacement address that can fit into a
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;; 16 bit (non-SH2A) memory load / store insn.
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(define_predicate "short_displacement_mem_operand"
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(match_test "sh_disp_addr_displacement (op)
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<= sh_max_mov_insn_displacement (GET_MODE (op), false)"))
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;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn.
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(define_predicate "zero_extend_movu_operand"
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(and (match_operand 0 "displacement_mem_operand")
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@ -445,6 +451,11 @@
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if (t_reg_operand (op, mode))
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return 0;
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/* Disallow PC relative QImode loads, since these is no insn to do that
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and an imm8 load should be used instead. */
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if (IS_PC_RELATIVE_LOAD_ADDR_P (op) && GET_MODE (op) == QImode)
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return false;
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if (MEM_P (op))
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{
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rtx inside = XEXP (op, 0);
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@ -162,6 +162,8 @@ extern bool sh_vector_mode_supported_p (enum machine_mode);
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extern bool sh_cfun_trap_exit_p (void);
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extern rtx sh_find_equiv_gbr_addr (rtx cur_insn, rtx mem);
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extern int sh_eval_treg_value (rtx op);
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extern HOST_WIDE_INT sh_disp_addr_displacement (rtx mem_op);
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extern int sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a);
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/* Result value of sh_find_set_of_reg. */
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struct set_of_reg
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@ -316,9 +316,7 @@ static rtx sh_trampoline_adjust_address (rtx);
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static void sh_conditional_register_usage (void);
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static bool sh_legitimate_constant_p (enum machine_mode, rtx);
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static int mov_insn_size (enum machine_mode, bool);
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static int max_mov_insn_displacement (enum machine_mode, bool);
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static int mov_insn_alignment_mask (enum machine_mode, bool);
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static HOST_WIDE_INT disp_addr_displacement (rtx);
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static bool sequence_insn_p (rtx);
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static void sh_canonicalize_comparison (int *, rtx *, rtx *, bool);
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static void sh_canonicalize_comparison (enum rtx_code&, rtx&, rtx&,
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@ -3582,8 +3580,8 @@ mov_insn_size (enum machine_mode mode, bool consider_sh2a)
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/* Determine the maximum possible displacement for a move insn for the
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specified mode. */
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static int
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max_mov_insn_displacement (enum machine_mode mode, bool consider_sh2a)
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int
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sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a)
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{
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/* The 4 byte displacement move insns are the same as the 2 byte
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versions but take a 12 bit displacement. All we need to do is to
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@ -3619,8 +3617,8 @@ mov_insn_alignment_mask (enum machine_mode mode, bool consider_sh2a)
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}
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/* Return the displacement value of a displacement address. */
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static inline HOST_WIDE_INT
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disp_addr_displacement (rtx x)
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HOST_WIDE_INT
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sh_disp_addr_displacement (rtx x)
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{
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gcc_assert (satisfies_constraint_Sdd (x));
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return INTVAL (XEXP (XEXP (x, 0), 1));
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@ -3657,12 +3655,12 @@ sh_address_cost (rtx x, enum machine_mode mode,
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HImode and QImode loads/stores with displacement put pressure on
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R0 which will most likely require another reg copy. Thus account
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a higher cost for that. */
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if (offset > 0 && offset <= max_mov_insn_displacement (mode, false))
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if (offset > 0 && offset <= sh_max_mov_insn_displacement (mode, false))
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return (mode == HImode || mode == QImode) ? 2 : 1;
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/* The displacement would fit into a 4 byte move insn (SH2A). */
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if (TARGET_SH2A
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&& offset > 0 && offset <= max_mov_insn_displacement (mode, true))
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&& offset > 0 && offset <= sh_max_mov_insn_displacement (mode, true))
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return 2;
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/* The displacement is probably out of range and will require extra
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@ -10175,7 +10173,7 @@ sh_legitimate_index_p (enum machine_mode mode, rtx op, bool consider_sh2a,
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else
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{
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const HOST_WIDE_INT offset = INTVAL (op);
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const int max_disp = max_mov_insn_displacement (mode, consider_sh2a);
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const int max_disp = sh_max_mov_insn_displacement (mode, consider_sh2a);
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const int align_mask = mov_insn_alignment_mask (mode, consider_sh2a);
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/* If the mode does not support any displacement always return false.
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@ -10361,7 +10359,7 @@ sh_find_mov_disp_adjust (enum machine_mode mode, HOST_WIDE_INT offset)
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effectively disable the small displacement insns. */
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const int mode_sz = GET_MODE_SIZE (mode);
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const int mov_insn_sz = mov_insn_size (mode, false);
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const int max_disp = max_mov_insn_displacement (mode, false);
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const int max_disp = sh_max_mov_insn_displacement (mode, false);
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const int max_disp_next = max_disp + mov_insn_sz;
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HOST_WIDE_INT align_modifier = offset > 127 ? mov_insn_sz : 0;
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HOST_WIDE_INT offset_adjust;
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@ -13121,7 +13119,8 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
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the insns must have the appropriate alternatives. */
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if ((mode == QImode || mode == HImode) && rclass != R0_REGS
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&& satisfies_constraint_Sdd (x)
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&& disp_addr_displacement (x) <= max_mov_insn_displacement (mode, false))
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&& sh_disp_addr_displacement (x)
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<= sh_max_mov_insn_displacement (mode, false))
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return R0_REGS;
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/* When reload is trying to address a QImode or HImode subreg on the stack,
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@ -6993,34 +6993,9 @@ label:
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prepare_move_operands (operands, QImode);
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})
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;; If movqi_reg_reg is specified as an alternative of movqi, movqi will be
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;; selected to copy QImode regs. If one of them happens to be allocated
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;; on the stack, reload will stick to movqi insn and generate wrong
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;; displacement addressing because of the generic m alternatives.
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;; With the movqi_reg_reg being specified before movqi it will be initially
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;; picked to load/store regs. If the regs regs are on the stack reload
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;; try other insns and not stick to movqi_reg_reg, unless there were spilled
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;; pseudos in which case 'm' constraints pertain.
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;; The same applies to the movhi variants.
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;;
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;; Notice, that T bit is not allowed as a mov src operand here. This is to
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;; avoid things like (set (reg:QI) (subreg:QI (reg:SI T_REG) 0)), which
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;; introduces zero extensions after T bit stores and redundant reg copies.
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;;
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;; FIXME: We can't use 'arith_reg_operand' (which disallows T_REG) as a
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;; predicate for the mov src operand because reload will have trouble
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;; reloading MAC subregs otherwise. For that probably special patterns
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;; would be required.
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(define_insn "*mov<mode>_reg_reg"
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[(set (match_operand:QIHI 0 "arith_reg_dest" "=r,m,*z")
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(match_operand:QIHI 1 "register_operand" "r,*z,m"))]
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"TARGET_SH1 && !t_reg_operand (operands[1], VOIDmode)"
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"@
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mov %1,%0
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mov.<bw> %1,%0
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mov.<bw> %1,%0"
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[(set_attr "type" "move,store,load")])
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;; Specifying the displacement addressing load / store patterns separately
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;; before the generic movqi / movhi pattern allows controlling the order
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;; in which load / store insns are selected in a more fine grained way.
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;; FIXME: The non-SH2A and SH2A variants should be combined by adding
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;; "enabled" attribute as it is done in other targets.
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(define_insn "*mov<mode>_store_mem_disp04"
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@ -7070,38 +7045,44 @@ label:
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[(set_attr "type" "load")
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(set_attr "length" "2,2,4")])
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;; The m constraints basically allow any kind of addresses to be used with any
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;; source/target register as the other operand. This is not true for
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;; displacement addressing modes on anything but SH2A. That's why the
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;; specialized load/store insns are specified above.
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(define_insn "*movqi"
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[(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,l")
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(match_operand:QI 1 "general_movsrc_operand" "i,m,r,l,r"))]
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;; The order of the constraint alternatives is important here.
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;; Q/r has to come first, otherwise PC relative loads might wrongly get
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;; placed into delay slots. Since there is no QImode PC relative load, the
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;; Q constraint and general_movsrc_operand will reject it for QImode.
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;; The Snd alternatives should come before Sdd in order to avoid a preference
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;; of using r0 als the register operand for addressing modes other than
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;; displacement addressing.
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;; The Sdd alternatives allow only r0 as register operand, even though on
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;; SH2A any register could be allowed by switching to a 32 bit insn.
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;; Generally sticking to the r0 is preferrable, since it generates smaller
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;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.
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(define_insn "*mov<mode>"
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[(set (match_operand:QIHI 0 "general_movdst_operand"
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"=r,r,r,Snd,r, Sdd,z, r,l")
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(match_operand:QIHI 1 "general_movsrc_operand"
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"Q,r,i,r, Snd,z, Sdd,l,r"))]
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"TARGET_SH1
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&& (arith_reg_operand (operands[0], QImode)
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|| arith_reg_operand (operands[1], QImode))"
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&& (arith_reg_operand (operands[0], <MODE>mode)
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|| arith_reg_operand (operands[1], <MODE>mode))"
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"@
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mov.<bw> %1,%0
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mov %1,%0
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mov.b %1,%0
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mov.b %1,%0
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mov %1,%0
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mov.<bw> %1,%0
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mov.<bw> %1,%0
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mov.<bw> %1,%0
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mov.<bw> %1,%0
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sts %1,%0
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lds %1,%0"
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[(set_attr "type" "movi8,load,store,prget,prset")])
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(define_insn "*movhi"
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[(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,m,r,l")
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(match_operand:HI 1 "general_movsrc_operand" "Q,i,m,r,l,r"))]
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"TARGET_SH1
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&& (arith_reg_operand (operands[0], HImode)
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|| arith_reg_operand (operands[1], HImode))"
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"@
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mov.w %1,%0
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mov %1,%0
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mov.w %1,%0
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mov.w %1,%0
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sts %1,%0
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lds %1,%0"
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[(set_attr "type" "pcload,movi8,load,store,prget,prset")])
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[(set_attr "type" "pcload,move,movi8,store,load,store,load,prget,prset")
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(set (attr "length")
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(cond [(and (match_operand 0 "displacement_mem_operand")
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(not (match_operand 0 "short_displacement_mem_operand")))
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(const_int 4)
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(and (match_operand 1 "displacement_mem_operand")
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(not (match_operand 1 "short_displacement_mem_operand")))
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(const_int 4)]
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(const_int 2)))])
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(define_insn "*movqi_media"
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[(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
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