re PR target/54009 (incorrect code generated for DFmode lo_sum mem)
gcc/ PR target/54009 * config/rs6000/rs6000.c (mem_operand_gpr): Check that LO_SUM addresses won't wrap when offsetting. (rs6000_secondary_reload): Provide secondary reloads needed for wrapping LO_SUM addresses. gcc/testsuite/ PR target/54009 * gcc.target/powerpc/pr54009.c: New test. From-SVN: r195836
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Alan Modra
Alan Modra
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921f2deea4
@ -1,3 +1,11 @@
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2013-02-07 Alan Modra <amodra@gmail.com>
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PR target/54009
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* config/rs6000/rs6000.c (mem_operand_gpr): Check that LO_SUM
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addresses won't wrap when offsetting.
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(rs6000_secondary_reload): Provide secondary reloads needed for
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wrapping LO_SUM addresses.
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2013-02-06 Thomas Schwinge <thomas@codesourcery.com>
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* config/gnu.h (GNU_USER_TARGET_OS_CPP_BUILTINS): Never define
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@ -5135,17 +5135,14 @@ mem_operand_gpr (rtx op, enum machine_mode mode)
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if (TARGET_POWERPC64 && (offset & 3) != 0)
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return false;
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if (GET_CODE (addr) == LO_SUM)
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/* We know by alignment that ABI_AIX medium/large model toc refs
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will not cross a 32k boundary, since all entries in the
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constant pool are naturally aligned and we check alignment for
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other medium model toc-relative addresses. For ABI_V4 and
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ABI_DARWIN lo_sum addresses, we just check that 64-bit
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offsets are 4-byte aligned. */
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return true;
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extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
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gcc_assert (extra >= 0);
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if (GET_CODE (addr) == LO_SUM)
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/* For lo_sum addresses, we must allow any offset except one that
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causes a wrap, so test only the low 16 bits. */
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offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
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return offset + 0x8000 < 0x10000u - extra;
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}
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@ -13823,19 +13820,36 @@ rs6000_secondary_reload (bool in_p,
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&& MEM_P (x)
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&& GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
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{
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rtx off = address_offset (XEXP (x, 0));
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unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
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rtx addr = XEXP (x, 0);
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rtx off = address_offset (addr);
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if (off != NULL_RTX
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&& (INTVAL (off) & 3) != 0
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&& (unsigned HOST_WIDE_INT) INTVAL (off) + 0x8000 < 0x10000 - extra)
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if (off != NULL_RTX)
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{
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if (in_p)
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sri->icode = CODE_FOR_reload_di_load;
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unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
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unsigned HOST_WIDE_INT offset = INTVAL (off);
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/* We need a secondary reload when our legitimate_address_p
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says the address is good (as otherwise the entire address
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will be reloaded), and the offset is not a multiple of
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four or we have an address wrap. Address wrap will only
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occur for LO_SUMs since legitimate_offset_address_p
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rejects addresses for 16-byte mems that will wrap. */
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if (GET_CODE (addr) == LO_SUM
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? (1 /* legitimate_address_p allows any offset for lo_sum */
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&& ((offset & 3) != 0
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|| ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
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: (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
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&& (offset & 3) != 0))
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{
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if (in_p)
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sri->icode = CODE_FOR_reload_di_load;
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else
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sri->icode = CODE_FOR_reload_di_store;
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sri->extra_cost = 2;
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ret = NO_REGS;
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}
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else
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sri->icode = CODE_FOR_reload_di_store;
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sri->extra_cost = 2;
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ret = NO_REGS;
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default_p = true;
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}
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else
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default_p = true;
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@ -13845,25 +13859,43 @@ rs6000_secondary_reload (bool in_p,
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&& MEM_P (x)
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&& GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
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{
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rtx off = address_offset (XEXP (x, 0));
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unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
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rtx addr = XEXP (x, 0);
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rtx off = address_offset (addr);
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/* We need a secondary reload only when our legitimate_address_p
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says the address is good (as otherwise the entire address
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will be reloaded). So for mode sizes of 8 and 16 this will
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be when the offset is in the ranges [0x7ffc,0x7fff] and
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[0x7ff4,0x7ff7] respectively. Note that the address we see
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here may have been manipulated by legitimize_reload_address. */
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if (off != NULL_RTX
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&& ((unsigned HOST_WIDE_INT) INTVAL (off) - (0x8000 - extra)
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< UNITS_PER_WORD))
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if (off != NULL_RTX)
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{
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if (in_p)
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sri->icode = CODE_FOR_reload_si_load;
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unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
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unsigned HOST_WIDE_INT offset = INTVAL (off);
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/* We need a secondary reload when our legitimate_address_p
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says the address is good (as otherwise the entire address
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will be reloaded), and we have a wrap.
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legitimate_lo_sum_address_p allows LO_SUM addresses to
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have any offset so test for wrap in the low 16 bits.
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legitimate_offset_address_p checks for the range
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[-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
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for mode size of 16. We wrap at [0x7ffc,0x7fff] and
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[0x7ff4,0x7fff] respectively, so test for the
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intersection of these ranges, [0x7ffc,0x7fff] and
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[0x7ff4,0x7ff7] respectively.
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Note that the address we see here may have been
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manipulated by legitimize_reload_address. */
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if (GET_CODE (addr) == LO_SUM
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? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
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: offset - (0x8000 - extra) < UNITS_PER_WORD)
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{
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if (in_p)
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sri->icode = CODE_FOR_reload_si_load;
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else
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sri->icode = CODE_FOR_reload_si_store;
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sri->extra_cost = 2;
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ret = NO_REGS;
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}
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else
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sri->icode = CODE_FOR_reload_si_store;
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sri->extra_cost = 2;
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ret = NO_REGS;
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default_p = true;
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}
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else
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default_p = true;
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@ -1,5 +1,7 @@
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2013-02-07 Alan Modra <amodra@gmail.com>
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PR target/54009
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* gcc.target/powerpc/pr54009.c: New test.
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PR target/54131
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* gfortran.dg/pr54131.f: New test.
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43
gcc/testsuite/gcc.target/powerpc/pr54009.c
Normal file
43
gcc/testsuite/gcc.target/powerpc/pr54009.c
Normal file
@ -0,0 +1,43 @@
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/* { dg-do compile { target { powerpc*-*-* } } } */
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/* { dg-require-effective-target powerpc_fprs } */
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/* { dg-options "-O2" } */
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/* { dg-final { scan-assembler-not "\[\+\]32768" } } */
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/* -O2 -m32 store to x.d in w was
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lis 9,x+32764@ha
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stw 10,x+32764@l(9)
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stw 11,x+32768@l(9) <-- wrap! */
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struct big {
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char a[32764];
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double d __attribute__ ((aligned (4)));
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} __attribute__ ((packed));
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extern struct big x;
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double y;
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void r (void)
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{
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double tmp = x.d;
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#if 1
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asm ("#": "+r" (tmp)
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: : "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
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"fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
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"fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
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"fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31");
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#endif
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y = tmp;
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}
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void w (void)
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{
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double tmp = y;
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#if 1
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asm ("#": "+r" (tmp)
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: : "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
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"fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
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"fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
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"fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31");
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#endif
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x.d = tmp;
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}
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