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sync-cache.c (__aarch64_sync_cache_range): Cast the results of (dcache_lsize - 1) and (icache_lsize - 1) to the type... 

2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>

	* config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Cast the
	results of (dcache_lsize - 1) and (icache_lsize - 1) to the type
	__UINTPTR_TYPE__; also cast 'base' to the same type before the
	alignment operation.

From-SVN: r195266
This commit is contained in:
Yufeng Zhang 2013-01-17 14:27:36 +00:00 committed by Yufeng Zhang
parent 8222c37ede
commit 922c57d1ba
2 changed files with 11 additions and 2 deletions
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7
libgcc/ChangeLog
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@ -1,3 +1,10 @@
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Cast the
results of (dcache_lsize - 1) and (icache_lsize - 1) to the type
__UINTPTR_TYPE__; also cast 'base' to the same type before the
alignment operation.
2013-01-15 Sofiane Naci <sofiane.naci@arm.com>
* config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Update

6
libgcc/config/aarch64/sync-cache.c
View File

@ -40,7 +40,8 @@ __aarch64_sync_cache_range (const void *base, const void *end)
as per the GNU definition of __clear_cache. */
/* Make the start address of the loop cache aligned. */
address = (const char*) ((unsigned long) base & ~ (dcache_lsize - 1));
address = (const char*) ((__UINTPTR_TYPE__) base
& ~ (__UINTPTR_TYPE__) (dcache_lsize - 1));
for (address; address < (const char *) end; address += dcache_lsize)
asm volatile ("dc\tcvau, %0"
@ -51,7 +52,8 @@ __aarch64_sync_cache_range (const void *base, const void *end)
asm volatile ("dsb\tish" : : : "memory");
/* Make the start address of the loop cache aligned. */
address = (const char*) ((unsigned long) base & ~ (icache_lsize - 1));
address = (const char*) ((__UINTPTR_TYPE__) base
& ~ (__UINTPTR_TYPE__) (icache_lsize - 1));
for (address; address < (const char *) end; address += icache_lsize)
asm volatile ("ic\tivau, %0"