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Update sparc constraint comments and documentation.

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* config/sparc/constraints.md: Update unused letter list, move
	"w" near other memory constraints.  Remove no longer relevant
	comment.
	* doc/md.texi: Sync sparc constraint documentation with reality.

From-SVN: r192871
This commit is contained in:
David S. Miller 2012-10-27 02:57:50 +00:00 committed by David S. Miller
parent b8b15f9676
commit 923f9dedd6
3 changed files with 25 additions and 14 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2012-10-26 David S. Miller <davem@davemloft.net>
* config/sparc/constraints.md: Update unused letter list, move
"w" near other memory constraints. Remove no longer relevant
comment.
* doc/md.texi: Sync sparc constraint documentation with reality.
2012-10-26 DJ Delorie <dj@redhat.com>
* config/rl78/rl78.c (rl78_as_legitimate_address): Do not allow

14
gcc/config/sparc/constraints.md
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@ -18,7 +18,7 @@
;; <http://www.gnu.org/licenses/>.
;;; Unused letters:
;;; AB
;;; AB U
;;; a jkl q tuv xyz
@ -44,10 +44,6 @@
(define_register_constraint "h" "(TARGET_V9 && TARGET_V8PLUS ? I64_REGS : NO_REGS)"
"64-bit global or out register in V8+ mode")
(define_memory_constraint "w"
"A memory with only a base register"
(match_operand 0 "mem_noofs_operand"))
;; Floating-point constant constraints
(define_constraint "G"
@ -107,10 +103,6 @@
(and (match_code "const_int")
(match_test "ival == -1")))
;; Extra constraints
;; Our memory extra constraints have to emulate the behavior of 'm' and 'o',
;; i.e. accept pseudo-registers during reload.
(define_constraint "D"
"const_vector"
(and (match_code "const_vector")
@ -144,6 +136,10 @@
(and (match_code "mem")
(match_test "memory_ok_for_ldd (op)")))
(define_memory_constraint "w"
"A memory with only a base register"
(match_operand 0 "mem_noofs_operand"))
(define_constraint "Y"
"The vector zero constant"
(and (match_code "const_vector")

18
gcc/doc/md.texi
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@ -3219,6 +3219,9 @@ when the Visual Instruction Set is available.
@item h
64-bit global or out register for the SPARC-V8+ architecture.
@item C
The constant all-ones, for floating-point.
@item D
A vector constant
@ -3233,10 +3236,12 @@ Zero
loaded with the @code{sethi} instruction)
@item L
A constant in the range supported by @code{movcc} instructions
A constant in the range supported by @code{movcc} instructions (11-bit
signed immediate)
@item M
A constant in the range supported by @code{movrcc} instructions
A constant in the range supported by @code{movrcc} instructions (10-bit
signed immediate)
@item N
Same as @samp{K}, except that it verifies that bits that are not in the
@ -3252,6 +3257,9 @@ Floating-point zero
@item H
Signed 13-bit constant, sign-extended to 32 or 64 bits
@item P
The constant -1
@item Q
Floating-point constant whose integral representation can
be moved into an integer register using a single sethi
@ -3270,12 +3278,12 @@ instruction sequence
@item T
Memory address aligned to an 8-byte boundary
@item U
Even register
@item W
Memory address for @samp{e} constraint registers
@item w
Memory address with only a base register
@item Y
Vector zero