re PR target/84899 (ICE: in final_scan_insn_1, at final.c:3139 (error: could not split insn))

PR target/84899
	* postreload.c (reload_combine_recognize_pattern): Perform
	INTVAL addition in unsigned HOST_WIDE_INT type to avoid UB and
	truncate_int_for_mode the result for the destination's mode.

	* gcc.dg/pr84899.c: New test.

From-SVN: r258610
This commit is contained in:
Jakub Jelinek 2018-03-16 22:01:16 +01:00 committed by Jakub Jelinek
parent ce811fc49b
commit 927fb0bc9b
4 changed files with 29 additions and 5 deletions

View File

@ -1,5 +1,10 @@
2018-03-16 Jakub Jelinek <jakub@redhat.com>
PR target/84899
* postreload.c (reload_combine_recognize_pattern): Perform
INTVAL addition in unsigned HOST_WIDE_INT type to avoid UB and
truncate_int_for_mode the result for the destination's mode.
PR c/84909
* hsa-gen.c (mem_type_for_type): Fix comment typo.
* tree-vect-loop-manip.c (vect_create_cond_for_niters_checks):

View File

@ -1157,11 +1157,13 @@ reload_combine_recognize_pattern (rtx_insn *insn)
value in PREV, the constant loading instruction. */
validate_change (prev, &SET_DEST (prev_set), index_reg, 1);
if (reg_state[regno].offset != const0_rtx)
validate_change (prev,
&SET_SRC (prev_set),
GEN_INT (INTVAL (SET_SRC (prev_set))
+ INTVAL (reg_state[regno].offset)),
1);
{
HOST_WIDE_INT c
= trunc_int_for_mode (UINTVAL (SET_SRC (prev_set))
+ UINTVAL (reg_state[regno].offset),
GET_MODE (index_reg));
validate_change (prev, &SET_SRC (prev_set), GEN_INT (c), 1);
}
/* Now for every use of REG that we have recorded, replace REG
with REG_SUM. */

View File

@ -1,3 +1,8 @@
2018-03-16 Jakub Jelinek <jakub@redhat.com>
PR target/84899
* gcc.dg/pr84899.c: New test.
2018-03-16 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/69395

View File

@ -0,0 +1,12 @@
/* PR target/84899 */
/* { dg-do compile } */
/* { dg-options "-O -funroll-all-loops -fno-move-loop-invariants" } */
void
foo (int x)
{
int a = 1 / x, b = 0;
while ((a + b + 1) < x)
b = __INT_MAX__;
}