mips.md (divide_condition): New mode attribute.
* config/mips/mips.md (divide_condition): New mode attribute. (div[sd]f3, *div[sd]f3): Use it. Redefine using :SCALARF. (sqrt[sd]f3): Redefine using SCALARF. (*recip[sd]f3, *rsqrt<mode>[ab]): Likewise. Name formerly unnamed patterns. From-SVN: r86721
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
aae0609ca9
commit
93898c8bc4
@ -1,3 +1,11 @@
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2004-08-29 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.md (divide_condition): New mode attribute.
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(div[sd]f3, *div[sd]f3): Use it. Redefine using :SCALARF.
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(sqrt[sd]f3): Redefine using SCALARF.
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(*recip[sd]f3, *rsqrt<mode>[ab]): Likewise. Name formerly unnamed
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patterns.
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2004-08-29 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.md (ANYF, SCALARF): New mode macros.
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@ -399,6 +399,16 @@
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;; floating-point mode.
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(define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
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;; This attribute works around the early SB-1 rev2 core "F2" erratum:
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;;
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;; In certain cases, div.s and div.ps may have a rounding error
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;; and/or wrong inexact flag.
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;;
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;; Therefore, we only allow div.s if not working around SB-1 rev2
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;; errata or if a slight loss of precision is OK.
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(define_mode_attr divide_condition
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[DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")])
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;; This code macro allows all branch instructions to be generated from
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;; a single define_expand template.
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(define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
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@ -1705,18 +1715,18 @@
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;; ....................
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;;
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(define_expand "divdf3"
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[(set (match_operand:DF 0 "register_operand")
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(div:DF (match_operand:DF 1 "reg_or_1_operand")
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(match_operand:DF 2 "register_operand")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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(define_expand "div<mode>3"
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[(set (match_operand:SCALARF 0 "register_operand")
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(div:SCALARF (match_operand:SCALARF 1 "reg_or_1_operand")
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(match_operand:SCALARF 2 "register_operand")))]
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"<divide_condition>"
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{
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if (const_1_operand (operands[1], DFmode))
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if (const_1_operand (operands[1], <MODE>mode))
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if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
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operands[1] = force_reg (DFmode, operands[1]);
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operands[1] = force_reg (<MODE>mode, operands[1]);
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})
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;; This pattern works around the early SB-1 rev2 core "F1" erratum:
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;; These patterns work around the early SB-1 rev2 core "F1" erratum:
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;;
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;; If an mfc1 or dmfc1 happens to access the floating point register
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;; file at the same time a long latency operation (div, sqrt, recip,
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@ -1728,102 +1738,37 @@
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;; The workaround is to insert an unconditional 'mov' from/to the
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;; long latency op destination register.
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(define_insn "*divdf3"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(div:DF (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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(define_insn "*div<mode>3"
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[(set (match_operand:SCALARF 0 "register_operand" "=f")
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(div:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
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(match_operand:SCALARF 2 "register_operand" "f")))]
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"<divide_condition>"
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{
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if (TARGET_FIX_SB1)
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return "div.d\t%0,%1,%2\;mov.d\t%0,%0";
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return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
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else
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return "div.d\t%0,%1,%2";
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return "div.<fmt>\t%0,%1,%2";
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}
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[(set_attr "type" "fdiv")
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(set_attr "mode" "DF")
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(set_attr "mode" "<MODE>")
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(set (attr "length")
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(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
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(const_int 8)
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(const_int 4)))])
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;; This pattern works around the early SB-1 rev2 core "F2" erratum:
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;;
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;; In certain cases, div.s and div.ps may have a rounding error
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;; and/or wrong inexact flag.
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;;
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;; Therefore, we only allow div.s if not working around SB-1 rev2
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;; errata, or if working around those errata and a slight loss of
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;; precision is OK (i.e., flag_unsafe_math_optimizations is set).
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(define_expand "divsf3"
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[(set (match_operand:SF 0 "register_operand")
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(div:SF (match_operand:SF 1 "reg_or_1_operand")
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(match_operand:SF 2 "register_operand")))]
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"TARGET_HARD_FLOAT && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)"
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{
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if (const_1_operand (operands[1], SFmode))
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if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
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operands[1] = force_reg (SFmode, operands[1]);
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})
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;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
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;; "divdf3" comment for details).
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;;
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;; This pattern works around the early SB-1 rev2 core "F2" erratum (see
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;; "divsf3" comment for details).
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(define_insn "*divsf3"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(div:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)"
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(define_insn "*recip<mode>3"
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[(set (match_operand:SCALARF 0 "register_operand" "=f")
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(div:SCALARF (match_operand:SCALARF 1 "const_1_operand" "")
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(match_operand:SCALARF 2 "register_operand" "f")))]
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"ISA_HAS_FP4 && flag_unsafe_math_optimizations"
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{
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if (TARGET_FIX_SB1)
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return "div.s\t%0,%1,%2\;mov.s\t%0,%0";
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return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
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else
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return "div.s\t%0,%1,%2";
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}
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[(set_attr "type" "fdiv")
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(set_attr "mode" "SF")
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(set (attr "length")
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(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
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(const_int 8)
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(const_int 4)))])
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;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
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;; "divdf3" comment for details).
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=f")
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(div:DF (match_operand:DF 1 "const_1_operand" "")
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(match_operand:DF 2 "register_operand" "f")))]
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
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{
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if (TARGET_FIX_SB1)
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return "recip.d\t%0,%2\;mov.d\t%0,%0";
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else
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return "recip.d\t%0,%2";
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return "recip.<fmt>\t%0,%2";
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}
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[(set_attr "type" "frdiv")
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(set_attr "mode" "DF")
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(set (attr "length")
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(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
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(const_int 8)
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(const_int 4)))])
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;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
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;; "divdf3" comment for details).
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(define_insn ""
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[(set (match_operand:SF 0 "register_operand" "=f")
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(div:SF (match_operand:SF 1 "const_1_operand" "")
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(match_operand:SF 2 "register_operand" "f")))]
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
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{
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if (TARGET_FIX_SB1)
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return "recip.s\t%0,%2\;mov.s\t%0,%0";
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else
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return "recip.s\t%0,%2";
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}
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[(set_attr "type" "frdiv")
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(set_attr "mode" "SF")
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(set_attr "mode" "<MODE>")
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(set (attr "length")
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(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
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(const_int 8)
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@ -1862,119 +1807,59 @@
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;;
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;; ....................
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;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
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;; "divdf3" comment for details).
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(define_insn "sqrtdf2"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && HAVE_SQRT_P() && TARGET_DOUBLE_FLOAT"
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;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
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;; "*div[sd]f3" comment for details).
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(define_insn "sqrt<mode>2"
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[(set (match_operand:SCALARF 0 "register_operand" "=f")
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(sqrt:SCALARF (match_operand:SCALARF 1 "register_operand" "f")))]
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"HAVE_SQRT_P()"
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{
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if (TARGET_FIX_SB1)
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return "sqrt.d\t%0,%1\;mov.d\t%0,%0";
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return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
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else
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return "sqrt.d\t%0,%1";
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return "sqrt.<fmt>\t%0,%1";
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}
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[(set_attr "type" "fsqrt")
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(set_attr "mode" "DF")
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(set_attr "mode" "<MODE>")
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(set (attr "length")
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(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
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(const_int 8)
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(const_int 4)))])
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;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
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;; "divdf3" comment for details).
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(define_insn "sqrtsf2"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && HAVE_SQRT_P()"
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(define_insn "*rsqrt<mode>a"
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[(set (match_operand:SCALARF 0 "register_operand" "=f")
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(div:SCALARF
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(match_operand:SCALARF 1 "const_1_operand" "")
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(sqrt:SCALARF (match_operand:SCALARF 2 "register_operand" "f"))))]
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"ISA_HAS_FP4 && flag_unsafe_math_optimizations"
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{
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if (TARGET_FIX_SB1)
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return "sqrt.s\t%0,%1\;mov.s\t%0,%0";
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return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
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else
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return "sqrt.s\t%0,%1";
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}
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[(set_attr "type" "fsqrt")
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(set_attr "mode" "SF")
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(set (attr "length")
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(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
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(const_int 8)
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(const_int 4)))])
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;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
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;; "divdf3" comment for details).
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=f")
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(div:DF (match_operand:DF 1 "const_1_operand" "")
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(sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
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{
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if (TARGET_FIX_SB1)
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return "rsqrt.d\t%0,%2\;mov.d\t%0,%0";
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else
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return "rsqrt.d\t%0,%2";
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return "rsqrt.<fmt>\t%0,%2";
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}
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[(set_attr "type" "frsqrt")
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(set_attr "mode" "DF")
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(set_attr "mode" "<MODE>")
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(set (attr "length")
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(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
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(const_int 8)
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(const_int 4)))])
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;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
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;; "divdf3" comment for details).
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(define_insn ""
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[(set (match_operand:SF 0 "register_operand" "=f")
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(div:SF (match_operand:SF 1 "const_1_operand" "")
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(sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
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(define_insn "*rsqrt<mode>b"
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[(set (match_operand:SCALARF 0 "register_operand" "=f")
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(sqrt:SCALARF
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(div:SCALARF (match_operand:SCALARF 1 "const_1_operand" "")
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(match_operand:SCALARF 2 "register_operand" "f"))))]
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"ISA_HAS_FP4 && flag_unsafe_math_optimizations"
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{
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if (TARGET_FIX_SB1)
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return "rsqrt.s\t%0,%2\;mov.s\t%0,%0";
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return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
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else
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return "rsqrt.s\t%0,%2";
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return "rsqrt.<fmt>\t%0,%2";
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}
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[(set_attr "type" "frsqrt")
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(set_attr "mode" "SF")
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(set (attr "length")
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(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
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(const_int 8)
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(const_int 4)))])
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;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
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;; "divdf3" comment for details).
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=f")
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(sqrt:DF (div:DF (match_operand:DF 1 "const_1_operand" "")
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(match_operand:DF 2 "register_operand" "f"))))]
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
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{
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if (TARGET_FIX_SB1)
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return "rsqrt.d\t%0,%2\;mov.d\t%0,%0";
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else
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return "rsqrt.d\t%0,%2";
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}
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[(set_attr "type" "frsqrt")
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(set_attr "mode" "DF")
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(set (attr "length")
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(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
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(const_int 8)
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(const_int 4)))])
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;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
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;; "divdf3" comment for details).
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(define_insn ""
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[(set (match_operand:SF 0 "register_operand" "=f")
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(sqrt:SF (div:SF (match_operand:SF 1 "const_1_operand" "")
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(match_operand:SF 2 "register_operand" "f"))))]
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
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{
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if (TARGET_FIX_SB1)
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return "rsqrt.s\t%0,%2\;mov.s\t%0,%0";
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else
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return "rsqrt.s\t%0,%2";
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}
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[(set_attr "type" "frsqrt")
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(set_attr "mode" "SF")
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(set_attr "mode" "<MODE>")
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(set (attr "length")
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(if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
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(const_int 8)
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