invoke.texi (Score Options): New section.
* doc/invoke.texi (Score Options): New section. * doc/md.texi (Score family): New section to document constraints. * config/score/t-score-elf: Fix spelling typo. * config/score/score.c: Add TARGET_DEFAULT_TARGET_FLAGS macro. * config/score/score.h: Fix spelling typo. * config/score/score-mdaux.c: Remove TARGET_NOPINDEX condition. * config/score/score.opt: Remove -mnpi -mnuls -mSCORE5/5U -mSCORE7 options. From-SVN: r117882
This commit is contained in:
parent
afc0a4ba17
commit
93ef7c1f7e
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@ -7,10 +7,6 @@
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* config.guess: Import latest version.
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* config.guess: Import latest version.
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* config.sub: Likewise.
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* config.sub: Likewise.
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2006-10-16 Tan Shengguo <shengguo@sunnorth.com.cn>
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* MAINTAINERS: Add Tan Shengguo as score port maintainer.
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2006-10-10 Brooks Moses <bmoses@stanford.edu>
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2006-10-10 Brooks Moses <bmoses@stanford.edu>
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* Makefile.def: Added pdf target handling.
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* Makefile.def: Added pdf target handling.
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@ -75,6 +75,7 @@ rs6000 port David Edelsohn dje@watson.ibm.com
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rs6000 vector extns Aldy Hernandez aldyh@redhat.com
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rs6000 vector extns Aldy Hernandez aldyh@redhat.com
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s390 port Hartmut Penner hpenner@de.ibm.com
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s390 port Hartmut Penner hpenner@de.ibm.com
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s390 port Ulrich Weigand uweigand@de.ibm.com
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s390 port Ulrich Weigand uweigand@de.ibm.com
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score port Chen Liqin liqin@sunnorth.com.cn
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sh port Joern Rennecke joern.rennecke@st.com
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sh port Joern Rennecke joern.rennecke@st.com
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sh port Alexandre Oliva aoliva@redhat.com
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sh port Alexandre Oliva aoliva@redhat.com
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sh libraries/configury Kaz Kojima kkojima@gcc.gnu.org
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sh libraries/configury Kaz Kojima kkojima@gcc.gnu.org
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@ -1,3 +1,28 @@
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2006-10-19 Chen Liqin <liqin@sunnorth.com.cn>
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* config/score/crti.asm: New file.
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* config/score/crtn.asm: New file.
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* config/score/elf.h: New file.
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* config/score/mac.md: New file.
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* config/score/misc.md: New file.
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* config/score/mul-div.S: New file.
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* config/score/predicates.md: New file.
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* config/score/score7.md: New file.
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* config/score/score.c: New file.
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* config/score/score-conv.h: New file.
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* config/score/score.h: New file.
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* config/score/score.md: New file.
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* config/score/score-mdaux.c: New file.
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* config/score/score-mdaux.h: New file.
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* config/score/score-modes.def: New file.
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* config/score/score.opt: New file.
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* config/score/score-protos.h: New file.
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* config/score/score-version.h: New file.
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* config/score/t-score-elf: New file.
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* config.gcc: Add score*-*-* configurations(Update before).
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* doc/invoke.texi (Score Options): New section.
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* doc/md.texi (Score family): New section to document constraints.
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2006-10-19 Nick Clifton <nickc@redhat.com>
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2006-10-19 Nick Clifton <nickc@redhat.com>
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* config/arm/arm.c: Fix spelling typo.
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* config/arm/arm.c: Fix spelling typo.
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@ -397,7 +397,7 @@ mda_classify_address (struct score_address_info *info,
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case POST_DEC:
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case POST_DEC:
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case PRE_INC:
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case PRE_INC:
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case POST_INC:
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case POST_INC:
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if (TARGET_NOPINDEX || GET_MODE_SIZE (mode) > GET_MODE_SIZE (SImode))
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if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (SImode))
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return false;
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return false;
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info->type = ADD_REG;
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info->type = ADD_REG;
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info->reg = XEXP (x, 0);
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info->reg = XEXP (x, 0);
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@ -126,6 +126,9 @@ static bool score_rtx_costs (rtx, int, int, int *);
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#undef TARGET_RTX_COSTS
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#undef TARGET_RTX_COSTS
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#define TARGET_RTX_COSTS score_rtx_costs
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#define TARGET_RTX_COSTS score_rtx_costs
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#undef TARGET_DEFAULT_TARGET_FLAGS
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#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
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/* Implement TARGET_RETURN_IN_MEMORY. In S+core,
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/* Implement TARGET_RETURN_IN_MEMORY. In S+core,
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small structures are returned in a register.
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small structures are returned in a register.
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Objects with varying size must still be returned in memory. */
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Objects with varying size must still be returned in memory. */
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@ -37,7 +37,7 @@ extern GTY(()) rtx cmp_op1;
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#undef ASM_SPEC
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#undef ASM_SPEC
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#define ASM_SPEC \
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#define ASM_SPEC \
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"%{!mel:-EB} %{mel:-EL} %{mSCORE5U:-SCORE5U} %{mSCORE7:-SCORE7} %{G*}"
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"%{!mel:-EB} %{mel:-EL} %{mscore5u:-SCORE5U} %{mscore7:-SCORE7} %{G*}"
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#undef LINK_SPEC
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#undef LINK_SPEC
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#define LINK_SPEC "%{!mel:-EB} %{mel:-EL} %{G*}"
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#define LINK_SPEC "%{!mel:-EB} %{mel:-EL} %{G*}"
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@ -207,10 +207,10 @@ extern GTY(()) rtx cmp_op1;
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but Control register have 32 registers, cr16-cr31. */
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but Control register have 32 registers, cr16-cr31. */
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#define FIXED_REGISTERS \
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#define FIXED_REGISTERS \
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{ \
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{ \
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/* General Purpose Registers */ \
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/* General Purpose Registers */ \
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1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, \
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/* Control Registers */ \
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/* Control Registers */ \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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/* CEH/ CEL/ CNT/ LCR/ SCR / ARG_POINTER_REGNUM/ FRAME_POINTER_REGNUM */\
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/* CEH/ CEL/ CNT/ LCR/ SCR / ARG_POINTER_REGNUM/ FRAME_POINTER_REGNUM */\
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0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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/* CP 2 Registers */ \
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/* CP 2 Registers */ \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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/* CP 3 Registers*/ \
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/* CP 3 Registers */ \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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}
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}
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#define CALL_USED_REGISTERS \
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#define CALL_USED_REGISTERS \
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{ \
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{ \
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/* General purpose register */ \
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/* General purpose register */ \
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1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
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1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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/* Control Registers */ \
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/* Control Registers */ \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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/* CP 1 Registers */ \
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/* CP 1 Registers */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000}, \
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{ 0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000}, \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffffff}, \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffffff}, \
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{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff}, \
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{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff}, \
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/* ALL_REGS */ \
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/* ALL_REGS */ \
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{ 0xffffffff, 0x001fffff, 0xffffffff, 0xffffffff, 0xffffffff}, \
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{ 0xffffffff, 0x001fffff, 0xffffffff, 0xffffffff, 0xffffffff}, \
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}
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}
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@ -27,27 +27,15 @@ mel
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Target RejectNegative Report Mask(LITTLE_ENDIAN)
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Target RejectNegative Report Mask(LITTLE_ENDIAN)
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Generate little-endian code
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Generate little-endian code
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mnpi
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Target RejectNegative Report Mask(NOPINDEX)
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Do not use pre/post index
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mnuls
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Target RejectNegative Report Mask(NOUNALIGNED)
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Do not use unaligned load/store
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mmac
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mmac
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Target RejectNegative Report Mask(MAC)
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Target RejectNegative Report Mask(MAC)
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Enable mac instruction
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Enable mac instruction
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mSCORE5
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mscore5u
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Target RejectNegative Report Mask(SCORE5)
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Support SCORE 5 ISA
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mSCORE5U
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Target RejectNegative Report Mask(SCORE5U)
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Target RejectNegative Report Mask(SCORE5U)
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Support SCORE 5U ISA
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Support SCORE 5U ISA
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mSCORE7
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mscore7
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Target RejectNegative Report Mask(SCORE7)
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Target RejectNegative Report Mask(SCORE7)
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Support SCORE 7 ISA
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Support SCORE 7 ISA
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@ -35,7 +35,7 @@ dp-bit.c: $(srcdir)/config/fp-bit.c
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# without the $gp register.
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# without the $gp register.
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TARGET_LIBGCC2_CFLAGS = -G 0
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TARGET_LIBGCC2_CFLAGS = -G 0
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MULTILIB_OPTIONS = fPIC mel mSCORE7
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MULTILIB_OPTIONS = fPIC mel mscore7
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MULTILIB_MATCHES = fPIC=fpic
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MULTILIB_MATCHES = fPIC=fpic
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EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
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EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
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@ -694,6 +694,11 @@ See RS/6000 and PowerPC Options.
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-mtpf-trace -mno-tpf-trace -mfused-madd -mno-fused-madd @gol
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-mtpf-trace -mno-tpf-trace -mfused-madd -mno-fused-madd @gol
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-mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard}
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-mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard}
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@emph{Score Options}
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@gccoptlist{-mel -mel @gol
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-mmac @gol
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-mscore5u -mscore7}
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@emph{SH Options}
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@emph{SH Options}
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@gccoptlist{-m1 -m2 -m2e -m3 -m3e @gol
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@gccoptlist{-m1 -m2 -m2e -m3 -m3e @gol
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-m4-nofpu -m4-single-only -m4-single -m4 @gol
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-m4-nofpu -m4-single-only -m4-single -m4 @gol
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@ -7319,6 +7324,7 @@ platform.
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* PowerPC Options::
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* PowerPC Options::
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* RS/6000 and PowerPC Options::
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* RS/6000 and PowerPC Options::
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* S/390 and zSeries Options::
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* S/390 and zSeries Options::
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* Score Options::
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* SH Options::
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* SH Options::
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* SPARC Options::
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* SPARC Options::
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* System V Options::
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* System V Options::
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@ -12162,6 +12168,34 @@ In order to be efficient the extra code makes the assumption that the stack star
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at an address aligned to the value given by @var{stack-size}.
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at an address aligned to the value given by @var{stack-size}.
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@end table
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@end table
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@node Score Options
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@subsection Score Options
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@cindex Score Options
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These options are defined for Score implementations:
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@table @gcctabopt
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@item -mel
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@opindex -mel
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Compile code for little endian mode.
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@item -meb
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@opindex meb
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Compile code for big endian mode. This is the default.
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@item -mmac
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@opindex mmac
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Enable the use of multiply-accumulate instructions. Disabled by default.
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@item -mscore5u
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@opindex mscore5u
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Specify the SCORE5U of the target architecture.
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@item -mscore7
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@opindex mscore7
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Specify the SCORE7 of the target architecture. This is the default.
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@end table
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@node SH Options
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@node SH Options
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@subsection SH Options
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@subsection SH Options
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@ -2766,6 +2766,87 @@ Shift count operand.
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@end table
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@end table
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@item Score family---@file{config/score/score.h}
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@table @code
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@item d
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Registers from r0 to r32.
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@item e
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Registers from r0 to r16.
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@item t
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r8---r11 or r22---r27 registers.
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@item h
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hi register.
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@item l
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lo register.
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@item x
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hi + lo register.
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@item q
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cnt register.
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@item y
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lcb register.
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@item z
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scb register.
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@item a
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cnt + lcb + scb register.
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@item c
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cr0---cr15 register.
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@item b
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cp1 registers.
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@item f
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cp2 registers.
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@item i
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cp3 registers.
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@item j
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cp1 + cp2 + cp3 registers.
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@item I
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Unsigned 15 bit integer (in the range 0 to 32767).
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@item J
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Unsigned 5 bit integer (in the range 0 to 31).
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@item K
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Unsigned 16 bit integer (in the range 0 to 65535).
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@item L
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Signed 16 bit integer (in the range @minus{}32768 to 32767).
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@item M
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Unsigned 14 bit integer (in the range 0 to 16383).
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@item N
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Signed 14 bit integer (in the range @minus{}8192 to 8191).
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@item O
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Signed 15 bit integer (in the range @minus{}16384 to 16383).
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@item P
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Signed 12 bit integer (in the range @minus{}2048 to 2047).
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@item J
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An integer constant with exactly a single bit set.
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@item Q
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An integer constant.
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@item Z
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Any SYMBOL_REF.
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@end table
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@item Xstormy16---@file{config/stormy16/stormy16.h}
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@item Xstormy16---@file{config/stormy16/stormy16.h}
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@table @code
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@table @code
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@item a
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@item a
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Loading…
Reference in New Issue