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rs6000.md (define_attr "type"): Add two and three.

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* config/rs6000/rs6000.md (define_attr "type"): Add two and three.
        Change multi-instruction sequences to new attribute.
        * config/rs6000/{40x.md,440.md,603.md,6xx.md,
        7450.md,7xx.md,8540.md,mpc.md,power4.md,power5.md,
        rios1.md,rios2.md,rs64.md}: Add descriptions for two and three.

From-SVN: r90456
This commit is contained in:
David Edelsohn 2004-11-10 21:57:14 +00:00 committed by David Edelsohn
parent 8b41b1b24f
commit 943c15ed46
15 changed files with 234 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
2004-11-10 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/rs6000.md (define_attr "type"): Add two and three.
Change multi-instruction sequences to new attribute.
* config/rs6000/{40x.md,440.md,603.md,6xx.md,
7450.md,7xx.md,8540.md,mpc.md,power4.md,power5.md,
rios1.md,rios2.md,rs64.md}: Add descriptions for two and three.
2004-11-10 Daniel Berlin <dberlin@dberlin.org>
* tree-data-ref.c (build_classic_dist_vector): If either loop

10
gcc/config/rs6000/40x.md
View File

@ -41,6 +41,16 @@
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,iu_40x")
(define_insn_reservation "ppc403-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,iu_40x,iu_40x")
(define_insn_reservation "ppc403-compare" 3
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
(eq_attr "cpu" "ppc403,ppc405"))

12
gcc/config/rs6000/440.md
View File

@ -58,6 +58,18 @@
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc440"))
"ppc440_issue_0+ppc440_issue_1,\
ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc440"))
"ppc440_issue_0+ppc440_issue_1,ppc440_i_pipe|ppc440_j_pipe,\
ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-imul" 3
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "ppc440"))

10
gcc/config/rs6000/603.md
View File

@ -58,6 +58,16 @@
(eq_attr "cpu" "ppc603"))
"iu_603")
(define_insn_reservation "ppc603-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc603"))
"iu_603,iu_603")
(define_insn_reservation "ppc603-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc603"))
"iu_603,iu_603,iu_603")
; This takes 2 or 3 cycles
(define_insn_reservation "ppc603-imul" 3
(and (eq_attr "type" "imul,imul_compare")

10
gcc/config/rs6000/6xx.md
View File

@ -68,6 +68,16 @@
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-imul" 4
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "ppc604"))

13
gcc/config/rs6000/7450.md
View File

@ -67,7 +67,18 @@
(define_insn_reservation "ppc7450-integer" 1
(and (eq_attr "type" "integer,insert_word")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
(define_insn_reservation "ppc7450-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
(define_insn_reservation "ppc7450-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450,\
iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
(define_insn_reservation "ppc7450-imul" 4
(and (eq_attr "type" "imul,imul_compare")

12
gcc/config/rs6000/7xx.md
View File

@ -61,7 +61,17 @@
(define_insn_reservation "ppc750-integer" 1
(and (eq_attr "type" "integer,insert_word")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,(iu1_7xx|iu2_7xx)")
"ppc750_du,iu1_7xx|iu2_7xx")
(define_insn_reservation "ppc750-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx")
(define_insn_reservation "ppc750-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx")
(define_insn_reservation "ppc750-imul" 4
(and (eq_attr "type" "imul,imul_compare")

13
gcc/config/rs6000/8540.md
View File

@ -89,6 +89,19 @@
(eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
(define_insn_reservation "ppc8540_two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
(define_insn_reservation "ppc8540_three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; Branch. Actually this latency time is not used by the scheduler.
(define_insn_reservation "ppc8540_branch" 1
(and (eq_attr "type" "jmpreg,branch")

10
gcc/config/rs6000/mpc.md
View File

@ -46,6 +46,16 @@
(eq_attr "cpu" "mpccore"))
"iu_mpc")
(define_insn_reservation "mpccore-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "mpccore"))
"iu_mpc,iu_mpc")
(define_insn_reservation "mpccore-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "mpccore"))
"iu_mpc,iu_mpc,iu_mpc")
(define_insn_reservation "mpccore-imul" 2
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "mpccore"))

20
gcc/config/rs6000/power4.md
View File

@ -183,6 +183,26 @@
(eq_attr "cpu" "power4"))
"iq_power4")
(define_insn_reservation "power4-two" 2
(and (eq_attr "type" "two")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\
|(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\
|(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)\
|(du4_power4+du1_power4,iu1_power4,nothing,iu1_power4)")
(define_insn_reservation "power4-three" 2
(and (eq_attr "type" "three")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4+du3_power4,\
iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\
|(du2_power4+du3_power4+du4_power4,\
iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\
|(du3_power4+du4_power4+du1_power4,\
iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\
|(du4_power4+du1_power4+du2_power4,\
iu1_power4,nothing,iu2_power4,nothing,iu2_power4)")
(define_insn_reservation "power4-insert" 4
(and (eq_attr "type" "insert_word")
(eq_attr "cpu" "power4"))

20
gcc/config/rs6000/power5.md
View File

@ -142,6 +142,26 @@
(eq_attr "cpu" "power5"))
"iq_power5")
(define_insn_reservation "power5-two" 2
(and (eq_attr "type" "two")
(eq_attr "cpu" "power5"))
"(du1_power5+du2_power5,iu1_power5,nothing,iu2_power5)\
|(du2_power5+du3_power5,iu2_power5,nothing,iu2_power5)\
|(du3_power5+du4_power5,iu2_power5,nothing,iu1_power5)\
|(du4_power5+du1_power5,iu1_power5,nothing,iu1_power5)")
(define_insn_reservation "power5-three" 2
(and (eq_attr "type" "three")
(eq_attr "cpu" "power5"))
"(du1_power5+du2_power5+du3_power5,\
iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
|(du2_power5+du3_power5+du4_power5,\
iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
|(du3_power5+du4_power5+du1_power5,\
iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
|(du4_power5+du1_power5+du2_power5,\
iu1_power5,nothing,iu2_power5,nothing,iu2_power5)")
(define_insn_reservation "power5-insert" 4
(and (eq_attr "type" "insert_word")
(eq_attr "cpu" "power5"))

10
gcc/config/rs6000/rios1.md
View File

@ -55,6 +55,16 @@
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1")
(define_insn_reservation "rios1-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1,iu_rios1")
(define_insn_reservation "rios1-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1,iu_rios1,iu_rios1")
(define_insn_reservation "rios1-imul" 5
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "rios1"))

10
gcc/config/rs6000/rios2.md
View File

@ -43,6 +43,16 @@
(eq_attr "cpu" "rios2"))
"iu1_rios2|iu2_rios2")
(define_insn_reservation "rios2-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "rios2"))
"iu1_rios2|iu2_rios2,iu1_rios2|iu2_rios2")
(define_insn_reservation "rios2-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "rios2"))
"iu1_rios2|iu2_rios2,iu1_rios2|iu2_rios2,iu1_rios2|iu2_rios2")
(define_insn_reservation "rios2-imul" 2
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "rios2"))

107
gcc/config/rs6000/rs6000.md
View File

@ -64,7 +64,7 @@
;; Define an insn type attribute. This is used in function unit delay
;; computations.
(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
(const_string "integer"))
;; Length (in bytes).
@ -1976,7 +1976,8 @@
(match_operand:SI 2 "exact_log2_cint_operand" "N")))]
""
"{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
[(set_attr "length" "8")])
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@ -5483,7 +5484,8 @@
? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
: \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
}"
[(set_attr "length" "8")])
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn "*subdi3_noppc64"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
@ -5501,7 +5503,8 @@
? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
: \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
}"
[(set_attr "length" "8")])
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn "*negdi2_noppc64"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
@ -5513,7 +5516,8 @@
? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
: \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
}"
[(set_attr "length" "8")])
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_expand "mulsidi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "")
@ -5796,7 +5800,8 @@
"@
{srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
{sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
[(set_attr "length" "8,12")])
[(set_attr "type" "two,three")
(set_attr "length" "8,12")])
(define_insn "*ashrdisi3_noppc64"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@ -6353,7 +6358,8 @@
(match_operand:DI 2 "exact_log2_cint_operand" "N")))]
"TARGET_POWERPC64"
"sradi %0,%1,%p2\;addze %0,%0"
[(set_attr "length" "8")])
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@ -6812,8 +6818,7 @@
(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri")))]
"TARGET_POWERPC64"
"sld%I2 %0,%1,%H2"
[(set_attr "length" "8")])
"sld%I2 %0,%1,%H2")
(define_insn "*ashldi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@ -8184,7 +8189,7 @@
return \"#\";
}
}"
[(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
[(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
(set_attr "length" "8,16,16,4,4,4,8,12,16")])
(define_insn "*movdf_softfloat32"
@ -8225,7 +8230,7 @@
return \"#\";
}
}"
[(set_attr "type" "*,load,store,*,*,*")
[(set_attr "type" "two,load,store,*,*,*")
(set_attr "length" "8,8,8,8,12,16")])
; ld/std require word-aligned displacements -> 'Y' constraint.
@ -11558,7 +11563,8 @@
{xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
{xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
{sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
[(set_attr "length" "12,8,12,12,12")])
[(set_attr "type" "three,two,three,three,three")
(set_attr "length" "12,8,12,12,12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
@ -11572,7 +11578,8 @@
xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
[(set_attr "length" "12,8,12,12,12")])
[(set_attr "type" "three,two,three,three,three")
(set_attr "length" "12,8,12,12,12")])
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
@ -11685,7 +11692,8 @@
{xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
{xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
{sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
[(set_attr "length" "12,8,12,12,12")])
[(set_attr "type" "three,two,three,three,three")
(set_attr "length" "12,8,12,12,12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
@ -11784,7 +11792,8 @@
{xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
{xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
{sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "12,8,12,12,12")])
[(set_attr "type" "three,two,three,three,three")
(set_attr "length" "12,8,12,12,12")])
;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
;; since it nabs/sr is just as fast.
@ -11795,7 +11804,8 @@
(clobber (match_scratch:SI 2 "=&r"))]
"! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
"{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
[(set_attr "length" "8")])
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
@ -11804,7 +11814,8 @@
(clobber (match_scratch:DI 2 "=&r"))]
"TARGET_64BIT"
"addic %2,%1,-1\;subfe %0,%2,%1"
[(set_attr "length" "8")])
[(set_attr "type" "two")
(set_attr "length" "8")])
;; This is what (plus (ne X (const_int 0)) Y) looks like.
(define_insn ""
@ -11816,7 +11827,8 @@
(clobber (match_scratch:SI 3 "=&r"))]
"TARGET_32BIT"
"{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
[(set_attr "length" "8")])
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
@ -11827,7 +11839,8 @@
(clobber (match_scratch:DI 3 "=&r"))]
"TARGET_64BIT"
"addic %3,%1,-1\;addze %0,%2"
[(set_attr "length" "8")])
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@ -12127,7 +12140,8 @@
(match_operand:SI 2 "reg_or_short_operand" "rI")))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
[(set_attr "length" "12")])
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
@ -12135,7 +12149,8 @@
(match_operand:DI 2 "reg_or_short_operand" "rI")))]
"TARGET_64BIT"
"subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
[(set_attr "length" "12")])
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
@ -12206,7 +12221,8 @@
(match_operand:SI 3 "gpc_reg_operand" "r")))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
[(set_attr "length" "8")])
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@ -12279,7 +12295,8 @@
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
[(set_attr "length" "12")])
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
@ -12289,7 +12306,8 @@
(match_operand:SI 3 "gpc_reg_operand" "r")))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
[(set_attr "length" "12")])
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@ -12638,7 +12656,7 @@
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
[(set_attr "type" "insert_word")
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
@ -12649,7 +12667,7 @@
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
[(set_attr "type" "insert_word")
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
@ -12785,7 +12803,8 @@
"@
{sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
{ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
[(set_attr "length" "12")])
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
@ -12795,7 +12814,8 @@
"@
subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
[(set_attr "length" "12")])
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
@ -12872,7 +12892,8 @@
"@
{sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
{ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
[(set_attr "length" "8")])
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@ -12951,7 +12972,8 @@
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
{sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
[(set_attr "length" "12")])
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
@ -12963,7 +12985,8 @@
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
[(set_attr "length" "12")])
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@ -13044,7 +13067,8 @@
(const_int 0)))]
"TARGET_32BIT"
"{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
[(set_attr "length" "12")])
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
@ -13052,7 +13076,8 @@
(const_int 0)))]
"TARGET_64BIT"
"subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
[(set_attr "length" "12")])
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
@ -13162,7 +13187,8 @@
(match_operand:SI 2 "gpc_reg_operand" "r")))]
"TARGET_32BIT"
"{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
[(set_attr "length" "12")])
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
@ -13171,7 +13197,8 @@
(match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_64BIT"
"addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
[(set_attr "length" "12")])
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@ -13382,7 +13409,8 @@
(const_int 0))))]
"TARGET_32BIT"
"{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")])
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
@ -13390,7 +13418,8 @@
(const_int 0))))]
"TARGET_64BIT"
"subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
[(set_attr "length" "12")])
[(set_attr "type" "three")
(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@ -13652,7 +13681,7 @@
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
[(set_attr "type" "insert_word")
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
@ -13661,7 +13690,7 @@
(match_operand:DI 2 "reg_or_short_operand" "rI"))))]
"TARGET_64BIT"
"subf%I2c %0,%1,%2\;subfe %0,%0,%0"
[(set_attr "type" "insert_word")
[(set_attr "type" "two")
(set_attr "length" "8")])
;; Define both directions of branch and return. If we need a reload

10
gcc/config/rs6000/rs64.md
View File

@ -46,6 +46,16 @@
(eq_attr "cpu" "rs64a"))
"iu_rs64")
(define_insn_reservation "rs64a-two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "rs64a"))
"iu_rs64,iu_rs64")
(define_insn_reservation "rs64a-three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "rs64a"))
"iu_rs64,iu_rs64,iu_rs64")
(define_insn_reservation "rs64a-imul" 20
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "rs64a"))