[ARM Refactor Builtins: 1/8] Remove arm_neon.h's "Magic Words"
gcc/testsuite/ * gcc.target/arm/pr51968.c (foo): Do not try to pass "Magic Word". gcc/ * config/arm/arm.c (arm_expand_neon_builtin): Remove "Magic Word" parameter, rearrange switch statement accordingly. (arm_evpc_neon_vrev): Remove "Magic Word". * config/arm/unspecs.md (unspec): Split many UNSPECs to rounding, or signed/unsigned variants. * config/arm/neon.md: Remove "Magic Word" code. * config/arm/iterators.md (VPF): New. (VADDL): Likewise. (VADDW): Likewise. (VHADD): Likewise. (VQADD): Likewise. (VADDHN): Likewise. (VMLAL): Likewise. (VMLAL_LANE): Likewise. (VLMSL): Likewise. (VMLSL_LANE): Likewise. (VQDMULH): Likewise, (VQDMULH_LANE): Likewise. (VMULL): Likewise. (VMULL_LANE): Likewise. (VSUBL): Likewise. (VSUBW): Likewise. (VHSUB): Likewise. (VQSUB): Likewise. (VSUBHN): Likewise. (VABD): Likewise. (VABDL): Likewise. (VMAXMIN): Likewise. (VMAXMINF): Likewise. (VPADDL): Likewise. (VPADAL): Likewise. (VPMAXMIN): Likewise. (VPMAXMINF): Likewise. (VCVT_US): Likewise. (VCVT_US_N): Likewise. (VQMOVN): Likewise. (VMOVL): Likewise. (VSHL): Likewise. (VQSHL): Likewise. (VSHR_N): Likewise. (VSHRN_N): Likewise. (VQSHRN_N): Likewise. (VQSHRUN_N): Likewise. (VQSHL_N): Likewise. (VSHLL_N): Likewise. (VSRA_N): Likewise. (pf): Likewise. (sup): Likewise. (r): Liekwise. (maxmin): Likewise. (shift_op): Likewise. * config/arm/arm_neon_builtins.def: Split many patterns. * config/arm/arm_neon.h (vaddl_s8): Remove "Magic Word" code. From-SVN: r217693
This commit is contained in:
James Greenhalgh
James Greenhalgh
parent
e8c4308977
commit
94f0f2ccaf
1182
gcc/ChangeLog
1182
gcc/ChangeLog
File diff suppressed because it is too large
Load Diff
@ -25535,29 +25535,26 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
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case NEON_CONVERT:
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case NEON_DUPLANE:
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return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
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NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
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NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
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case NEON_BINOP:
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case NEON_SETLANE:
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case NEON_LOGICBINOP:
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case NEON_SCALARMUL:
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case NEON_SCALARMULL:
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case NEON_SCALARMULH:
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case NEON_SHIFTINSERT:
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case NEON_LOGICBINOP:
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return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
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NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
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NEON_ARG_STOP);
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NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
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case NEON_TERNOP:
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return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
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NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
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NEON_ARG_CONSTANT, NEON_ARG_STOP);
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NEON_ARG_STOP);
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case NEON_GETLANE:
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case NEON_FIXCONV:
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case NEON_SHIFTIMM:
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return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
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NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
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NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
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NEON_ARG_STOP);
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case NEON_CREATE:
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@ -25583,24 +25580,26 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
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case NEON_LANEMUL:
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case NEON_LANEMULL:
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case NEON_LANEMULH:
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case NEON_SETLANE:
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case NEON_SHIFTINSERT:
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return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
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NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
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NEON_ARG_CONSTANT, NEON_ARG_STOP);
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NEON_ARG_STOP);
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case NEON_LANEMAC:
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return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
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NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
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NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
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NEON_ARG_CONSTANT, NEON_ARG_STOP);
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case NEON_SHIFTACC:
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return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
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NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
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NEON_ARG_CONSTANT, NEON_ARG_STOP);
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NEON_ARG_STOP);
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case NEON_SCALARMAC:
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return arm_expand_neon_args (target, icode, 1, type_mode, exp, fcode,
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NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
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NEON_ARG_CONSTANT, NEON_ARG_STOP);
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NEON_ARG_STOP);
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case NEON_SELECT:
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case NEON_VTBX:
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@ -31003,7 +31002,7 @@ static bool
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arm_evpc_neon_vrev (struct expand_vec_perm_d *d)
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{
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unsigned int i, j, diff, nelt = d->nelt;
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rtx (*gen)(rtx, rtx, rtx);
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rtx (*gen)(rtx, rtx);
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if (!d->one_vector_p)
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return false;
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@ -31067,9 +31066,7 @@ arm_evpc_neon_vrev (struct expand_vec_perm_d *d)
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if (d->testing_p)
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return true;
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/* ??? The third operand is an artifact of the builtin infrastructure
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and is ignored by the actual instruction. */
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emit_insn (gen (d->target, d->op0, const0_rtx));
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emit_insn (gen (d->target, d->op0));
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return true;
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}
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File diff suppressed because it is too large
Load Diff
@ -19,46 +19,87 @@
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<http://www.gnu.org/licenses/>. */
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VAR2 (BINOP, vadd, v2sf, v4sf),
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VAR3 (BINOP, vaddl, v8qi, v4hi, v2si),
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VAR3 (BINOP, vaddw, v8qi, v4hi, v2si),
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VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR3 (BINOP, vaddls, v8qi, v4hi, v2si),
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VAR3 (BINOP, vaddlu, v8qi, v4hi, v2si),
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VAR3 (BINOP, vaddws, v8qi, v4hi, v2si),
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VAR3 (BINOP, vaddwu, v8qi, v4hi, v2si),
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VAR6 (BINOP, vhaddu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR6 (BINOP, vhadds, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR6 (BINOP, vrhaddu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR6 (BINOP, vrhadds, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR8 (BINOP, vqadds, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (BINOP, vqaddu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR3 (BINOP, vaddhn, v8hi, v4si, v2di),
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VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
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VAR3 (BINOP, vraddhn, v8hi, v4si, v2di),
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VAR2 (BINOP, vmulf, v2sf, v4sf),
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VAR2 (BINOP, vmulp, v8qi, v16qi),
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VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
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VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si),
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VAR3 (TERNOP, vmlals, v8qi, v4hi, v2si),
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VAR3 (TERNOP, vmlalu, v8qi, v4hi, v2si),
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VAR2 (TERNOP, vfma, v2sf, v4sf),
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VAR2 (TERNOP, vfms, v2sf, v4sf),
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VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
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VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si),
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VAR3 (TERNOP, vmlsls, v8qi, v4hi, v2si),
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VAR3 (TERNOP, vmlslu, v8qi, v4hi, v2si),
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VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si),
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VAR4 (BINOP, vqrdmulh, v4hi, v2si, v8hi, v4si),
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VAR2 (TERNOP, vqdmlal, v4hi, v2si),
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VAR2 (TERNOP, vqdmlsl, v4hi, v2si),
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VAR3 (BINOP, vmull, v8qi, v4hi, v2si),
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VAR2 (SCALARMULL, vmull_n, v4hi, v2si),
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VAR2 (LANEMULL, vmull_lane, v4hi, v2si),
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VAR3 (BINOP, vmullp, v8qi, v4hi, v2si),
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VAR3 (BINOP, vmulls, v8qi, v4hi, v2si),
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VAR3 (BINOP, vmullu, v8qi, v4hi, v2si),
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VAR2 (SCALARMULL, vmulls_n, v4hi, v2si),
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VAR2 (SCALARMULL, vmullu_n, v4hi, v2si),
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VAR2 (LANEMULL, vmulls_lane, v4hi, v2si),
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VAR2 (LANEMULL, vmullu_lane, v4hi, v2si),
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VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si),
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VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si),
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VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si),
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VAR4 (SCALARMULH, vqrdmulh_n, v4hi, v2si, v8hi, v4si),
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VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si),
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VAR4 (LANEMULH, vqrdmulh_lane, v4hi, v2si, v8hi, v4si),
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VAR2 (BINOP, vqdmull, v4hi, v2si),
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VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (BINOP, vshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (BINOP, vshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (BINOP, vrshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (BINOP, vrshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (BINOP, vqshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (BINOP, vqshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (BINOP, vqrshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (BINOP, vqrshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (SHIFTIMM, vshrs_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (SHIFTIMM, vshru_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (SHIFTIMM, vrshrs_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (SHIFTIMM, vrshru_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di),
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VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di),
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VAR3 (SHIFTIMM, vrshrn_n, v8hi, v4si, v2di),
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VAR3 (SHIFTIMM, vqshrns_n, v8hi, v4si, v2di),
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VAR3 (SHIFTIMM, vqshrnu_n, v8hi, v4si, v2di),
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VAR3 (SHIFTIMM, vqrshrns_n, v8hi, v4si, v2di),
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VAR3 (SHIFTIMM, vqrshrnu_n, v8hi, v4si, v2di),
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VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di),
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VAR3 (SHIFTIMM, vqrshrun_n, v8hi, v4si, v2di),
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VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (SHIFTIMM, vqshl_s_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (SHIFTIMM, vqshl_u_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si),
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VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR3 (SHIFTIMM, vshlls_n, v8qi, v4hi, v2si),
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VAR3 (SHIFTIMM, vshllu_n, v8qi, v4hi, v2si),
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VAR8 (SHIFTACC, vsras_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (SHIFTACC, vsrau_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (SHIFTACC, vrsras_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (SHIFTACC, vrsrau_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR2 (BINOP, vsub, v2sf, v4sf),
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VAR3 (BINOP, vsubl, v8qi, v4hi, v2si),
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VAR3 (BINOP, vsubw, v8qi, v4hi, v2si),
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VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR3 (BINOP, vsubls, v8qi, v4hi, v2si),
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VAR3 (BINOP, vsublu, v8qi, v4hi, v2si),
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VAR3 (BINOP, vsubws, v8qi, v4hi, v2si),
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VAR3 (BINOP, vsubwu, v8qi, v4hi, v2si),
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VAR8 (BINOP, vqsubs, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR8 (BINOP, vqsubu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
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VAR6 (BINOP, vhsubs, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR6 (BINOP, vhsubu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR3 (BINOP, vsubhn, v8hi, v4si, v2di),
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VAR3 (BINOP, vrsubhn, v8hi, v4si, v2di),
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VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
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VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
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VAR6 (BINOP, vcgeu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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@ -67,17 +108,36 @@ VAR6 (BINOP, vcgtu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR2 (BINOP, vcage, v2sf, v4sf),
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VAR2 (BINOP, vcagt, v2sf, v4sf),
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VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
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VAR3 (BINOP, vabdl, v8qi, v4hi, v2si),
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VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR3 (TERNOP, vabal, v8qi, v4hi, v2si),
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VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
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VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
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VAR6 (BINOP, vabds, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR6 (BINOP, vabdu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR2 (BINOP, vabdf, v2sf, v4sf),
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VAR3 (BINOP, vabdls, v8qi, v4hi, v2si),
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VAR3 (BINOP, vabdlu, v8qi, v4hi, v2si),
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VAR6 (TERNOP, vabas, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR6 (TERNOP, vabau, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR3 (TERNOP, vabals, v8qi, v4hi, v2si),
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VAR3 (TERNOP, vabalu, v8qi, v4hi, v2si),
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VAR6 (BINOP, vmaxs, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR6 (BINOP, vmaxu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR2 (BINOP, vmaxf, v2sf, v4sf),
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VAR6 (BINOP, vmins, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR6 (BINOP, vminu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR2 (BINOP, vminf, v2sf, v4sf),
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VAR3 (BINOP, vpmaxs, v8qi, v4hi, v2si),
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VAR3 (BINOP, vpmaxu, v8qi, v4hi, v2si),
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VAR1 (BINOP, vpmaxf, v2sf),
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VAR3 (BINOP, vpmins, v8qi, v4hi, v2si),
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VAR3 (BINOP, vpminu, v8qi, v4hi, v2si),
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VAR1 (BINOP, vpminf, v2sf),
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VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf),
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VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
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VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf),
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VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf),
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VAR6 (UNOP, vpaddls, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
|
||||
VAR6 (UNOP, vpaddlu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
|
||||
VAR6 (BINOP, vpadals, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
|
||||
VAR6 (BINOP, vpadalu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
|
||||
VAR2 (BINOP, vrecps, v2sf, v4sf),
|
||||
VAR2 (BINOP, vrsqrts, v2sf, v4sf),
|
||||
VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
|
||||
@ -96,41 +156,50 @@ VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
|
||||
/* FIXME: vget_lane supports more variants than this! */
|
||||
VAR10 (GETLANE, vget_lane,
|
||||
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
|
||||
VAR6 (GETLANE, vget_laneu, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
|
||||
VAR10 (SETLANE, vset_lane,
|
||||
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
|
||||
VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di),
|
||||
VAR10 (DUP, vdup_n,
|
||||
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
|
||||
VAR10 (DUPLANE, vdup_lane,
|
||||
VAR10 (BINOP, vdup_lane,
|
||||
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
|
||||
VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di),
|
||||
VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di),
|
||||
VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di),
|
||||
VAR3 (UNOP, vmovn, v8hi, v4si, v2di),
|
||||
VAR3 (UNOP, vqmovn, v8hi, v4si, v2di),
|
||||
VAR3 (UNOP, vqmovns, v8hi, v4si, v2di),
|
||||
VAR3 (UNOP, vqmovnu, v8hi, v4si, v2di),
|
||||
VAR3 (UNOP, vqmovun, v8hi, v4si, v2di),
|
||||
VAR3 (UNOP, vmovl, v8qi, v4hi, v2si),
|
||||
VAR3 (UNOP, vmovls, v8qi, v4hi, v2si),
|
||||
VAR3 (UNOP, vmovlu, v8qi, v4hi, v2si),
|
||||
VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
|
||||
VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
|
||||
VAR2 (LANEMAC, vmlal_lane, v4hi, v2si),
|
||||
VAR2 (LANEMAC, vmlals_lane, v4hi, v2si),
|
||||
VAR2 (LANEMAC, vmlalu_lane, v4hi, v2si),
|
||||
VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si),
|
||||
VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
|
||||
VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si),
|
||||
VAR2 (LANEMAC, vmlsls_lane, v4hi, v2si),
|
||||
VAR2 (LANEMAC, vmlslu_lane, v4hi, v2si),
|
||||
VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si),
|
||||
VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
|
||||
VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
|
||||
VAR2 (SCALARMAC, vmlal_n, v4hi, v2si),
|
||||
VAR2 (SCALARMAC, vmlals_n, v4hi, v2si),
|
||||
VAR2 (SCALARMAC, vmlalu_n, v4hi, v2si),
|
||||
VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si),
|
||||
VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
|
||||
VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si),
|
||||
VAR2 (SCALARMAC, vmlsls_n, v4hi, v2si),
|
||||
VAR2 (SCALARMAC, vmlslu_n, v4hi, v2si),
|
||||
VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si),
|
||||
VAR10 (BINOP, vext,
|
||||
VAR10 (SHIFTINSERT, vext,
|
||||
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
|
||||
VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
|
||||
VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi),
|
||||
VAR2 (UNOP, vrev16, v8qi, v16qi),
|
||||
VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf),
|
||||
VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf),
|
||||
VAR4 (CONVERT, vcvts, v2si, v2sf, v4si, v4sf),
|
||||
VAR4 (CONVERT, vcvtu, v2si, v2sf, v4si, v4sf),
|
||||
VAR4 (FIXCONV, vcvts_n, v2si, v2sf, v4si, v4sf),
|
||||
VAR4 (FIXCONV, vcvtu_n, v2si, v2sf, v4si, v4sf),
|
||||
VAR1 (FLOAT_WIDEN, vcvtv4sf, v4hf),
|
||||
VAR1 (FLOAT_NARROW, vcvtv4hf, v4sf),
|
||||
VAR10 (SELECT, vbsl,
|
||||
|
||||
@ -169,6 +169,9 @@
|
||||
|
||||
(define_mode_iterator QMUL [HQ HA])
|
||||
|
||||
;; Modes for polynomial or float values.
|
||||
(define_mode_iterator VPF [V8QI V16QI V2SF V4SF])
|
||||
|
||||
;;----------------------------------------------------------------------------
|
||||
;; Code iterators
|
||||
;;----------------------------------------------------------------------------
|
||||
@ -225,6 +228,92 @@
|
||||
|
||||
(define_int_iterator NEON_VCVT [UNSPEC_NVRINTP UNSPEC_NVRINTM UNSPEC_NVRINTA])
|
||||
|
||||
(define_int_iterator VADDL [UNSPEC_VADDL_S UNSPEC_VADDL_U])
|
||||
|
||||
(define_int_iterator VADDW [UNSPEC_VADDW_S UNSPEC_VADDW_U])
|
||||
|
||||
(define_int_iterator VHADD [UNSPEC_VRHADD_S UNSPEC_VRHADD_U
|
||||
UNSPEC_VHADD_S UNSPEC_VHADD_U])
|
||||
|
||||
(define_int_iterator VQADD [UNSPEC_VQADD_S UNSPEC_VQADD_U])
|
||||
|
||||
(define_int_iterator VADDHN [UNSPEC_VADDHN UNSPEC_VRADDHN])
|
||||
|
||||
(define_int_iterator VMLAL [UNSPEC_VMLAL_S UNSPEC_VMLAL_U])
|
||||
|
||||
(define_int_iterator VMLAL_LANE [UNSPEC_VMLAL_S_LANE UNSPEC_VMLAL_U_LANE])
|
||||
|
||||
(define_int_iterator VMLSL [UNSPEC_VMLSL_S UNSPEC_VMLSL_U])
|
||||
|
||||
(define_int_iterator VMLSL_LANE [UNSPEC_VMLSL_S_LANE UNSPEC_VMLSL_U_LANE])
|
||||
|
||||
(define_int_iterator VQDMULH [UNSPEC_VQDMULH UNSPEC_VQRDMULH])
|
||||
|
||||
(define_int_iterator VQDMULH_LANE [UNSPEC_VQDMULH_LANE UNSPEC_VQRDMULH_LANE])
|
||||
|
||||
(define_int_iterator VMULL [UNSPEC_VMULL_S UNSPEC_VMULL_U UNSPEC_VMULL_P])
|
||||
|
||||
(define_int_iterator VMULL_LANE [UNSPEC_VMULL_S_LANE UNSPEC_VMULL_U_LANE])
|
||||
|
||||
(define_int_iterator VSUBL [UNSPEC_VSUBL_S UNSPEC_VSUBL_U])
|
||||
|
||||
(define_int_iterator VSUBW [UNSPEC_VSUBW_S UNSPEC_VSUBW_U])
|
||||
|
||||
(define_int_iterator VHSUB [UNSPEC_VHSUB_S UNSPEC_VHSUB_U])
|
||||
|
||||
(define_int_iterator VQSUB [UNSPEC_VQSUB_S UNSPEC_VQSUB_U])
|
||||
|
||||
(define_int_iterator VSUBHN [UNSPEC_VSUBHN UNSPEC_VRSUBHN])
|
||||
|
||||
(define_int_iterator VABD [UNSPEC_VABD_S UNSPEC_VABD_U])
|
||||
|
||||
(define_int_iterator VABDL [UNSPEC_VABDL_S UNSPEC_VABDL_U])
|
||||
|
||||
(define_int_iterator VMAXMIN [UNSPEC_VMAX UNSPEC_VMAX_U
|
||||
UNSPEC_VMIN UNSPEC_VMIN_U])
|
||||
|
||||
(define_int_iterator VMAXMINF [UNSPEC_VMAX UNSPEC_VMIN])
|
||||
|
||||
(define_int_iterator VPADDL [UNSPEC_VPADDL_S UNSPEC_VPADDL_U])
|
||||
|
||||
(define_int_iterator VPADAL [UNSPEC_VPADAL_S UNSPEC_VPADAL_U])
|
||||
|
||||
(define_int_iterator VPMAXMIN [UNSPEC_VPMAX UNSPEC_VPMAX_U
|
||||
UNSPEC_VPMIN UNSPEC_VPMIN_U])
|
||||
|
||||
(define_int_iterator VPMAXMINF [UNSPEC_VPMAX UNSPEC_VPMIN])
|
||||
|
||||
(define_int_iterator VCVT_US [UNSPEC_VCVT_S UNSPEC_VCVT_U])
|
||||
|
||||
(define_int_iterator VCVT_US_N [UNSPEC_VCVT_S_N UNSPEC_VCVT_U_N])
|
||||
|
||||
(define_int_iterator VQMOVN [UNSPEC_VQMOVN_S UNSPEC_VQMOVN_U])
|
||||
|
||||
(define_int_iterator VMOVL [UNSPEC_VMOVL_S UNSPEC_VMOVL_U])
|
||||
|
||||
(define_int_iterator VSHL [UNSPEC_VSHL_S UNSPEC_VSHL_U
|
||||
UNSPEC_VRSHL_S UNSPEC_VRSHL_U])
|
||||
|
||||
(define_int_iterator VQSHL [UNSPEC_VQSHL_S UNSPEC_VQSHL_U
|
||||
UNSPEC_VQRSHL_S UNSPEC_VQRSHL_U])
|
||||
|
||||
(define_int_iterator VSHR_N [UNSPEC_VSHR_S_N UNSPEC_VSHR_U_N
|
||||
UNSPEC_VRSHR_S_N UNSPEC_VRSHR_U_N])
|
||||
|
||||
(define_int_iterator VSHRN_N [UNSPEC_VSHRN_N UNSPEC_VRSHRN_N])
|
||||
|
||||
(define_int_iterator VQSHRN_N [UNSPEC_VQSHRN_S_N UNSPEC_VQSHRN_U_N
|
||||
UNSPEC_VQRSHRN_S_N UNSPEC_VQRSHRN_U_N])
|
||||
|
||||
(define_int_iterator VQSHRUN_N [UNSPEC_VQSHRUN_N UNSPEC_VQRSHRUN_N])
|
||||
|
||||
(define_int_iterator VQSHL_N [UNSPEC_VQSHL_S_N UNSPEC_VQSHL_U_N])
|
||||
|
||||
(define_int_iterator VSHLL_N [UNSPEC_VSHLL_S_N UNSPEC_VSHLL_U_N])
|
||||
|
||||
(define_int_iterator VSRA_N [UNSPEC_VSRA_S_N UNSPEC_VSRA_U_N
|
||||
UNSPEC_VRSRA_S_N UNSPEC_VRSRA_U_N])
|
||||
|
||||
(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
|
||||
UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW])
|
||||
|
||||
@ -504,6 +593,8 @@
|
||||
(DI "") (V2DI "_q")
|
||||
(DF "") (V2DF "_q")])
|
||||
|
||||
(define_mode_attr pf [(V8QI "p") (V16QI "p") (V2SF "f") (V4SF "f")])
|
||||
|
||||
;;----------------------------------------------------------------------------
|
||||
;; Code attributes
|
||||
;;----------------------------------------------------------------------------
|
||||
@ -541,6 +632,82 @@
|
||||
;; Int attributes
|
||||
;;----------------------------------------------------------------------------
|
||||
|
||||
;; Mapping between vector UNSPEC operations and the signed ('s'),
|
||||
;; unsigned ('u'), poly ('p') or float ('f') nature of their data type.
|
||||
(define_int_attr sup [
|
||||
(UNSPEC_VADDL_S "s") (UNSPEC_VADDL_U "u")
|
||||
(UNSPEC_VADDW_S "s") (UNSPEC_VADDW_U "u")
|
||||
(UNSPEC_VRHADD_S "s") (UNSPEC_VRHADD_U "u")
|
||||
(UNSPEC_VHADD_S "s") (UNSPEC_VHADD_U "u")
|
||||
(UNSPEC_VQADD_S "s") (UNSPEC_VQADD_U "u")
|
||||
(UNSPEC_VMLAL_S "s") (UNSPEC_VMLAL_U "u")
|
||||
(UNSPEC_VMLAL_S_LANE "s") (UNSPEC_VMLAL_U_LANE "u")
|
||||
(UNSPEC_VMLSL_S "s") (UNSPEC_VMLSL_U "u")
|
||||
(UNSPEC_VMLSL_S_LANE "s") (UNSPEC_VMLSL_U_LANE "u")
|
||||
(UNSPEC_VMULL_S "s") (UNSPEC_VMULL_U "u") (UNSPEC_VMULL_P "p")
|
||||
(UNSPEC_VMULL_S_LANE "s") (UNSPEC_VMULL_U_LANE "u")
|
||||
(UNSPEC_VSUBL_S "s") (UNSPEC_VSUBL_U "u")
|
||||
(UNSPEC_VSUBW_S "s") (UNSPEC_VSUBW_U "u")
|
||||
(UNSPEC_VHSUB_S "s") (UNSPEC_VHSUB_U "u")
|
||||
(UNSPEC_VQSUB_S "s") (UNSPEC_VQSUB_U "u")
|
||||
(UNSPEC_VABD_S "s") (UNSPEC_VABD_U "u")
|
||||
(UNSPEC_VABDL_S "s") (UNSPEC_VABDL_U "u")
|
||||
(UNSPEC_VMAX "s") (UNSPEC_VMAX_U "u")
|
||||
(UNSPEC_VMIN "s") (UNSPEC_VMIN_U "u")
|
||||
(UNSPEC_VPADDL_S "s") (UNSPEC_VPADDL_U "u")
|
||||
(UNSPEC_VPADAL_S "s") (UNSPEC_VPADAL_U "u")
|
||||
(UNSPEC_VPMAX "s") (UNSPEC_VPMAX_U "u")
|
||||
(UNSPEC_VPMIN "s") (UNSPEC_VPMIN_U "u")
|
||||
(UNSPEC_VCVT_S "s") (UNSPEC_VCVT_U "u")
|
||||
(UNSPEC_VCVT_S_N "s") (UNSPEC_VCVT_U_N "u")
|
||||
(UNSPEC_VQMOVN_S "s") (UNSPEC_VQMOVN_U "u")
|
||||
(UNSPEC_VMOVL_S "s") (UNSPEC_VMOVL_U "u")
|
||||
(UNSPEC_VSHL_S "s") (UNSPEC_VSHL_U "u")
|
||||
(UNSPEC_VRSHL_S "s") (UNSPEC_VRSHL_U "u")
|
||||
(UNSPEC_VQSHL_S "s") (UNSPEC_VQSHL_U "u")
|
||||
(UNSPEC_VQRSHL_S "s") (UNSPEC_VQRSHL_U "u")
|
||||
(UNSPEC_VSHR_S_N "s") (UNSPEC_VSHR_U_N "u")
|
||||
(UNSPEC_VRSHR_S_N "s") (UNSPEC_VRSHR_U_N "u")
|
||||
(UNSPEC_VQSHRN_S_N "s") (UNSPEC_VQSHRN_U_N "u")
|
||||
(UNSPEC_VQRSHRN_S_N "s") (UNSPEC_VQRSHRN_U_N "u")
|
||||
(UNSPEC_VQSHL_S_N "s") (UNSPEC_VQSHL_U_N "u")
|
||||
(UNSPEC_VSHLL_S_N "s") (UNSPEC_VSHLL_U_N "u")
|
||||
(UNSPEC_VSRA_S_N "s") (UNSPEC_VSRA_U_N "u")
|
||||
(UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u")
|
||||
|
||||
])
|
||||
|
||||
(define_int_attr r [
|
||||
(UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r")
|
||||
(UNSPEC_VHADD_S "") (UNSPEC_VHADD_U "")
|
||||
(UNSPEC_VADDHN "") (UNSPEC_VRADDHN "r")
|
||||
(UNSPEC_VQDMULH "") (UNSPEC_VQRDMULH "r")
|
||||
(UNSPEC_VQDMULH_LANE "") (UNSPEC_VQRDMULH_LANE "r")
|
||||
(UNSPEC_VSUBHN "") (UNSPEC_VRSUBHN "r")
|
||||
])
|
||||
|
||||
(define_int_attr maxmin [
|
||||
(UNSPEC_VMAX "max") (UNSPEC_VMAX_U "max")
|
||||
(UNSPEC_VMIN "min") (UNSPEC_VMIN_U "min")
|
||||
(UNSPEC_VPMAX "max") (UNSPEC_VPMAX_U "max")
|
||||
(UNSPEC_VPMIN "min") (UNSPEC_VPMIN_U "min")
|
||||
])
|
||||
|
||||
(define_int_attr shift_op [
|
||||
(UNSPEC_VSHL_S "shl") (UNSPEC_VSHL_U "shl")
|
||||
(UNSPEC_VRSHL_S "rshl") (UNSPEC_VRSHL_U "rshl")
|
||||
(UNSPEC_VQSHL_S "qshl") (UNSPEC_VQSHL_U "qshl")
|
||||
(UNSPEC_VQRSHL_S "qrshl") (UNSPEC_VQRSHL_U "qrshl")
|
||||
(UNSPEC_VSHR_S_N "shr") (UNSPEC_VSHR_U_N "shr")
|
||||
(UNSPEC_VRSHR_S_N "rshr") (UNSPEC_VRSHR_U_N "rshr")
|
||||
(UNSPEC_VSHRN_N "shrn") (UNSPEC_VRSHRN_N "rshrn")
|
||||
(UNSPEC_VQRSHRN_S_N "qrshrn") (UNSPEC_VQRSHRN_U_N "qrshrn")
|
||||
(UNSPEC_VQSHRN_S_N "qshrn") (UNSPEC_VQSHRN_U_N "qshrn")
|
||||
(UNSPEC_VQSHRUN_N "qshrun") (UNSPEC_VQRSHRUN_N "qrshrun")
|
||||
(UNSPEC_VSRA_S_N "sra") (UNSPEC_VSRA_U_N "sra")
|
||||
(UNSPEC_VRSRA_S_N "rsra") (UNSPEC_VRSRA_U_N "rsra")
|
||||
])
|
||||
|
||||
;; Standard names for floating point to integral rounding instructions.
|
||||
(define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil")
|
||||
(UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor")
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -173,12 +173,18 @@
|
||||
UNSPEC_SHA256SU1
|
||||
UNSPEC_VMULLP64
|
||||
UNSPEC_LOAD_COUNT
|
||||
UNSPEC_VABD
|
||||
UNSPEC_VABDL
|
||||
UNSPEC_VABD_F
|
||||
UNSPEC_VABD_S
|
||||
UNSPEC_VABD_U
|
||||
UNSPEC_VABDL_S
|
||||
UNSPEC_VABDL_U
|
||||
UNSPEC_VADD
|
||||
UNSPEC_VADDHN
|
||||
UNSPEC_VADDL
|
||||
UNSPEC_VADDW
|
||||
UNSPEC_VRADDHN
|
||||
UNSPEC_VADDL_S
|
||||
UNSPEC_VADDL_U
|
||||
UNSPEC_VADDW_S
|
||||
UNSPEC_VADDW_U
|
||||
UNSPEC_VBSL
|
||||
UNSPEC_VCAGE
|
||||
UNSPEC_VCAGT
|
||||
@ -190,10 +196,17 @@
|
||||
UNSPEC_VCLS
|
||||
UNSPEC_VCONCAT
|
||||
UNSPEC_VCVT
|
||||
UNSPEC_VCVT_N
|
||||
UNSPEC_VCVT_S
|
||||
UNSPEC_VCVT_U
|
||||
UNSPEC_VCVT_S_N
|
||||
UNSPEC_VCVT_U_N
|
||||
UNSPEC_VEXT
|
||||
UNSPEC_VHADD
|
||||
UNSPEC_VHSUB
|
||||
UNSPEC_VHADD_S
|
||||
UNSPEC_VHADD_U
|
||||
UNSPEC_VRHADD_S
|
||||
UNSPEC_VRHADD_U
|
||||
UNSPEC_VHSUB_S
|
||||
UNSPEC_VHSUB_U
|
||||
UNSPEC_VLD1
|
||||
UNSPEC_VLD1_LANE
|
||||
UNSPEC_VLD2
|
||||
@ -210,49 +223,77 @@
|
||||
UNSPEC_VLD4_DUP
|
||||
UNSPEC_VLD4_LANE
|
||||
UNSPEC_VMAX
|
||||
UNSPEC_VMAX_U
|
||||
UNSPEC_VMIN
|
||||
UNSPEC_VMIN_U
|
||||
UNSPEC_VMLA
|
||||
UNSPEC_VMLAL
|
||||
UNSPEC_VMLA_LANE
|
||||
UNSPEC_VMLAL_LANE
|
||||
UNSPEC_VMLAL_S
|
||||
UNSPEC_VMLAL_U
|
||||
UNSPEC_VMLAL_S_LANE
|
||||
UNSPEC_VMLAL_U_LANE
|
||||
UNSPEC_VMLS
|
||||
UNSPEC_VMLSL
|
||||
UNSPEC_VMLS_LANE
|
||||
UNSPEC_VMLSL_S
|
||||
UNSPEC_VMLSL_U
|
||||
UNSPEC_VMLSL_S_LANE
|
||||
UNSPEC_VMLSL_U_LANE
|
||||
UNSPEC_VMLSL_LANE
|
||||
UNSPEC_VMOVL
|
||||
UNSPEC_VMOVL_S
|
||||
UNSPEC_VMOVL_U
|
||||
UNSPEC_VMOVN
|
||||
UNSPEC_VMUL
|
||||
UNSPEC_VMULL
|
||||
UNSPEC_VMULL_P
|
||||
UNSPEC_VMULL_S
|
||||
UNSPEC_VMULL_U
|
||||
UNSPEC_VMUL_LANE
|
||||
UNSPEC_VMULL_LANE
|
||||
UNSPEC_VPADAL
|
||||
UNSPEC_VMULL_S_LANE
|
||||
UNSPEC_VMULL_U_LANE
|
||||
UNSPEC_VPADAL_S
|
||||
UNSPEC_VPADAL_U
|
||||
UNSPEC_VPADD
|
||||
UNSPEC_VPADDL
|
||||
UNSPEC_VPADDL_S
|
||||
UNSPEC_VPADDL_U
|
||||
UNSPEC_VPMAX
|
||||
UNSPEC_VPMAX_U
|
||||
UNSPEC_VPMIN
|
||||
UNSPEC_VPMIN_U
|
||||
UNSPEC_VPSMAX
|
||||
UNSPEC_VPSMIN
|
||||
UNSPEC_VPUMAX
|
||||
UNSPEC_VPUMIN
|
||||
UNSPEC_VQABS
|
||||
UNSPEC_VQADD
|
||||
UNSPEC_VQADD_S
|
||||
UNSPEC_VQADD_U
|
||||
UNSPEC_VQDMLAL
|
||||
UNSPEC_VQDMLAL_LANE
|
||||
UNSPEC_VQDMLSL
|
||||
UNSPEC_VQDMLSL_LANE
|
||||
UNSPEC_VQDMULH
|
||||
UNSPEC_VQDMULH_LANE
|
||||
UNSPEC_VQRDMULH
|
||||
UNSPEC_VQRDMULH_LANE
|
||||
UNSPEC_VQDMULL
|
||||
UNSPEC_VQDMULL_LANE
|
||||
UNSPEC_VQMOVN
|
||||
UNSPEC_VQMOVN_S
|
||||
UNSPEC_VQMOVN_U
|
||||
UNSPEC_VQMOVUN
|
||||
UNSPEC_VQNEG
|
||||
UNSPEC_VQSHL
|
||||
UNSPEC_VQSHL_N
|
||||
UNSPEC_VQSHL_S
|
||||
UNSPEC_VQSHL_U
|
||||
UNSPEC_VQRSHL_S
|
||||
UNSPEC_VQRSHL_U
|
||||
UNSPEC_VQSHL_S_N
|
||||
UNSPEC_VQSHL_U_N
|
||||
UNSPEC_VQSHLU_N
|
||||
UNSPEC_VQSHRN_N
|
||||
UNSPEC_VQSHRN_S_N
|
||||
UNSPEC_VQSHRN_U_N
|
||||
UNSPEC_VQRSHRN_S_N
|
||||
UNSPEC_VQRSHRN_U_N
|
||||
UNSPEC_VQSHRUN_N
|
||||
UNSPEC_VQSUB
|
||||
UNSPEC_VQRSHRUN_N
|
||||
UNSPEC_VQSUB_S
|
||||
UNSPEC_VQSUB_U
|
||||
UNSPEC_VRECPE
|
||||
UNSPEC_VRECPS
|
||||
UNSPEC_VREV16
|
||||
@ -260,13 +301,24 @@
|
||||
UNSPEC_VREV64
|
||||
UNSPEC_VRSQRTE
|
||||
UNSPEC_VRSQRTS
|
||||
UNSPEC_VSHL
|
||||
UNSPEC_VSHLL_N
|
||||
UNSPEC_VSHL_S
|
||||
UNSPEC_VSHL_U
|
||||
UNSPEC_VRSHL_S
|
||||
UNSPEC_VRSHL_U
|
||||
UNSPEC_VSHLL_S_N
|
||||
UNSPEC_VSHLL_U_N
|
||||
UNSPEC_VSHL_N
|
||||
UNSPEC_VSHR_N
|
||||
UNSPEC_VSHR_S_N
|
||||
UNSPEC_VSHR_U_N
|
||||
UNSPEC_VRSHR_S_N
|
||||
UNSPEC_VRSHR_U_N
|
||||
UNSPEC_VSHRN_N
|
||||
UNSPEC_VRSHRN_N
|
||||
UNSPEC_VSLI
|
||||
UNSPEC_VSRA_N
|
||||
UNSPEC_VSRA_S_N
|
||||
UNSPEC_VSRA_U_N
|
||||
UNSPEC_VRSRA_S_N
|
||||
UNSPEC_VRSRA_U_N
|
||||
UNSPEC_VSRI
|
||||
UNSPEC_VST1
|
||||
UNSPEC_VST1_LANE
|
||||
@ -283,8 +335,11 @@
|
||||
UNSPEC_VSTRUCTDUMMY
|
||||
UNSPEC_VSUB
|
||||
UNSPEC_VSUBHN
|
||||
UNSPEC_VSUBL
|
||||
UNSPEC_VSUBW
|
||||
UNSPEC_VRSUBHN
|
||||
UNSPEC_VSUBL_S
|
||||
UNSPEC_VSUBL_U
|
||||
UNSPEC_VSUBW_S
|
||||
UNSPEC_VSUBW_U
|
||||
UNSPEC_VTBL
|
||||
UNSPEC_VTBX
|
||||
UNSPEC_VTRN1
|
||||
|
||||
@ -1,3 +1,8 @@
|
||||
2014-11-18 James Greenhalgh <james.greenhalgh@arm.com>
|
||||
|
||||
* gcc.target/arm/pr51968.c (foo): Fix call to
|
||||
__builtin_neon_vqmovunv8hi.
|
||||
|
||||
2014-11-18 Marat Zakirov <m.zakirov@samsung.com>
|
||||
|
||||
* c-c++-common/asan/aggressive-opts.c: New test.
|
||||
|
||||
@ -24,7 +24,7 @@ foo (int8x8_t z, int8x8_t x, int16x8_t b, int8x8_t n)
|
||||
int8x16_t g;
|
||||
int8x8_t h, j, k;
|
||||
struct T m;
|
||||
j = __builtin_neon_vqmovunv8hi (b, 1);
|
||||
j = __builtin_neon_vqmovunv8hi (b);
|
||||
g = __builtin_neon_vcombinev8qi (j, h);
|
||||
k = __builtin_neon_vget_lowv16qi (g);
|
||||
__builtin_neon_vuzpv8qi (&m.val[0], k, n);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user