i386.c (ix86_expand_branch): Don't split DI mode xor instruction to SI mode.
gcc/ * config/i386/i386.c (ix86_expand_branch): Don't split DI mode xor instruction to SI mode. gcc/testsuite/ * gcc.target/i386/pr65105-5.c: New test. From-SVN: r232413
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2016-01-15 Ilya Enkovich <enkovich.gnu@gmail.com>
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* config/i386/i386.c (ix86_expand_branch): Don't split
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DI mode xor instruction to SI mode.
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2016-01-15 Jan Hubicka <hubicka@ucw.cz>
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PR ipa/68148
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@ -21699,6 +21699,19 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
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case DImode:
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if (TARGET_64BIT)
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goto simple;
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/* For 32-bit target DI comparison may be performed on
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SSE registers. To allow this we should avoid split
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to SI mode which is achieved by doing xor in DI mode
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and then comparing with zero (which is recognized by
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STV pass). We don't compare using xor when optimizing
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for size. */
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if (!optimize_insn_for_size_p ()
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&& TARGET_STV
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&& (code == EQ || code == NE))
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{
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op0 = force_reg (mode, gen_rtx_XOR (mode, op0, op1));
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op1 = const0_rtx;
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}
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case TImode:
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/* Expand DImode branch into multiple compare+branch. */
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{
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@ -1,3 +1,7 @@
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2016-01-15 Ilya Enkovich <enkovich.gnu@gmail.com>
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* gcc.target/i386/pr65105-5.c: New test.
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2016-01-15 Jan Hubicka <hubicka@ucw.cz>
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* gcc.c-torture/execute/alias-4.c: New testcase.
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@ -0,0 +1,22 @@
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/* PR target/pr65105 */
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/* { dg-do compile { target { ia32 } } } */
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/* { dg-options "-O2 -march=core-avx2" } */
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/* { dg-final { scan-assembler "pand" } } */
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/* { dg-final { scan-assembler "pxor" } } */
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/* { dg-final { scan-assembler "ptest" } } */
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struct S1
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{
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unsigned long long a;
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unsigned long long b;
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};
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void
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test (int p1, unsigned long long p2, int p3, struct S1 *p4)
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{
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int i;
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for (i = 0; i < p1; i++)
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if ((p4[i].a & p2) != p2)
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p4[i].a ^= (1ULL << p3);
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}
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