arm.md (QHSI): New mode iterator.
* arm.md (QHSI): New mode iterator. (movqi): If generating for thumb, then truncate any immediate to 8 bits. * thumb2.md (thumb2_movsi_shortim and peephole2 generator): Replace with... (thumb2_mov<mode>_shortim and peephole2 generator): ... iterator based version. From-SVN: r153739
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@ -1,3 +1,13 @@
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2009-10-30 Richard Earnshaw <rearnsha@arm.com>
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* arm.md (QHSI): New mode iterator.
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(movqi): If generating for thumb, then truncate any immediate to
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8 bits.
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* thumb2.md (thumb2_movsi_shortim and peephole2 generator): Replace
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with...
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(thumb2_mov<mode>_shortim and peephole2 generator): ... iterator based
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version.
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2009-10-29 Cary Coutant <ccoutant@google.com>
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PR debug/41700
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@ -392,6 +392,9 @@
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; registers.
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(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF])
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;; The integer modes up to word size
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(define_mode_iterator QHSI [QI HI SI])
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;;---------------------------------------------------------------------------
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;; Predicates
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@ -5848,6 +5851,11 @@
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{
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rtx reg = gen_reg_rtx (SImode);
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/* For thumb we want an unsigned immediate, then we are more likely
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to be able to use a movs insn. */
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if (TARGET_THUMB)
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operands[1] = GEN_INT (INTVAL (operands[1]) & 255);
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emit_insn (gen_movsi (reg, operands[1]));
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operands[1] = gen_lowpart (QImode, reg);
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}
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@ -1156,8 +1156,8 @@
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;; 16-bit load immediate
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(define_peephole2
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[(set (match_operand:SI 0 "low_register_operand" "")
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(match_operand:SI 1 "const_int_operand" ""))]
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[(set (match_operand:QHSI 0 "low_register_operand" "")
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(match_operand:QHSI 1 "const_int_operand" ""))]
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"TARGET_THUMB2
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&& peep2_regno_dead_p(0, CC_REGNUM)
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&& (unsigned HOST_WIDE_INT) INTVAL(operands[1]) < 256"
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@ -1168,9 +1168,9 @@
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""
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)
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(define_insn "*thumb2_movsi_shortim"
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[(set (match_operand:SI 0 "low_register_operand" "=l")
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(match_operand:SI 1 "const_int_operand" "I"))
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(define_insn "*thumb2_mov<mode>_shortim"
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[(set (match_operand:QHSI 0 "low_register_operand" "=l")
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(match_operand:QHSI 1 "const_int_operand" "I"))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_THUMB2 && reload_completed"
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"mov%!\t%0, %1"
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