[ARM][3/3] Expand mod by power of 2
* config/arm/arm.md (*subsi3_compare0): Rename to... (subsi3_compare0): ... This. (modsi3): New define_expand. * config/arm/arm.c (arm_new_rtx_costs, MOD case): Handle case when operand is power of 2. * gcc.target/aarch64/mod_2.x: New file. * gcc.target/aarch64/mod_256.x: Likewise. * gcc.target/arm/mod_2.c: New test. * gcc.target/arm/mod_256.c: Likewise. * gcc.target/aarch64/mod_2.c: Likewise. * gcc.target/aarch64/mod_256.c: Likewise. From-SVN: r227586
This commit is contained in:
Kyrylo Tkachov
Kyrylo Tkachov
parent
4f58fe36c1
commit
956db28eb5
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@ -1,3 +1,11 @@
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2015-09-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/arm.md (*subsi3_compare0): Rename to...
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(subsi3_compare0): ... This.
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(modsi3): New define_expand.
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* config/arm/arm.c (arm_new_rtx_costs, MOD case): Handle case
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when operand is power of 2.
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2015-09-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/aarch64/aarch64.md (mod<mode>3): New define_expand.
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@ -9580,6 +9580,24 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
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return false; /* All arguments must be in registers. */
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case MOD:
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/* MOD by a power of 2 can be expanded as:
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rsbs r1, r0, #0
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and r0, r0, #(n - 1)
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and r1, r1, #(n - 1)
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rsbpl r0, r1, #0. */
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if (CONST_INT_P (XEXP (x, 1))
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&& exact_log2 (INTVAL (XEXP (x, 1))) > 0
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&& mode == SImode)
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{
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*cost += COSTS_N_INSNS (3);
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if (speed_p)
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*cost += 2 * extra_cost->alu.logical
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+ extra_cost->alu.arith;
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return true;
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}
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/* Fall-through. */
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case UMOD:
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*cost = LIBCALL_COST (2);
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return false; /* All arguments must be in registers. */
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@ -1229,7 +1229,7 @@
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""
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)
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(define_insn "*subsi3_compare0"
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(define_insn "subsi3_compare0"
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[(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV
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(minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,r,I")
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@ -11142,6 +11142,75 @@
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""
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)
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;; ARM-specific expansion of signed mod by power of 2
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;; using conditional negate.
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;; For r0 % n where n is a power of 2 produce:
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;; rsbs r1, r0, #0
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;; and r0, r0, #(n - 1)
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;; and r1, r1, #(n - 1)
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;; rsbpl r0, r1, #0
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(define_expand "modsi3"
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[(match_operand:SI 0 "register_operand" "")
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(match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "const_int_operand" "")]
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"TARGET_32BIT"
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{
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HOST_WIDE_INT val = INTVAL (operands[2]);
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if (val <= 0
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|| exact_log2 (val) <= 0)
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FAIL;
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rtx mask = GEN_INT (val - 1);
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/* In the special case of x0 % 2 we can do the even shorter:
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cmp r0, #0
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and r0, r0, #1
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rsblt r0, r0, #0. */
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if (val == 2)
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{
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rtx cc_reg = arm_gen_compare_reg (LT,
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operands[1], const0_rtx, NULL_RTX);
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rtx cond = gen_rtx_LT (SImode, cc_reg, const0_rtx);
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rtx masked = gen_reg_rtx (SImode);
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emit_insn (gen_andsi3 (masked, operands[1], mask));
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emit_move_insn (operands[0],
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gen_rtx_IF_THEN_ELSE (SImode, cond,
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gen_rtx_NEG (SImode,
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masked),
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masked));
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DONE;
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}
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rtx neg_op = gen_reg_rtx (SImode);
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rtx_insn *insn = emit_insn (gen_subsi3_compare0 (neg_op, const0_rtx,
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operands[1]));
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/* Extract the condition register and mode. */
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rtx cmp = XVECEXP (PATTERN (insn), 0, 0);
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rtx cc_reg = SET_DEST (cmp);
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rtx cond = gen_rtx_GE (SImode, cc_reg, const0_rtx);
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emit_insn (gen_andsi3 (operands[0], operands[1], mask));
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rtx masked_neg = gen_reg_rtx (SImode);
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emit_insn (gen_andsi3 (masked_neg, neg_op, mask));
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/* We want a conditional negate here, but emitting COND_EXEC rtxes
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during expand does not always work. Do an IF_THEN_ELSE instead. */
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emit_move_insn (operands[0],
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gen_rtx_IF_THEN_ELSE (SImode, cond,
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gen_rtx_NEG (SImode, masked_neg),
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operands[0]));
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DONE;
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}
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)
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(define_expand "bswapsi2"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
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@ -1,3 +1,12 @@
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2015-09-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* gcc.target/aarch64/mod_2.x: New file.
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* gcc.target/aarch64/mod_256.x: Likewise.
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* gcc.target/arm/mod_2.c: New test.
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* gcc.target/arm/mod_256.c: Likewise.
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* gcc.target/aarch64/mod_2.c: Likewise.
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* gcc.target/aarch64/mod_256.c: Likewise.
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2015-09-09 Jakub Jelinek <jakub@redhat.com>
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PR c++/67504
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@ -0,0 +1,7 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -mcpu=cortex-a57 -save-temps" } */
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#include "mod_2.x"
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/* { dg-final { scan-assembler "csneg\t\[wx\]\[0-9\]*" } } */
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/* { dg-final { scan-assembler-times "and\t\[wx\]\[0-9\]*" 1 } } */
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@ -0,0 +1,5 @@
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int
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f (int x)
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{
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return x % 2;
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}
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@ -0,0 +1,6 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -mcpu=cortex-a57 -save-temps" } */
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#include "mod_256.x"
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/* { dg-final { scan-assembler "csneg\t\[wx\]\[0-9\]*" } } */
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@ -0,0 +1,5 @@
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int
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f (int x)
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{
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return x % 256;
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}
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@ -0,0 +1,8 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target arm32 } */
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/* { dg-options "-O2 -mcpu=cortex-a57 -save-temps" } */
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#include "../aarch64/mod_2.x"
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/* { dg-final { scan-assembler "rsblt\tr\[0-9\]*" } } */
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/* { dg-final { scan-assembler-times "and\tr\[0-9\].*1" 1 } } */
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@ -0,0 +1,8 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target arm32 } */
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/* { dg-options "-O2 -mcpu=cortex-a57 -save-temps" } */
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#include "../aarch64/mod_256.x"
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/* { dg-final { scan-assembler "rsbpl\tr\[0-9\]*" } } */
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