c4x.md: Fix minor formatting problems.
* config/c4x/c4x.md: Fix minor formatting problems. Update docs. (*b, *b_rev, *b_noov, *b_noov_rev, *db, decrement_and_branch_until_zero, rptb_end): Use c4x_output_cbranch to output the instruction sequences. (rpts): Delete. (rptb_top): Provide alternatives to use any register or memory for loop counter. (rptb_end): Emit use of operands rather than assigning them explicitly to the RS and RE registers. From-SVN: r23880
This commit is contained in:
Michael Hayes
Michael Hayes
parent
4271f0030d
commit
959e0a7606
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@ -1,3 +1,15 @@
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Thu Nov 26 17:15:38 1998 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
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* config/c4x/c4x.md: Fix minor formatting problems. Update docs.
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(*b, *b_rev, *b_noov, *b_noov_rev, *db,
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decrement_and_branch_until_zero, rptb_end): Use c4x_output_cbranch
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to output the instruction sequences.
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(rpts): Delete.
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(rptb_top): Provide alternatives to use any register or memory
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for loop counter.
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(rptb_end): Emit use of operands rather than assigning them
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explicitly to the RS and RE registers.
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Thu Nov 26 16:37:59 1998 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
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* config/c4x/c4x.c (c4x_modified_between_p, c4x_mem_set_p,
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@ -23,7 +23,7 @@
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;
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; TODO :
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; Set up addressing macros to handle direct memory references properly
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; Set up addressing macros to handle direct memory references properly.
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; Try using PQImode again for addresses since C30 only uses
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; 24-bit addresses. Ideally GCC would emit different insns
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; for QImode and Pmode, whether Pmode was QImode or PQImode.
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@ -90,16 +90,25 @@
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; b stack pointer SP
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; c other int reg AR0-AR7, IR0-IR1, RC, RS, RE
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; d fp reg R0-R11 (sets CC when dst)
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; e
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; f fp reg R0-R11 (sets CC when dst)
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; g general reg, memory, constant
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; h fp reg R0-R11 (sets CC when dst)
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; h fp reg (HFmode) R0-R11 (sets CC when dst)
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; i immediate int constant
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; j
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; k block count BK
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; l
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; m memory
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; n immediate int constant with known numeric value
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; o offsettable memory
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; p memory address
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; q low fp reg R0-R7 (sets CC when dst)
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; r general reg R0-R11, AR0-AR7, IR0-IR1, RC, RS, RE
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; s immediate int (value not explicit)
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; s immediate int constant (value not explicit)
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; t R0-R1
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; u R2-R3
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; v repeat count reg RC
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; w
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; x index reg IR0-IR1
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; y status (CC) reg ST
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; z data pointer DP
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@ -117,6 +126,8 @@
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; R ARx + 5-bit unsigned disp (C4x only)
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; S ARx + 0, 1, IRx disp
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; T symbol ref (direct)
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; V non offsettable memory
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; X any operand
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; < memory operand with autodecrement addressing
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; > memory operand with autoincrement addressing
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; { memory operand with pre-modify addressing
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@ -1063,6 +1074,14 @@
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(const_int 1) (const_int 0))]
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(const_int 0)))
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;
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; C4x INSN PATTERNS:
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;
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; Note that the movMM and addP patterns can be called during reload
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; so we need to take special care with theses patterns since
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; we cannot blindly clobber CC or generate new pseudo registers.
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;
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; TWO OPERAND INTEGER INSTRUCTIONS
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;
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@ -1110,6 +1129,7 @@
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;
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; LDIU/LDA/STI/STIK
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;
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; The following moves will not set the condition codes register.
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;
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@ -1596,7 +1616,8 @@
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; Default to int16 data attr.
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; This pattern is required primarily for manipulating the stack pointer
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; where GCC doesn't expect CC to be clobbered.
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; where GCC doesn't expect CC to be clobbered or for calculating
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; addresses during reload.
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(define_insn "addqi3_noclobber"
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[(set (match_operand:QI 0 "std_reg_operand" "=c,?c,c")
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(plus:QI (match_operand:QI 1 "src_operand" "%rR,rS<>,0")
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@ -1765,13 +1786,13 @@
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if (operands[1] == operands[2])
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{
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/* Do the squaring operation in-line. */
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emit_insn (gen_sqrqi2_inline(operands[0], operands[1]));
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emit_insn (gen_sqrqi2_inline (operands[0], operands[1]));
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DONE;
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}
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if (TARGET_INLINE)
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{
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emit_insn (gen_mulqi3_inline(operands[0], operands[1],
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operands[2]));
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emit_insn (gen_mulqi3_inline (operands[0], operands[1],
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operands[2]));
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DONE;
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}
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c4x_emit_libcall3 (MULQI3_LIBCALL, MULT, QImode, operands);
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@ -3261,7 +3282,7 @@
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FAIL;
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else
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{
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emit_insn (gen_sqrtqf2_inline( operands[0], operands[1]));
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emit_insn (gen_sqrtqf2_inline (operands[0], operands[1]));
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DONE;
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}
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")
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@ -3506,7 +3527,7 @@
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}
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else
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{
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emit_insn (gen_divqf3_inline( operands[0], operands[1], operands[2]));
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emit_insn (gen_divqf3_inline (operands[0], operands[1], operands[2]));
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DONE;
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}
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")
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@ -3533,10 +3554,10 @@
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[(reg:CC_NOOV 21) (const_int 0)])
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(match_operand:QI 2 "src_operand" "g,0")
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(match_operand:QI 3 "src_operand" "0,g")))]
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"GET_CODE(operands[1]) != LE
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&& GET_CODE(operands[1]) != GE
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&& GET_CODE(operands[1]) != LT
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&& GET_CODE(operands[1]) != GT"
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"GET_CODE (operands[1]) != LE
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&& GET_CODE (operands[1]) != GE
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&& GET_CODE (operands[1]) != LT
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&& GET_CODE (operands[1]) != GT"
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"@
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ldi%1\\t%2,%0
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ldi%I1\\t%3,%0"
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@ -3581,10 +3602,10 @@
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[(reg:CC_NOOV 21) (const_int 0)])
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(match_operand:QF 2 "src_operand" "fmH,0")
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(match_operand:QF 3 "src_operand" "0,fmH")))]
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"GET_CODE(operands[1]) != LE
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&& GET_CODE(operands[1]) != GE
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&& GET_CODE(operands[1]) != LT
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&& GET_CODE(operands[1]) != GT"
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"GET_CODE (operands[1]) != LE
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&& GET_CODE (operands[1]) != GE
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&& GET_CODE (operands[1]) != LT
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&& GET_CODE (operands[1]) != GT"
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"@
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ldf%1\\t%2,%0
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ldf%I1\\t%3,%0"
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@ -3818,10 +3839,10 @@
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(define_insn "*mulqf3_addqf3_clobber"
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[(set (match_operand:QF 0 "r0r1_reg_operand" "=t")
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(mult:QF (match_operand:QF 1 "parallel_operand" "S<>q")
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(mult:QF (match_operand:QF 1 "parallel_operand" "%S<>q")
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(match_operand:QF 2 "parallel_operand" "S<>q")))
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(set (match_operand:QF 3 "r2r3_reg_operand" "=u")
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(plus:QF (match_operand:QF 4 "parallel_operand" "S<>q")
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(plus:QF (match_operand:QF 4 "parallel_operand" "%S<>q")
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(match_operand:QF 5 "parallel_operand" "S<>q")))
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(clobber (reg:CC 21))]
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"TARGET_PARALLEL_MPY && valid_parallel_operands_6 (operands, QFmode)"
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@ -4134,7 +4155,7 @@
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(pc)))]
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""
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"*
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return c4x_output_cbranch (0, insn);"
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return c4x_output_cbranch (\"b%0\", insn);"
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[(set_attr "type" "jmpc")])
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(define_insn "*b_rev"
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@ -4144,7 +4165,7 @@
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(label_ref (match_operand 1 "" ""))))]
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""
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"*
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return c4x_output_cbranch (1, insn);"
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return c4x_output_cbranch (\"b%I0\", insn);"
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[(set_attr "type" "jmpc")])
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(define_insn "*b_noov"
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@ -4152,12 +4173,12 @@
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[(reg:CC_NOOV 21) (const_int 0)])
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(label_ref (match_operand 1 "" ""))
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(pc)))]
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"GET_CODE(operands[0]) != LE
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&& GET_CODE(operands[0]) != GE
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&& GET_CODE(operands[0]) != LT
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&& GET_CODE(operands[0]) != GT"
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"GET_CODE (operands[0]) != LE
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&& GET_CODE (operands[0]) != GE
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&& GET_CODE (operands[0]) != LT
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&& GET_CODE (operands[0]) != GT"
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"*
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return c4x_output_cbranch (0, insn);"
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return c4x_output_cbranch (\"b%0\", insn);"
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[(set_attr "type" "jmpc")])
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(define_insn "*b_noov_rev"
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@ -4165,12 +4186,12 @@
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[(reg:CC_NOOV 21) (const_int 0)])
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(pc)
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(label_ref (match_operand 1 "" ""))))]
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"GET_CODE(operands[0]) != LE
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&& GET_CODE(operands[0]) != GE
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&& GET_CODE(operands[0]) != LT
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&& GET_CODE(operands[0]) != GT"
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"GET_CODE (operands[0]) != LE
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&& GET_CODE (operands[0]) != GE
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&& GET_CODE (operands[0]) != LT
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&& GET_CODE (operands[0]) != GT"
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"*
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return c4x_output_cbranch (1, insn);"
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return c4x_output_cbranch (\"b%I0\", insn);"
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[(set_attr "type" "jmpc")])
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(define_expand "beq"
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@ -4382,10 +4403,10 @@
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[(reg:CC_NOOV 21) (const_int 0)])
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(return)
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(pc)))]
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"GET_CODE(operands[0]) != LE
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&& GET_CODE(operands[0]) != GE
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&& GET_CODE(operands[0]) != LT
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&& GET_CODE(operands[0]) != GT
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"GET_CODE (operands[0]) != LE
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&& GET_CODE (operands[0]) != GE
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&& GET_CODE (operands[0]) != LT
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&& GET_CODE (operands[0]) != GT
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&& c4x_null_epilogue_p ()"
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"rets%0"
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[(set_attr "type" "rets")])
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@ -4406,10 +4427,10 @@
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[(reg:CC_NOOV 21) (const_int 0)])
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(pc)
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(return)))]
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"GET_CODE(operands[0]) != LE
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&& GET_CODE(operands[0]) != GE
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&& GET_CODE(operands[0]) != LT
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&& GET_CODE(operands[0]) != GT
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"GET_CODE (operands[0]) != LE
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&& GET_CODE (operands[0]) != GE
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&& GET_CODE (operands[0]) != LT
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&& GET_CODE (operands[0]) != GT
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&& c4x_null_epilogue_p ()"
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"rets%I0"
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[(set_attr "type" "rets")])
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@ -4434,55 +4455,50 @@
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; have an option to disable this instruction.
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(define_insn "*db"
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[(set (pc)
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(if_then_else (ne (match_operand:QI 0 "addr_reg_operand" "+a,!d,!m")
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(if_then_else (ne (match_operand:QI 2 "addr_reg_operand" "0,0,0,0")
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(const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))
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(set (match_dup 0)
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(set (match_operand:QI 0 "addr_reg_operand" "+a,?*d,??*r,!m")
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(plus:QI (match_dup 0)
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(const_int -1)))]
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(const_int -1)))
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(clobber (reg:CC_NOOV 21))]
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"TARGET_DB && TARGET_LOOP_UNSIGNED"
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"*
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if (IS_ADDR_REG (REGNO (operands[0])))
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{
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return \"dbu%#\\t%0,%l1\";
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}
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else if (IS_EXT_REG (REGNO (operands[0])))
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{
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return \"subi\\t1,%0\\n\\tbge%#\\t%l1\";
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}
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if (which_alternative == 0)
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return \"dbu%#\\t%0,%l1\";
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else if (which_alternative == 1)
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return c4x_output_cbranch (\"subi\\t1,%0\\n\\tbge\", insn);
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else if (which_alternative == 2)
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return c4x_output_cbranch (\"subi\\t1,%0\\n\\tcmpi\\t0,%0\\n\\tbge\", insn);
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else
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{
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return \"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\tpop\\tr0\\n\\tbhs%#\\t%l1\";
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}
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return c4x_output_cbranch (\"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\tpop\\tr0\\n\\tbhs\", insn);
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"
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[(set_attr "type" "db")])
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[(set_attr "type" "db,jmpc,jmpc,jmpc")])
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(define_insn "decrement_and_branch_until_zero"
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[(set (pc)
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(if_then_else (ge (plus:QI (match_operand:QI 0 "addr_reg_operand" "+a,!d,!m")
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(const_int -1)) (const_int 0))
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(if_then_else (ge (plus:QI (match_operand:QI 2 "addr_reg_operand" "0,0,0,0")
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(const_int -1))
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(const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))
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(set (match_dup 0)
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(set (match_operand:QI 0 "addr_reg_operand" "+a,?*d,??*r,!m")
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(plus:QI (match_dup 0)
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(const_int -1)))]
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(const_int -1)))
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(clobber (reg:CC_NOOV 21))]
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"TARGET_DB && find_reg_note (insn, REG_NONNEG, 0)"
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"*
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if (IS_ADDR_REG (REGNO (operands[0])))
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{
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return \"dbu%#\\t%0,%l1\";
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}
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else if (IS_EXT_REG (REGNO (operands[0])))
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{
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return \"subi\\t1,%0\\n\\tbge%#\\t%l1\";
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}
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if (which_alternative == 0)
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return \"dbu%#\\t%0,%l1\";
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else if (which_alternative == 1)
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return c4x_output_cbranch (\"subi\\t1,%0\\n\\tbge\", insn);
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else if (which_alternative == 2)
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return c4x_output_cbranch (\"subi\\t1,%0\\n\\tcmpi\\t0,%0\\n\\tbge\", insn);
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else
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{
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return \"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\t\\tpop\\tr0\\n\\tbhs%#\\t%l1\";
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}
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return c4x_output_cbranch (\"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\tpop\\tr0\\n\\tbhs\", insn);
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"
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[(set_attr "type" "db")])
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[(set_attr "type" "db,jmpc,jmpc,jmpc")])
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;
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; MISC INSTRUCTIONS
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@ -4497,25 +4513,13 @@
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"nop")
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; Default to misc type attr.
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;
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; RPTS
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;
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; Should we disallow RPTS if we get a silly number of shifts?
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(define_insn "rpts"
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[(set (reg:QI 27)
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(unspec [(match_operand:QI 0 "src_operand" "g")] 2))
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(clobber (reg:QI 25))
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(clobber (reg:QI 26))]
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""
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"rpts\\t%0"
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[(set_attr "type" "repeat")])
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;
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; RPTB
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;
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(define_insn "rptb_top"
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[(set (reg:QI 25) (label_ref (match_operand 0 "" "")))
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(set (reg:QI 26) (label_ref (match_operand 1 "" "")))]
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[(use (label_ref (match_operand 0 "" "")))
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(use (label_ref (match_operand 1 "" "")))]
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""
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"*
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return !final_sequence && c4x_rptb_rpts_p (insn, operands[0])
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@ -4523,23 +4527,45 @@
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"
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[(set_attr "type" "repeat_top")])
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(define_insn "rptb_end"
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[(set (pc)
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(if_then_else (ge (match_operand:QI 0 "rc_reg_operand" "v")
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(const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))
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(set (match_dup 0)
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(plus:QI (match_dup 0)
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(const_int -1)))
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; This pattern needs to be emitted at the start of the loop to
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; say that RS and RE are loaded.
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(define_insn "init_branch_on_count"
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[(unspec[(match_operand:QI 0 "rc_reg_operand" "v")] 22)
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(clobber (reg:QI 25))
|
||||
(clobber (reg:QI 26))]
|
||||
""
|
||||
"*
|
||||
return c4x_rptb_nop_p(insn) ? \"nop\" : \"\";"
|
||||
""
|
||||
[(set_attr "type" "repeat")])
|
||||
|
||||
; The RS (25) and RE (26) registers must be unviolate from the top of the loop
|
||||
; to here.
|
||||
(define_insn "rptb_end"
|
||||
[(set (pc)
|
||||
(if_then_else (ge (match_operand:QI 2 "rc_reg_operand" "0,0,0,0,0")
|
||||
(const_int 0))
|
||||
(label_ref (match_operand 1 "" ""))
|
||||
(pc)))
|
||||
(set (match_operand:QI 0 "rc_reg_operand" "+v,*a,*d,*x*k,*m")
|
||||
(plus:QI (match_dup 0)
|
||||
(const_int -1)))
|
||||
(use (reg:QI 25))
|
||||
(use (reg:QI 26))
|
||||
(clobber (reg:CC_NOOV 21))]
|
||||
""
|
||||
"*
|
||||
if (which_alternative == 0)
|
||||
return c4x_rptb_nop_p (insn) ? \"nop\" : \"\";
|
||||
else if (which_alternative == 1)
|
||||
return \"dbu%#\\t%0,%l1\";
|
||||
else if (which_alternative == 2)
|
||||
return c4x_output_cbranch (\"subi\\t1,%0\\n\\tbge\", insn);
|
||||
else if (which_alternative == 3)
|
||||
return c4x_output_cbranch (\"subi\\t1,%0\\n\\tcmpi\\t0,%0\\n\\tbge\", insn);
|
||||
else
|
||||
return c4x_output_cbranch (\"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\tpop\\tr0\\n\\tbhs\", insn);
|
||||
"
|
||||
[(set_attr "type" "repeat,db,jmpc,jmpc,jmpc")])
|
||||
|
||||
|
||||
(define_expand "decrement_and_branch_on_count"
|
||||
[(parallel [(set (pc)
|
||||
|
|
@ -4547,9 +4573,12 @@
|
|||
(const_int 0))
|
||||
(label_ref (match_operand 1 "" ""))
|
||||
(pc)))
|
||||
(set (match_dup 0) (plus:QI (match_dup 0) (const_int -1)))
|
||||
(clobber (reg:QI 25))
|
||||
(clobber (reg:QI 26))])]
|
||||
(set (match_dup 0)
|
||||
(plus:QI (match_dup 0)
|
||||
(const_int -1)))
|
||||
(use (reg:QI 25))
|
||||
(use (reg:QI 26))
|
||||
(clobber (reg:CC_NOOV 21))])]
|
||||
""
|
||||
"")
|
||||
|
||||
|
|
@ -4647,7 +4676,7 @@
|
|||
int len = INTVAL (operands[2]);
|
||||
|
||||
output_asm_insn (\"ldiu\\t*%1++,%4\", operands);
|
||||
if (TARGET_RPTS_CYCLES(len))
|
||||
if (TARGET_RPTS_CYCLES (len))
|
||||
{
|
||||
output_asm_insn (\"rpts\\t%2-2\", operands);
|
||||
output_asm_insn (\"sti\\t%4,*%0++\", operands);
|
||||
|
|
@ -4665,7 +4694,7 @@
|
|||
}
|
||||
}
|
||||
"
|
||||
[(set_attr "type" "repeat")])
|
||||
[(set_attr "type" "multi")])
|
||||
|
||||
; Operand 2 is the count, operand 3 is the alignment.
|
||||
(define_expand "movstrqi"
|
||||
|
|
@ -4684,8 +4713,8 @@
|
|||
FAIL; /* Try to call _memcpy */
|
||||
}
|
||||
|
||||
operands[0] = copy_to_mode_reg (Pmode, XEXP(operands[0], 0));
|
||||
operands[1] = copy_to_mode_reg (Pmode, XEXP(operands[1], 0));
|
||||
operands[0] = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
|
||||
operands[1] = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
|
||||
tmp = gen_reg_rtx (QImode);
|
||||
if (INTVAL (operands[2]) < 8)
|
||||
emit_insn (gen_movstrqi_small (operands[0], operands[1], operands[2],
|
||||
|
|
@ -4733,8 +4762,8 @@
|
|||
{
|
||||
FAIL;
|
||||
}
|
||||
operands[1] = copy_to_mode_reg (Pmode, XEXP(operands[1], 0));
|
||||
operands[2] = copy_to_mode_reg (Pmode, XEXP(operands[2], 0));
|
||||
operands[1] = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
|
||||
operands[2] = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
|
||||
operands[5] = gen_reg_rtx (QImode);
|
||||
}")
|
||||
|
||||
|
|
@ -5116,7 +5145,7 @@
|
|||
FAIL;
|
||||
else
|
||||
{
|
||||
emit_insn (gen_sqrthf2_inline( operands[0], operands[1]));
|
||||
emit_insn (gen_sqrthf2_inline (operands[0], operands[1]));
|
||||
DONE;
|
||||
}
|
||||
")
|
||||
|
|
@ -5269,7 +5298,7 @@
|
|||
}
|
||||
else
|
||||
{
|
||||
emit_insn (gen_divhf3_inline( operands[0], operands[1], operands[2]));
|
||||
emit_insn (gen_divhf3_inline (operands[0], operands[1], operands[2]));
|
||||
DONE;
|
||||
}
|
||||
")
|
||||
|
|
@ -6122,14 +6151,15 @@
|
|||
(parallel
|
||||
[(set (pc)
|
||||
(if_then_else
|
||||
(ge (plus:QI (match_operand:QI 0 "addr_reg_operand" "+a")
|
||||
(ge (plus:QI (match_operand:QI 4 "addr_reg_operand" "0")
|
||||
(const_int -1))
|
||||
(const_int 0))
|
||||
(label_ref (match_operand 1 "" ""))
|
||||
(pc)))
|
||||
(set (match_dup 0)
|
||||
(set (match_operand:QI 0 "addr_reg_operand" "+a")
|
||||
(plus:QI (match_dup 0)
|
||||
(const_int -1)))])]
|
||||
(const_int -1)))
|
||||
(clobber (reg:CC_NOOV 21))])]
|
||||
"!c4x_label_conflict (insn, operands[2], operands[1])"
|
||||
"db%I3\\t%0,%l1\\n\\tb%3\\t%l2")
|
||||
|
||||
|
|
@ -6141,13 +6171,14 @@
|
|||
(parallel
|
||||
[(set (pc)
|
||||
(if_then_else
|
||||
(ne (match_operand:QI 0 "addr_reg_operand" "+a")
|
||||
(ne (match_operand:QI 4 "addr_reg_operand" "0")
|
||||
(const_int 0))
|
||||
(label_ref (match_operand 1 "" ""))
|
||||
(pc)))
|
||||
(set (match_dup 0)
|
||||
(set (match_operand:QI 0 "addr_reg_operand" "+a")
|
||||
(plus:QI (match_dup 0)
|
||||
(const_int -1)))])]
|
||||
(const_int -1)))
|
||||
(clobber (reg:CC_NOOV 21))])]
|
||||
"!c4x_label_conflict (insn, operands[2], operands[1])"
|
||||
"db%I3\\t%0,%l1\\n\\tb%3\\t%l2")
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue