i386.c (ix86_fpmath, [...]): New.
Fri Dec 14 12:05:14 CET 2001 Jan Hubicka <jh@suse.cz> * i386.c (ix86_fpmath, ix86_fpmath_string): New. (override_option): Set ix86_fpmath. * i386.h (MASK_MIX_SSE_I387): Remove. (TARGET_SSE_MATH): New. (TARGET_MIX_SSE_I387): Use ix86_fpmath. (TARGET_SWITCHES): Remove "mix-sse-i387". (fpmath_unit): New enum. (ix86_fpmath, ix86_fpmath_string): Declare. * i386.md (swapsf): Fix condition. (add?f, sub?f, mul?f, div?f, sqrt?f, min?f): Use TARGET_SSE_MATH. (fp_?f_*_nosse): New. (fp_*): Use TARGET_SSE_MATH. * invoke.texi (-mfpmath): Document. (-msse2): Add. From-SVN: r47999
This commit is contained in:
Jan Hubicka
Jan Hubicka
parent
009c32817a
commit
965f5423cd
@ -1,3 +1,20 @@
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Fri Dec 14 12:05:14 CET 2001 Jan Hubicka <jh@suse.cz>
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* i386.c (ix86_fpmath, ix86_fpmath_string): New.
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(override_option): Set ix86_fpmath.
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* i386.h (MASK_MIX_SSE_I387): Remove.
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(TARGET_SSE_MATH): New.
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(TARGET_MIX_SSE_I387): Use ix86_fpmath.
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(TARGET_SWITCHES): Remove "mix-sse-i387".
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(fpmath_unit): New enum.
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(ix86_fpmath, ix86_fpmath_string): Declare.
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* i386.md (swapsf): Fix condition.
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(add?f, sub?f, mul?f, div?f, sqrt?f, min?f): Use TARGET_SSE_MATH.
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(fp_?f_*_nosse): New.
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(fp_*): Use TARGET_SSE_MATH.
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* invoke.texi (-mfpmath): Document.
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(-msse2): Add.
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2001-12-14 Jason Merrill <jason@redhat.com>
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* dwarf2out.c (output_die): Print the string in the comment for
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@ -578,12 +578,16 @@ enum cmodel ix86_cmodel;
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/* which cpu are we scheduling for */
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enum processor_type ix86_cpu;
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/* which unit we are generating floating point math for */
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enum fpmath_unit ix86_fpmath;
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/* which instruction set architecture to use. */
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int ix86_arch;
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/* Strings to hold which cpu and instruction set architecture to use. */
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const char *ix86_cpu_string; /* for -mcpu=<xxx> */
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const char *ix86_arch_string; /* for -march=<xxx> */
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const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */
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/* # of registers to use to pass arguments. */
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const char *ix86_regparm_string;
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@ -1066,8 +1070,45 @@ override_options ()
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if (TARGET_RTD)
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error ("-mrtd calling convention not supported in the 64bit mode");
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/* Enable by default the SSE and MMX builtins. */
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target_flags |= MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE;
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target_flags |= (MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE);
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ix86_fpmath = FPMATH_SSE;
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}
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else
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ix86_fpmath = FPMATH_387;
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if (ix86_fpmath_string != 0)
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{
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if (! strcmp (ix86_fpmath_string, "387"))
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ix86_fpmath = FPMATH_387;
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else if (! strcmp (ix86_fpmath_string, "sse"))
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{
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if (!TARGET_SSE)
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{
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warning ("SSE instruction set disabled, using 387 arithmetics");
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ix86_fpmath = FPMATH_387;
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}
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else
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ix86_fpmath = FPMATH_SSE;
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}
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else if (! strcmp (ix86_fpmath_string, "387,sse")
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|| ! strcmp (ix86_fpmath_string, "sse,387"))
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{
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if (!TARGET_SSE)
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{
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warning ("SSE instruction set disabled, using 387 arithmetics");
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ix86_fpmath = FPMATH_387;
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}
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else if (!TARGET_80387)
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{
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warning ("387 instruction set disabled, using SSE arithmetics");
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ix86_fpmath = FPMATH_SSE;
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}
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else
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ix86_fpmath = FPMATH_SSE | FPMATH_387;
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}
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else
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error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
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}
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/* It makes no sense to ask for just SSE builtins, so MMX is also turned
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on by -msse. */
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@ -8117,8 +8158,8 @@ ix86_expand_fp_movcc (operands)
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/* For SF/DFmode conditional moves based on comparisons
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in same mode, we may want to use SSE min/max instructions. */
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if (((TARGET_SSE && GET_MODE (operands[0]) == SFmode)
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|| (TARGET_SSE2 && GET_MODE (operands[0]) == DFmode))
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if (((TARGET_SSE_MATH && GET_MODE (operands[0]) == SFmode)
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|| (TARGET_SSE2 && TARGET_SSE_MATH && GET_MODE (operands[0]) == DFmode))
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&& GET_MODE (ix86_compare_op0) == GET_MODE (operands[0])
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/* The SSE comparisons does not support the LTGT/UNEQ pair. */
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&& (!TARGET_IEEE_FP
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@ -272,7 +272,9 @@ extern const int x86_epilogue_using_move, x86_decompose_lea;
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#define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
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#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
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#define TARGET_MIX_SSE_I387 ((target_flags & MASK_MIX_SSE_I387) != 0)
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#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
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#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
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&& (ix86_fpmath & FPMATH_387))
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#define TARGET_MMX ((target_flags & MASK_MMX) != 0)
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#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
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#define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
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@ -365,10 +367,6 @@ extern const int x86_epilogue_using_move, x86_decompose_lea;
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{ "no-sse2", -MASK_SSE2, N_("") }, \
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{ "no-sse2", MASK_SSE2_SET, \
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N_("Do not support MMX, SSE and SSE2 builtins and code generation") }, \
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{ "mix-sse-i387", MASK_MIX_SSE_I387, \
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N_("Use both SSE and i387 instruction sets for floating point arithmetics") },\
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{ "no-mix-sse-i387", -MASK_MIX_SSE_I387, \
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N_("Do not use both SSE and i387 instruction sets for floating point arithmetics") },\
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{ "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
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N_("sizeof(long double) is 16") }, \
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{ "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
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@ -404,8 +402,14 @@ enum processor_type
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PROCESSOR_PENTIUM4,
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PROCESSOR_max
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};
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enum fpmath_unit
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{
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FPMATH_387 = 1,
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FPMATH_SSE = 2
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};
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extern enum processor_type ix86_cpu;
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extern enum fpmath_unit ix86_fpmath;
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extern int ix86_arch;
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@ -421,6 +425,8 @@ extern int ix86_arch;
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#define TARGET_OPTIONS \
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{ { "cpu=", &ix86_cpu_string, \
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N_("Schedule code for given CPU")}, \
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{ "fpmath=", &ix86_fpmath_string, \
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N_("Generate floating point mathematics using given instruction set")},\
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{ "arch=", &ix86_arch_string, \
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N_("Generate code for given CPU")}, \
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{ "regparm=", &ix86_regparm_string, \
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@ -1271,7 +1277,7 @@ enum reg_class
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#define SSE_REG_P(n) (REG_P (n) && SSE_REGNO_P (REGNO (n)))
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#define SSE_FLOAT_MODE_P(m) \
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((TARGET_SSE && (m) == SFmode) || (TARGET_SSE2 && (m) == DFmode))
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((TARGET_SSE_MATH && (m) == SFmode) || (TARGET_SSE2 && (m) == DFmode))
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#define MMX_REGNO_P(n) ((n) >= FIRST_MMX_REG && (n) <= LAST_MMX_REG)
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#define MMX_REG_P(xop) (REG_P (xop) && MMX_REGNO_P (REGNO (xop)))
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@ -3112,6 +3118,7 @@ extern enum cmodel ix86_cmodel;
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/* Variables in i386.c */
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extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */
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extern const char *ix86_arch_string; /* for -march=<xxx> */
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extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */
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extern const char *ix86_regparm_string; /* # registers to use to pass args */
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extern const char *ix86_align_loops_string; /* power of two alignment for loops */
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extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */
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@ -2776,7 +2776,7 @@
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(match_operand:SF 1 "register_operand" "+f"))
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(set (match_dup 1)
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(match_dup 0))]
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"reload_completed || !TARGET_SSE2"
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"reload_completed || !TARGET_SSE"
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{
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if (STACK_TOP_P (operands[0]))
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return "fxch\t%1";
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@ -6890,14 +6890,14 @@
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[(set (match_operand:DF 0 "register_operand" "")
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(plus:DF (match_operand:DF 1 "register_operand" "")
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(match_operand:DF 2 "nonimmediate_operand" "")))]
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"TARGET_80387 || TARGET_SSE2"
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"TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
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"")
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(define_expand "addsf3"
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[(set (match_operand:SF 0 "register_operand" "")
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(plus:SF (match_operand:SF 1 "register_operand" "")
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(match_operand:SF 2 "nonimmediate_operand" "")))]
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"TARGET_80387 || TARGET_SSE"
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"TARGET_80387 || TARGET_SSE_MATH"
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"")
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;; Subtract instructions
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@ -7207,14 +7207,14 @@
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[(set (match_operand:DF 0 "register_operand" "")
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(minus:DF (match_operand:DF 1 "register_operand" "")
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(match_operand:DF 2 "nonimmediate_operand" "")))]
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"TARGET_80387 || TARGET_SSE2"
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"TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
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"")
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(define_expand "subsf3"
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[(set (match_operand:SF 0 "register_operand" "")
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(minus:SF (match_operand:SF 1 "register_operand" "")
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(match_operand:SF 2 "nonimmediate_operand" "")))]
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"TARGET_80387 || TARGET_SSE"
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"TARGET_80387 || TARGET_SSE_MATH"
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"")
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;; Multiply instructions
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@ -7533,14 +7533,14 @@
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[(set (match_operand:DF 0 "register_operand" "")
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(mult:DF (match_operand:DF 1 "register_operand" "")
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(match_operand:DF 2 "nonimmediate_operand" "")))]
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"TARGET_80387 || TARGET_SSE2"
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"TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
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"")
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(define_expand "mulsf3"
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[(set (match_operand:SF 0 "register_operand" "")
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(mult:SF (match_operand:SF 1 "register_operand" "")
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(match_operand:SF 2 "nonimmediate_operand" "")))]
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"TARGET_80387 || TARGET_SSE"
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"TARGET_80387 || TARGET_SSE_MATH"
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"")
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;; Divide instructions
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@ -7587,14 +7587,14 @@
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[(set (match_operand:DF 0 "register_operand" "")
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(div:DF (match_operand:DF 1 "register_operand" "")
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(match_operand:DF 2 "nonimmediate_operand" "")))]
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"TARGET_80387 || TARGET_SSE2"
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"TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
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"")
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(define_expand "divsf3"
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[(set (match_operand:SF 0 "register_operand" "")
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(div:SF (match_operand:SF 1 "register_operand" "")
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(match_operand:SF 2 "nonimmediate_operand" "")))]
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"TARGET_80387 || TARGET_SSE"
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"TARGET_80387 || TARGET_SSE_MATH"
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"")
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;; Remainder instructions.
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@ -13849,12 +13849,26 @@
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;; Gcc is slightly more smart about handling normal two address instructions
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;; so use special patterns for add and mull.
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(define_insn "*fop_sf_comm_nosse"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(match_operator:SF 3 "binary_fp_operator"
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[(match_operand:SF 1 "register_operand" "%0")
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(match_operand:SF 2 "nonimmediate_operand" "fm")]))]
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"TARGET_80387 && !TARGET_SSE_MATH
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&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
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"* return output_387_binary_op (insn, operands);"
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[(set (attr "type")
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(if_then_else (match_operand:SF 3 "mult_operator" "")
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(const_string "fmul")
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(const_string "fop")))
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(set_attr "mode" "SF")])
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(define_insn "*fop_sf_comm"
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[(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
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(match_operator:SF 3 "binary_fp_operator"
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[(match_operand:SF 1 "register_operand" "%0,0")
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(match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
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"TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
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"TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
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&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
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"* return output_387_binary_op (insn, operands);"
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[(set (attr "type")
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@ -13870,17 +13884,31 @@
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(match_operator:SF 3 "binary_fp_operator"
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[(match_operand:SF 1 "register_operand" "%0")
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(match_operand:SF 2 "nonimmediate_operand" "xm")]))]
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"TARGET_SSE && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
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"TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
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"* return output_387_binary_op (insn, operands);"
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[(set_attr "type" "sse")
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(set_attr "mode" "SF")])
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(define_insn "*fop_df_comm_nosse"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(match_operator:DF 3 "binary_fp_operator"
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[(match_operand:DF 1 "register_operand" "%0")
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(match_operand:DF 2 "nonimmediate_operand" "fm")]))]
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"TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
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&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
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"* return output_387_binary_op (insn, operands);"
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[(set (attr "type")
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(if_then_else (match_operand:SF 3 "mult_operator" "")
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(const_string "fmul")
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(const_string "fop")))
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(set_attr "mode" "DF")])
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(define_insn "*fop_df_comm"
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[(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
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(match_operator:DF 3 "binary_fp_operator"
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[(match_operand:DF 1 "register_operand" "%0,0")
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(match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
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"TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
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"TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
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&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
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"* return output_387_binary_op (insn, operands);"
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[(set (attr "type")
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@ -13896,7 +13924,7 @@
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(match_operator:DF 3 "binary_fp_operator"
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[(match_operand:DF 1 "register_operand" "%0")
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(match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
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"TARGET_SSE2
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"TARGET_SSE2 && TARGET_SSE_MATH
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&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
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"* return output_387_binary_op (insn, operands);"
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[(set_attr "type" "sse")
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@ -13929,12 +13957,30 @@
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(const_string "fop")))
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(set_attr "mode" "XF")])
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(define_insn "*fop_sf_1_nosse"
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[(set (match_operand:SF 0 "register_operand" "=f,f")
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(match_operator:SF 3 "binary_fp_operator"
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[(match_operand:SF 1 "nonimmediate_operand" "0,fm")
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(match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
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"TARGET_80387 && !TARGET_SSE_MATH
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&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"* return output_387_binary_op (insn, operands);"
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[(set (attr "type")
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(cond [(match_operand:SF 3 "mult_operator" "")
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(const_string "fmul")
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(match_operand:SF 3 "div_operator" "")
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(const_string "fdiv")
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]
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(const_string "fop")))
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(set_attr "mode" "SF")])
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(define_insn "*fop_sf_1"
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[(set (match_operand:SF 0 "register_operand" "=f,f,x")
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(match_operator:SF 3 "binary_fp_operator"
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[(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
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(match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
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"TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
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"TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
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&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
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&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
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"* return output_387_binary_op (insn, operands);"
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@ -13954,7 +14000,7 @@
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(match_operator:SF 3 "binary_fp_operator"
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[(match_operand:SF 1 "register_operand" "0")
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(match_operand:SF 2 "nonimmediate_operand" "xm")]))]
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"TARGET_SSE
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"TARGET_SSE_MATH
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&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
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"* return output_387_binary_op (insn, operands);"
|
||||
[(set_attr "type" "sse")
|
||||
@ -13966,7 +14012,7 @@
|
||||
(match_operator:SF 3 "binary_fp_operator"
|
||||
[(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
|
||||
(match_operand:SF 2 "register_operand" "0,0")]))]
|
||||
"TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
|
||||
"TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
|
||||
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
|
||||
[(set (attr "type")
|
||||
(cond [(match_operand:SF 3 "mult_operator" "")
|
||||
@ -13984,7 +14030,7 @@
|
||||
(match_operator:SF 3 "binary_fp_operator"
|
||||
[(match_operand:SF 1 "register_operand" "0,0")
|
||||
(float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
|
||||
"TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
|
||||
"TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
|
||||
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
|
||||
[(set (attr "type")
|
||||
(cond [(match_operand:SF 3 "mult_operator" "")
|
||||
@ -13997,12 +14043,31 @@
|
||||
(set_attr "ppro_uops" "many")
|
||||
(set_attr "mode" "SI")])
|
||||
|
||||
(define_insn "*fop_df_1_nosse"
|
||||
[(set (match_operand:DF 0 "register_operand" "=f,f")
|
||||
(match_operator:DF 3 "binary_fp_operator"
|
||||
[(match_operand:DF 1 "nonimmediate_operand" "0,fm")
|
||||
(match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
|
||||
"TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
|
||||
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"* return output_387_binary_op (insn, operands);"
|
||||
[(set (attr "type")
|
||||
(cond [(match_operand:DF 3 "mult_operator" "")
|
||||
(const_string "fmul")
|
||||
(match_operand:DF 3 "div_operator" "")
|
||||
(const_string "fdiv")
|
||||
]
|
||||
(const_string "fop")))
|
||||
(set_attr "mode" "DF")])
|
||||
|
||||
|
||||
(define_insn "*fop_df_1"
|
||||
[(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
|
||||
(match_operator:DF 3 "binary_fp_operator"
|
||||
[(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
|
||||
(match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
|
||||
"TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
|
||||
"TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
|
||||
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
|
||||
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
|
||||
"* return output_387_binary_op (insn, operands);"
|
||||
@ -14022,7 +14087,7 @@
|
||||
(match_operator:DF 3 "binary_fp_operator"
|
||||
[(match_operand:DF 1 "register_operand" "0")
|
||||
(match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
|
||||
"TARGET_SSE
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH
|
||||
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
|
||||
"* return output_387_binary_op (insn, operands);"
|
||||
[(set_attr "type" "sse")])
|
||||
@ -14033,7 +14098,7 @@
|
||||
(match_operator:DF 3 "binary_fp_operator"
|
||||
[(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
|
||||
(match_operand:DF 2 "register_operand" "0,0")]))]
|
||||
"TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
|
||||
"TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
|
||||
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
|
||||
[(set (attr "type")
|
||||
(cond [(match_operand:DF 3 "mult_operator" "")
|
||||
@ -14051,7 +14116,7 @@
|
||||
(match_operator:DF 3 "binary_fp_operator"
|
||||
[(match_operand:DF 1 "register_operand" "0,0")
|
||||
(float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
|
||||
"TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
|
||||
"TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
|
||||
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
|
||||
[(set (attr "type")
|
||||
(cond [(match_operand:DF 3 "mult_operator" "")
|
||||
@ -14087,7 +14152,7 @@
|
||||
[(match_operand:DF 1 "register_operand" "0,f")
|
||||
(float_extend:DF
|
||||
(match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
|
||||
"TARGET_80387 && !TARGET_SSE2"
|
||||
"TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
|
||||
"* return output_387_binary_op (insn, operands);"
|
||||
[(set (attr "type")
|
||||
(cond [(match_operand:DF 3 "mult_operator" "")
|
||||
@ -14421,9 +14486,10 @@
|
||||
(define_expand "sqrtdf2"
|
||||
[(set (match_operand:DF 0 "register_operand" "")
|
||||
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
|
||||
"(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE2"
|
||||
"(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
|
||||
|| (TARGET_SSE2 && TARGET_SSE_MATH)"
|
||||
{
|
||||
if (!TARGET_SSE2)
|
||||
if (!TARGET_SSE2 || !TARGET_SSE_MATH)
|
||||
operands[1] = force_reg (DFmode, operands[1]);
|
||||
})
|
||||
|
||||
@ -14431,7 +14497,7 @@
|
||||
[(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
|
||||
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
|
||||
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
|
||||
&& (TARGET_SSE2 && TARGET_MIX_SSE_I387)"
|
||||
&& (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
|
||||
"@
|
||||
fsqrt
|
||||
sqrtsd\t{%1, %0|%0, %1}"
|
||||
@ -14442,7 +14508,7 @@
|
||||
(define_insn "sqrtdf2_1_sse_only"
|
||||
[(set (match_operand:DF 0 "register_operand" "=Y")
|
||||
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
|
||||
"TARGET_SSE2 && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
|
||||
"sqrtsd\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "sse")
|
||||
(set_attr "mode" "DF")
|
||||
@ -14452,7 +14518,7 @@
|
||||
[(set (match_operand:DF 0 "register_operand" "=f")
|
||||
(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
|
||||
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
|
||||
&& (!TARGET_SSE2 && !TARGET_MIX_SSE_I387)"
|
||||
&& (!TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387)"
|
||||
"fsqrt"
|
||||
[(set_attr "type" "fpspc")
|
||||
(set_attr "mode" "DF")
|
||||
@ -14462,7 +14528,8 @@
|
||||
[(set (match_operand:DF 0 "register_operand" "=f")
|
||||
(sqrt:DF (float_extend:DF
|
||||
(match_operand:SF 1 "register_operand" "0"))))]
|
||||
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_SSE2"
|
||||
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
|
||||
&& !(TARGET_SSE2 && TARGET_SSE_MATH)"
|
||||
"fsqrt"
|
||||
[(set_attr "type" "fpspc")
|
||||
(set_attr "mode" "DF")
|
||||
@ -15963,7 +16030,7 @@
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (reg:CC 17))])]
|
||||
"TARGET_SSE2"
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH"
|
||||
"#")
|
||||
|
||||
(define_insn "*mindf"
|
||||
@ -15973,7 +16040,7 @@
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (reg:CC 17))]
|
||||
"TARGET_SSE2 && TARGET_IEEE_FP"
|
||||
"TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
|
||||
"#")
|
||||
|
||||
(define_insn "*mindf_nonieee"
|
||||
@ -15983,7 +16050,7 @@
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (reg:CC 17))]
|
||||
"TARGET_SSE2 && !TARGET_IEEE_FP"
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
|
||||
"#")
|
||||
|
||||
(define_split
|
||||
@ -16031,7 +16098,7 @@
|
||||
(match_operand:DF 2 "nonimmediate_operand" "Ym"))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"TARGET_SSE2 && reload_completed"
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
|
||||
"minsd\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sse")
|
||||
(set_attr "mode" "DF")])
|
||||
@ -16124,7 +16191,7 @@
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (reg:CC 17))])]
|
||||
"TARGET_SSE2"
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH"
|
||||
"#")
|
||||
|
||||
(define_insn "*maxdf"
|
||||
@ -16134,7 +16201,7 @@
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (reg:CC 17))]
|
||||
"TARGET_SSE2 && TARGET_IEEE_FP"
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
|
||||
"#")
|
||||
|
||||
(define_insn "*maxdf_nonieee"
|
||||
@ -16144,7 +16211,7 @@
|
||||
(match_dup 1)
|
||||
(match_dup 2)))
|
||||
(clobber (reg:CC 17))]
|
||||
"TARGET_SSE2 && !TARGET_IEEE_FP"
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
|
||||
"#")
|
||||
|
||||
(define_split
|
||||
@ -16191,7 +16258,7 @@
|
||||
(match_operand:DF 2 "nonimmediate_operand" "Ym"))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"TARGET_SSE2 && reload_completed"
|
||||
"TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
|
||||
"maxsd\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sse")
|
||||
(set_attr "mode" "DF")])
|
||||
|
||||
@ -473,12 +473,12 @@ in the following sections.
|
||||
|
||||
@emph{i386 and x86-64 Options}
|
||||
@gccoptlist{
|
||||
-mcpu=@var{cpu-type} -march=@var{cpu-type} @gol
|
||||
-mcpu=@var{cpu-type} -march=@var{cpu-type} -mfpmath=@var{unit} @gol
|
||||
-mintel-syntax -mieee-fp -mno-fancy-math-387 @gol
|
||||
-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
|
||||
-mno-wide-multiply -mrtd -malign-double @gol
|
||||
-mpreferred-stack-boundary=@var{num} @gol
|
||||
-mmmx -msse -m3dnow @gol
|
||||
-mmmx -msse -msse2 -msse-math -m3dnow @gol
|
||||
-mthreads -mno-align-stringops -minline-all-stringops @gol
|
||||
-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
|
||||
-m96bit-long-double -mregparm=@var{num} -momit-leaf-frame-pointer @gol
|
||||
@ -7513,6 +7513,48 @@ These options are synonyms for @option{-mcpu=i386}, @option{-mcpu=i486},
|
||||
@option{-mcpu=pentium}, and @option{-mcpu=pentiumpro} respectively.
|
||||
These synonyms are deprecated.
|
||||
|
||||
@item -mfpmath=@var{unit}
|
||||
@opindex march
|
||||
generate floating point arithmetics for selected unit @var{unit}. the choices
|
||||
for @var{unit} are:
|
||||
|
||||
@table @samp
|
||||
@item 387
|
||||
Use the standard 387 floating point coprocessor present majority of chips and
|
||||
emulated otherwise. Code compiled with this option will run almost everywhere.
|
||||
The temporary results are computed in 80bit precesion instead of precision
|
||||
specified by the type resulting in slightly different results compared to most
|
||||
of other chips. See @option{-ffloat-store} for more detailed description.
|
||||
|
||||
This is the default choice for i386 compiler.
|
||||
|
||||
@item sse
|
||||
Use scalar floating point instructions present in the SSE instruction set.
|
||||
This instruction set is supported by Pentium3 and newer chips, in the AMD line
|
||||
by Athlon-4, Athlon-xp and Athlon-mp chips. The earlier version of SSE
|
||||
instruction set supports only single precision arithmetics, thus the double and
|
||||
extended precision arithmetics is still done using 387. Later version, present
|
||||
only in Pentium4 and the future AMD x86-64 chips supports double precision
|
||||
arithmetics too.
|
||||
|
||||
For i387 you need to use @option{-march=@var{cpu-type}}, @option{-msse} or
|
||||
@option{-msse2} switches to enable SSE extensions and make this option
|
||||
effective. For x86-64 compiler, these extensions are enabled by default.
|
||||
|
||||
The resulting code should be considerably faster in majority of cases and avoid
|
||||
the numerical instability problems of 387 code, but may break some existing
|
||||
code that expects temporaries to be 80bit.
|
||||
|
||||
This is the default choice for x86-64 compiler.
|
||||
|
||||
@item sse,387
|
||||
Attempt to utilize both instruction sets at once. This effectivly double the
|
||||
amount of available registers and on chips with separate execution units for
|
||||
387 and SSE the execution resources too. Use this option with care, as it is
|
||||
still experimental, because gcc register allocator does not model separate
|
||||
functional units well resulting in instable performance.
|
||||
@end table
|
||||
|
||||
@item -mintel-syntax
|
||||
@opindex mintel-syntax
|
||||
Emit assembly using Intel syntax opcodes instead of AT&T syntax.
|
||||
@ -7663,6 +7705,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
|
||||
@itemx -mno-mmx
|
||||
@item -msse
|
||||
@itemx -mno-sse
|
||||
@item -msse2
|
||||
@itemx -mno-sse2
|
||||
@item -m3dnow
|
||||
@itemx -mno-3dnow
|
||||
@opindex mmmx
|
||||
|
||||
Loading…
Reference in New Issue
Block a user