Fix __atomic to not implement atomic loads with CAS.
gcc/ * builtins.c (fold_builtin_atomic_always_lock_free): Make "lock-free" conditional on existance of a fast atomic load. * optabs-query.c (can_atomic_load_p): New function. * optabs-query.h (can_atomic_load_p): Declare it. * optabs.c (expand_atomic_exchange): Always delegate to libatomic if no fast atomic load is available for the particular size of access. (expand_atomic_compare_and_swap): Likewise. (expand_atomic_load): Likewise. (expand_atomic_store): Likewise. (expand_atomic_fetch_op): Likewise. * testsuite/lib/target-supports.exp (check_effective_target_sync_int_128): Remove x86 because it provides no fast atomic load. (check_effective_target_sync_int_128_runtime): Likewise. libatomic/ * acinclude.m4: Add #define FAST_ATOMIC_LDST_*. * auto-config.h.in: Regenerate. * config/x86/host-config.h (FAST_ATOMIC_LDST_16): Define to 0. (atomic_compare_exchange_n): New. * glfree.c (EXACT, LARGER): Change condition and add comments. From-SVN: r245098
This commit is contained in:
Torvald Riegel
parent
55e75c7c6b
commit
969a32ce93
@ -1,3 +1,21 @@
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2017-02-01 Torvald Riegel <triegel@redhat.com>
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Richard Henderson <rth@redhat.com>
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* builtins.c (fold_builtin_atomic_always_lock_free): Make "lock-free"
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conditional on existance of a fast atomic load.
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* optabs-query.c (can_atomic_load_p): New function.
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* optabs-query.h (can_atomic_load_p): Declare it.
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* optabs.c (expand_atomic_exchange): Always delegate to libatomic if
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no fast atomic load is available for the particular size of access.
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(expand_atomic_compare_and_swap): Likewise.
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(expand_atomic_load): Likewise.
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(expand_atomic_store): Likewise.
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(expand_atomic_fetch_op): Likewise.
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* testsuite/lib/target-supports.exp
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(check_effective_target_sync_int_128): Remove x86 because it provides
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no fast atomic load.
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(check_effective_target_sync_int_128_runtime): Likewise.
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2017-02-01 Richard Biener <rguenther@suse.de>
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* graphite.c: Include tree-vectorizer.h for find_loop_location.
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@ -6157,8 +6157,9 @@ fold_builtin_atomic_always_lock_free (tree arg0, tree arg1)
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/* Check if a compare_and_swap pattern exists for the mode which represents
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the required size. The pattern is not allowed to fail, so the existence
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of the pattern indicates support is present. */
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if (can_compare_and_swap_p (mode, true))
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of the pattern indicates support is present. Also require that an
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atomic load exists for the required size. */
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if (can_compare_and_swap_p (mode, true) && can_atomic_load_p (mode))
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return boolean_true_node;
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else
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return boolean_false_node;
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@ -584,6 +584,25 @@ can_atomic_exchange_p (machine_mode mode, bool allow_libcall)
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return can_compare_and_swap_p (mode, allow_libcall);
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}
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/* Return true if an atomic load can be performed without falling back to
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a compare-and-swap. */
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bool
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can_atomic_load_p (machine_mode mode)
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{
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enum insn_code icode;
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/* Does the target supports the load directly? */
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icode = direct_optab_handler (atomic_load_optab, mode);
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if (icode != CODE_FOR_nothing)
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return true;
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/* If the size of the object is greater than word size on this target,
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then we assume that a load will not be atomic. Also see
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expand_atomic_load. */
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return GET_MODE_PRECISION (mode) <= BITS_PER_WORD;
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}
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/* Determine whether "1 << x" is relatively cheap in word_mode. */
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bool
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@ -176,6 +176,7 @@ int can_mult_highpart_p (machine_mode, bool);
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bool can_vec_mask_load_store_p (machine_mode, machine_mode, bool);
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bool can_compare_and_swap_p (machine_mode, bool);
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bool can_atomic_exchange_p (machine_mode, bool);
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bool can_atomic_load_p (machine_mode);
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bool lshift_cheap_p (bool);
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#endif
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53
gcc/optabs.c
53
gcc/optabs.c
@ -6086,8 +6086,15 @@ expand_atomic_test_and_set (rtx target, rtx mem, enum memmodel model)
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rtx
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expand_atomic_exchange (rtx target, rtx mem, rtx val, enum memmodel model)
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{
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machine_mode mode = GET_MODE (mem);
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rtx ret;
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/* If loads are not atomic for the required size and we are not called to
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provide a __sync builtin, do not do anything so that we stay consistent
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with atomic loads of the same size. */
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if (!can_atomic_load_p (mode) && !is_mm_sync (model))
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return NULL_RTX;
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ret = maybe_emit_atomic_exchange (target, mem, val, model);
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/* Next try a compare-and-swap loop for the exchange. */
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@ -6121,6 +6128,12 @@ expand_atomic_compare_and_swap (rtx *ptarget_bool, rtx *ptarget_oval,
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rtx target_oval, target_bool = NULL_RTX;
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rtx libfunc;
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/* If loads are not atomic for the required size and we are not called to
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provide a __sync builtin, do not do anything so that we stay consistent
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with atomic loads of the same size. */
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if (!can_atomic_load_p (mode) && !is_mm_sync (succ_model))
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return false;
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/* Load expected into a register for the compare and swap. */
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if (MEM_P (expected))
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expected = copy_to_reg (expected);
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@ -6316,19 +6329,13 @@ expand_atomic_load (rtx target, rtx mem, enum memmodel model)
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}
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/* If the size of the object is greater than word size on this target,
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then we assume that a load will not be atomic. */
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then we assume that a load will not be atomic. We could try to
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emulate a load with a compare-and-swap operation, but the store that
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doing this could result in would be incorrect if this is a volatile
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atomic load or targetting read-only-mapped memory. */
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if (GET_MODE_PRECISION (mode) > BITS_PER_WORD)
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{
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/* Issue val = compare_and_swap (mem, 0, 0).
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This may cause the occasional harmless store of 0 when the value is
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already 0, but it seems to be OK according to the standards guys. */
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if (expand_atomic_compare_and_swap (NULL, &target, mem, const0_rtx,
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const0_rtx, false, model, model))
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return target;
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else
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/* Otherwise there is no atomic load, leave the library call. */
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/* If there is no atomic load, leave the library call. */
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return NULL_RTX;
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}
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/* Otherwise assume loads are atomic, and emit the proper barriers. */
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if (!target || target == const0_rtx)
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@ -6370,7 +6377,9 @@ expand_atomic_store (rtx mem, rtx val, enum memmodel model, bool use_release)
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return const0_rtx;
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}
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/* If using __sync_lock_release is a viable alternative, try it. */
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/* If using __sync_lock_release is a viable alternative, try it.
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Note that this will not be set to true if we are expanding a generic
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__atomic_store_n. */
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if (use_release)
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{
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icode = direct_optab_handler (sync_lock_release_optab, mode);
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@ -6389,16 +6398,22 @@ expand_atomic_store (rtx mem, rtx val, enum memmodel model, bool use_release)
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}
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/* If the size of the object is greater than word size on this target,
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a default store will not be atomic, Try a mem_exchange and throw away
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the result. If that doesn't work, don't do anything. */
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a default store will not be atomic. */
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if (GET_MODE_PRECISION (mode) > BITS_PER_WORD)
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{
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/* If loads are atomic or we are called to provide a __sync builtin,
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we can try a atomic_exchange and throw away the result. Otherwise,
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don't do anything so that we do not create an inconsistency between
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loads and stores. */
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if (can_atomic_load_p (mode) || is_mm_sync (model))
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{
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rtx target = maybe_emit_atomic_exchange (NULL_RTX, mem, val, model);
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if (!target)
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target = maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val);
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target = maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem,
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val);
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if (target)
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return const0_rtx;
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else
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}
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return NULL_RTX;
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}
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@ -6713,6 +6728,12 @@ expand_atomic_fetch_op (rtx target, rtx mem, rtx val, enum rtx_code code,
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rtx result;
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bool unused_result = (target == const0_rtx);
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/* If loads are not atomic for the required size and we are not called to
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provide a __sync builtin, do not do anything so that we stay consistent
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with atomic loads of the same size. */
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if (!can_atomic_load_p (mode) && !is_mm_sync (model))
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return NULL_RTX;
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result = expand_atomic_fetch_op_no_fallback (target, mem, val, code, model,
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after);
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@ -6514,9 +6514,7 @@ proc check_effective_target_section_anchors { } {
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# Return 1 if the target supports atomic operations on "int_128" values.
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proc check_effective_target_sync_int_128 { } {
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if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
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&& ![is-effective-target ia32])
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|| [istarget spu-*-*] } {
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if { [istarget spu-*-*] } {
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return 1
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} else {
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return 0
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@ -6525,23 +6523,10 @@ proc check_effective_target_sync_int_128 { } {
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# Return 1 if the target supports atomic operations on "int_128" values
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# and can execute them.
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# This requires support for both compare-and-swap and true atomic loads.
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proc check_effective_target_sync_int_128_runtime { } {
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if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
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&& ![is-effective-target ia32]
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&& [check_cached_effective_target sync_int_128_available {
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check_runtime_nocache sync_int_128_available {
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#include "cpuid.h"
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int main ()
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{
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unsigned int eax, ebx, ecx, edx;
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if (__get_cpuid (1, &eax, &ebx, &ecx, &edx))
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return !(ecx & bit_CMPXCHG16B);
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return 1;
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}
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} ""
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}])
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|| [istarget spu-*-*] } {
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if { [istarget spu-*-*] } {
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return 1
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} else {
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return 0
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@ -1,3 +1,12 @@
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2017-02-01 Richard Henderson <rth@redhat.com>
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Torvald Riegel <triegel@redhat.com>
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* acinclude.m4: Add #define FAST_ATOMIC_LDST_*.
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* auto-config.h.in: Regenerate.
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* config/x86/host-config.h (FAST_ATOMIC_LDST_16): Define to 0.
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(atomic_compare_exchange_n): New.
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* glfree.c (EXACT, LARGER): Change condition and add comments.
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2017-01-30 Szabolcs Nagy <szabolcs.nagy@arm.com>
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PR target/78945
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@ -96,6 +96,7 @@ AC_DEFUN([LIBAT_HAVE_ATOMIC_LOADSTORE],[
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LIBAT_DEFINE_YESNO([HAVE_ATOMIC_LDST_$2], [$libat_cv_have_at_ldst_$2],
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[Have __atomic_load/store for $2 byte integers.])
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AH_BOTTOM([#define MAYBE_HAVE_ATOMIC_LDST_$2 HAVE_ATOMIC_LDST_$2])
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AH_BOTTOM([#define FAST_ATOMIC_LDST_$2 HAVE_ATOMIC_LDST_$2])
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])
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dnl
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@ -222,6 +222,16 @@
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#define MAYBE_HAVE_ATOMIC_LDST_1 HAVE_ATOMIC_LDST_1
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#define FAST_ATOMIC_LDST_16 HAVE_ATOMIC_LDST_16
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#define MAYBE_HAVE_ATOMIC_TAS_1 HAVE_ATOMIC_TAS_1
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#define MAYBE_HAVE_ATOMIC_TAS_2 HAVE_ATOMIC_TAS_2
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#define MAYBE_HAVE_ATOMIC_TAS_4 HAVE_ATOMIC_TAS_4
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#define MAYBE_HAVE_ATOMIC_TAS_8 HAVE_ATOMIC_TAS_8
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#define MAYBE_HAVE_ATOMIC_TAS_16 HAVE_ATOMIC_TAS_16
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#define MAYBE_HAVE_ATOMIC_EXCHANGE_1 HAVE_ATOMIC_EXCHANGE_1
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@ -232,6 +242,8 @@
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#define MAYBE_HAVE_ATOMIC_EXCHANGE_8 HAVE_ATOMIC_EXCHANGE_8
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#define FAST_ATOMIC_LDST_1 HAVE_ATOMIC_LDST_1
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#define MAYBE_HAVE_ATOMIC_EXCHANGE_16 HAVE_ATOMIC_EXCHANGE_16
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#define MAYBE_HAVE_ATOMIC_CAS_1 HAVE_ATOMIC_CAS_1
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@ -242,8 +254,6 @@
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#define MAYBE_HAVE_ATOMIC_CAS_8 HAVE_ATOMIC_CAS_8
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#define MAYBE_HAVE_ATOMIC_LDST_2 HAVE_ATOMIC_LDST_2
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#define MAYBE_HAVE_ATOMIC_CAS_16 HAVE_ATOMIC_CAS_16
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#define MAYBE_HAVE_ATOMIC_FETCH_ADD_1 HAVE_ATOMIC_FETCH_ADD_1
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@ -254,6 +264,8 @@
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#define MAYBE_HAVE_ATOMIC_FETCH_ADD_8 HAVE_ATOMIC_FETCH_ADD_8
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#define MAYBE_HAVE_ATOMIC_LDST_2 HAVE_ATOMIC_LDST_2
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#define MAYBE_HAVE_ATOMIC_FETCH_ADD_16 HAVE_ATOMIC_FETCH_ADD_16
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#define MAYBE_HAVE_ATOMIC_FETCH_OP_1 HAVE_ATOMIC_FETCH_OP_1
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@ -264,22 +276,20 @@
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#define MAYBE_HAVE_ATOMIC_FETCH_OP_8 HAVE_ATOMIC_FETCH_OP_8
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#define MAYBE_HAVE_ATOMIC_LDST_4 HAVE_ATOMIC_LDST_4
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#define MAYBE_HAVE_ATOMIC_FETCH_OP_16 HAVE_ATOMIC_FETCH_OP_16
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#ifndef WORDS_BIGENDIAN
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#define WORDS_BIGENDIAN 0
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#endif
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#define FAST_ATOMIC_LDST_2 HAVE_ATOMIC_LDST_2
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#define MAYBE_HAVE_ATOMIC_LDST_4 HAVE_ATOMIC_LDST_4
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#define FAST_ATOMIC_LDST_4 HAVE_ATOMIC_LDST_4
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#define MAYBE_HAVE_ATOMIC_LDST_8 HAVE_ATOMIC_LDST_8
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#define FAST_ATOMIC_LDST_8 HAVE_ATOMIC_LDST_8
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#define MAYBE_HAVE_ATOMIC_LDST_16 HAVE_ATOMIC_LDST_16
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#define MAYBE_HAVE_ATOMIC_TAS_1 HAVE_ATOMIC_TAS_1
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#define MAYBE_HAVE_ATOMIC_TAS_2 HAVE_ATOMIC_TAS_2
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#define MAYBE_HAVE_ATOMIC_TAS_4 HAVE_ATOMIC_TAS_4
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#define MAYBE_HAVE_ATOMIC_TAS_8 HAVE_ATOMIC_TAS_8
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@ -47,6 +47,9 @@ extern unsigned int libat_feat1_edx HIDDEN;
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# define MAYBE_HAVE_ATOMIC_EXCHANGE_16 IFUNC_COND_1
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# undef MAYBE_HAVE_ATOMIC_LDST_16
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# define MAYBE_HAVE_ATOMIC_LDST_16 IFUNC_COND_1
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/* Since load and store are implemented with CAS, they are not fast. */
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# undef FAST_ATOMIC_LDST_16
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# define FAST_ATOMIC_LDST_16 0
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# if IFUNC_ALT == 1
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# undef HAVE_ATOMIC_CAS_16
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# define HAVE_ATOMIC_CAS_16 1
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@ -64,6 +67,21 @@ extern unsigned int libat_feat1_edx HIDDEN;
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# endif
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#endif
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#if defined(__x86_64__) && N == 16 && IFUNC_ALT == 1
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static inline bool
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atomic_compare_exchange_n (UTYPE *mptr, UTYPE *eptr, UTYPE newval,
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bool weak_p UNUSED, int sm UNUSED, int fm UNUSED)
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{
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UTYPE cmpval = *eptr;
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UTYPE oldval = __sync_val_compare_and_swap_16 (mptr, cmpval, newval);
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if (oldval == cmpval)
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return true;
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*eptr = oldval;
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return false;
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}
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# define atomic_compare_exchange_n atomic_compare_exchange_n
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#endif /* Have CAS 16 */
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#endif /* HAVE_IFUNC */
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#include_next <host-config.h>
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@ -24,26 +24,41 @@
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#include "libatomic_i.h"
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/* Accesses with a power-of-two size are not lock-free if we don't have an
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integer type of this size or if they are not naturally aligned. They
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are lock-free if such a naturally aligned access is always lock-free
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according to the compiler, which requires that both atomic loads and CAS
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are available.
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In all other cases, we fall through to LARGER (see below). */
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#define EXACT(N) \
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do { \
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if (!C2(HAVE_INT,N)) break; \
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if ((uintptr_t)ptr & (N - 1)) break; \
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if (__atomic_always_lock_free(N, 0)) return true; \
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if (C2(MAYBE_HAVE_ATOMIC_CAS_,N)) return true; \
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if (!C2(MAYBE_HAVE_ATOMIC_CAS_,N)) break; \
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if (C2(FAST_ATOMIC_LDST_,N)) return true; \
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} while (0)
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/* We next check to see if an access of a larger size is lock-free. We use
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a similar check as in EXACT, except that we also check that the alignment
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of the access is so that the data to be accessed is completely covered
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by the larger access. */
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#define LARGER(N) \
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do { \
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uintptr_t r = (uintptr_t)ptr & (N - 1); \
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if (!C2(HAVE_INT,N)) break; \
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if (!C2(HAVE_ATOMIC_LDST_,N)) break; \
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if (!C2(FAST_ATOMIC_LDST_,N)) break; \
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if (!C2(MAYBE_HAVE_ATOMIC_CAS_,N)) break; \
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if (r + n <= N) return true; \
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} while (0)
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/* Note that this can return that a size/alignment is not lock-free even if
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all the operations that we use to implement the respective accesses provide
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lock-free forward progress as specified in C++14: Users likely expect
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"lock-free" to also mean "fast", which is why we do not return true if, for
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example, we implement loads with this size/alignment using a CAS. */
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bool
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libat_is_lock_free (size_t n, void *ptr)
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{
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