mips.h (ISA_HAS_BRANCHLIKELY, [...]): Disable if TARGET_MIPS16.
* config/mips/mips.h (ISA_HAS_BRANCHLIKELY, ISA_HAS_CONDMOVE, ISA_HAS_FP4, ISA_HAS_MADD_MSUB, ISA_HAS_NMADD_NMSUB, ISA_HAS_CLZ_CLO, ISA_HAS_DCLZ_DCLO): Disable if TARGET_MIPS16. From-SVN: r51917
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@ -1,3 +1,9 @@
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2002-04-05 Alexandre Oliva <aoliva@redhat.com>
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* config/mips/mips.h (ISA_HAS_BRANCHLIKELY, ISA_HAS_CONDMOVE,
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ISA_HAS_FP4, ISA_HAS_MADD_MSUB, ISA_HAS_NMADD_NMSUB,
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ISA_HAS_CLZ_CLO, ISA_HAS_DCLZ_DCLO): Disable if TARGET_MIPS16.
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2002-04-05 Andreas Schwab <schwab@suse.de>
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* c-convert.c: Include c-common.h.
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@ -634,52 +634,51 @@ extern void sbss_section PARAMS ((void));
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/* Disable branchlikely for tx39 until compare rewrite. They haven't
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been generated up to this point. */
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#define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
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/* || TARGET_MIPS3900 */)
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&& ! TARGET_MIPS16)
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/* ISA has the conditional move instructions introduced in mips4. */
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#define ISA_HAS_CONDMOVE (mips_isa == 4 \
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|| mips_isa == 32 \
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|| mips_isa == 64)
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#define ISA_HAS_CONDMOVE ((mips_isa == 4 \
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|| mips_isa == 32 \
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|| mips_isa == 64) \
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&& ! TARGET_MIPS16)
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/* ISA has just the integer condition move instructions (movn,movz) */
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#define ISA_HAS_INT_CONDMOVE 0
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/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
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branch on CC, and move (both FP and non-FP) on CC. */
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#define ISA_HAS_8CC (mips_isa == 4 \
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|| mips_isa == 32 \
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|| mips_isa == 64)
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/* This is a catch all for the other new mips4 instructions: indexed load and
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indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
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and the FP recip and recip sqrt instructions */
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#define ISA_HAS_FP4 (mips_isa == 4 \
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)
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&& ! TARGET_MIPS16)
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/* ISA has conditional trap instructions. */
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#define ISA_HAS_COND_TRAP (mips_isa >= 2 && ! TARGET_MIPS16)
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#define ISA_HAS_COND_TRAP (mips_isa >= 2 \
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&& ! TARGET_MIPS16)
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/* ISA has multiply-accumulate instructions, madd and msub. */
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#define ISA_HAS_MADD_MSUB (mips_isa == 32 \
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|| mips_isa == 64 \
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)
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#define ISA_HAS_MADD_MSUB ((mips_isa == 32 \
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|| mips_isa == 64 \
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) && ! TARGET_MIPS16)
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/* ISA has nmadd and nmsub instructions. */
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#define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \
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)
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&& ! TARGET_MIPS16)
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/* ISA has count leading zeroes/ones instruction (not implemented). */
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#define ISA_HAS_CLZ_CLO (mips_isa == 32 \
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|| mips_isa == 64 \
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)
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#define ISA_HAS_CLZ_CLO ((mips_isa == 32 \
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|| mips_isa == 64 \
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) && ! TARGET_MIPS16)
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/* ISA has double-word count leading zeroes/ones instruction (not
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implemented). */
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#define ISA_HAS_DCLZ_DCLO (mips_isa == 64)
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#define ISA_HAS_DCLZ_DCLO (mips_isa == 64 \
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&& ! TARGET_MIPS16)
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/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
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-mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
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