ia64-protos.h: Remove duplicates.
* config/ia64/ia64-protos.h: Remove duplicates. Update for massive code rearrangements. * config/ia64/ia64.c (ia64_arpfs_regno): Remove. (ia64_rp_regno, ia64_fp_regno, ia64_input_regs): Remove. (ia64_local_regs, ia64_need_regstk): Remove. (ar_ccv_reg_operand): New. (ia64_gp_save_reg): New. (struct ia64_frame_info): Combine most of the size elements; add new gr save elements. (find_gr_spill): New. (next_scratch_gr_reg): New. (mark_reg_gr_used_mask): New. (ia64_compute_frame_size): Rewrite. Allocate special AR regs to GR backing store regs when possible. (ia64_initial_elimination_offset): New. (ia64_rap_fp_offset): Remove. (save_restore_insns): Remove. (setup_spill_pointers): New. (finish_spill_pointers): New. (spill_restore_mem): New. (do_spill, do_restore): New. (ia64_expand_prologue): Rewrite to use them. (ia64_expand_epilogue): Likewise. (ia64_direct_return): Update for current_frame_info changes. (ia64_function_prologue): Simplify .prologue emission. Emit .spill when needed. (ia64_setup_incoming_varargs): Don't ever emit rtl. (ia64_dbx_register_number): New. (ia64_initialize_trampoline): New. (ia64_secondary_reload_class): Request GR_REGS for integer arithmetic destined for FR_REGS. (ia64_init_machine_status): Don't reset return_address_pointer_rtx. (ia64_mark_machine_status): Mark ia64_gp_save. (rws_access_regno): Rename from rws_access_reg; don't treat predicates specially. (rws_access_reg): New. Update all callers. (rtx_needs_barrier): Remove dead unspecs. (ia64_epilogue_uses): Mark ar.pfs and ar.unat live on exit. (ia64_encode_section_info): Silence signed/unsigned warnings. (spill_offset, sp_offset, spill_offset_emitted): Remove. (tmp_reg, tmp_saved): Remove. (process_set): Rewrite to expect complicated bits via REG_FRAME_RELATED_EXPR. (ia64_expand_fetch_and_op): Use emit_move_insn; be explicit in the use of ar.ccv; never set RTX_UNCHANGING_P. (ia64_expand_op_and_fetch): Likewise. (ia64_expand_compare_and_swap): Likewise. (ia64_expand_builtin): Likewise. * config/ia64/ia64.h (AR_UNAT_REGNUM): New. (FIRST_PSEUDO_REGISTER): Update. (AR_M_REGNO_P): Update. (FIXED_REGS): Don't mark three local registers as used. (EXTRA_CC_MODES): New. (SELECT_CC_MODE): New. (HARD_REGNO_NREGS): Allow DImode in p0; handle CCImode. (HARD_REGNO_MODE_OK): Disallow CCImode from non-predicates. (FRAME_GROWS_DOWNWARD): Unset. (STARTING_FRAME_OFFSET): Zero. (ELIMINABLE_REGS): Eliminate from the soft to hard frame pointer. (INITIAL_ELIMINATION_OFFSET): Defer to out of line function. (HARD_FRAME_POINTER_REGNUM): New. (CAN_DEBUG_WITHOUT_FP): Define. (TRAMPOLINE_TEMPLATE): Remove. (TRAMPOLINE_SIZE): Lower to 32. (TRAMPOLINE_ALIGNMENT): Lower to 64. (INITIALIZE_TRAMPOLINE): Defer to out of line function. (PREDICATE_CODES): Update. (struct machine_function): Add ia64_gp_save. * config/ia64/ia64.md: Purge unused unspecs. (movsi patterns): Allow moves to/from AR_M_REGS. (movdi patterns): Allow moves to/from p0. (call patterns): Move most setjmp hackery to ia64_gp_save_reg. (gr_spill, gr_restore): Indicate ar.unat read/written. (nonlocal_goto): Don't pass old frame_pointer. (nonlocal_goto_receiver): Remove. (exception_receiver): New. (builtin_setjmp_setup): New. (builtin_setjmp_receiver): New. * config/ia64/lib1funcs.asm (__ia64_save_stack_nonlocal): Bundle. (__ia64_nonlocal_goto): Bundle. Don't kill r7. (__ia64_restore_stack_nonlocal): Likewise. (__ia64_trampoline): New. * config/ia64/sysv4.h (DBX_REGISTER_NUMBER): Defer to out of line function. * config/ia64/t-ia64 (LIB1ASMFUNCS): Add __trampoline. From-SVN: r35568
This commit is contained in:
Richard Henderson
Richard Henderson
parent
ee7152458a
commit
97e242b0a7
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@ -1,3 +1,91 @@
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2000-08-08 Richard Henderson <rth@cygnus.com>
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* config/ia64/ia64-protos.h: Remove duplicates. Update
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for massive code rearrangements.
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* config/ia64/ia64.c (ia64_arpfs_regno): Remove.
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(ia64_rp_regno, ia64_fp_regno, ia64_input_regs): Remove.
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(ia64_local_regs, ia64_need_regstk): Remove.
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(ar_ccv_reg_operand): New.
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(ia64_gp_save_reg): New.
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(struct ia64_frame_info): Combine most of the size elements;
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add new gr save elements.
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(find_gr_spill): New.
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(next_scratch_gr_reg): New.
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(mark_reg_gr_used_mask): New.
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(ia64_compute_frame_size): Rewrite. Allocate special AR regs
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to GR backing store regs when possible.
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(ia64_initial_elimination_offset): New.
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(ia64_rap_fp_offset): Remove.
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(save_restore_insns): Remove.
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(setup_spill_pointers): New.
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(finish_spill_pointers): New.
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(spill_restore_mem): New.
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(do_spill, do_restore): New.
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(ia64_expand_prologue): Rewrite to use them.
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(ia64_expand_epilogue): Likewise.
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(ia64_direct_return): Update for current_frame_info changes.
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(ia64_function_prologue): Simplify .prologue emission. Emit
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.spill when needed.
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(ia64_setup_incoming_varargs): Don't ever emit rtl.
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(ia64_dbx_register_number): New.
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(ia64_initialize_trampoline): New.
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(ia64_secondary_reload_class): Request GR_REGS for integer
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arithmetic destined for FR_REGS.
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(ia64_init_machine_status): Don't reset return_address_pointer_rtx.
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(ia64_mark_machine_status): Mark ia64_gp_save.
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(rws_access_regno): Rename from rws_access_reg; don't treat
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predicates specially.
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(rws_access_reg): New. Update all callers.
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(rtx_needs_barrier): Remove dead unspecs.
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(ia64_epilogue_uses): Mark ar.pfs and ar.unat live on exit.
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(ia64_encode_section_info): Silence signed/unsigned warnings.
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(spill_offset, sp_offset, spill_offset_emitted): Remove.
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(tmp_reg, tmp_saved): Remove.
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(process_set): Rewrite to expect complicated bits via
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REG_FRAME_RELATED_EXPR.
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(ia64_expand_fetch_and_op): Use emit_move_insn; be explicit
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in the use of ar.ccv; never set RTX_UNCHANGING_P.
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(ia64_expand_op_and_fetch): Likewise.
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(ia64_expand_compare_and_swap): Likewise.
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(ia64_expand_builtin): Likewise.
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* config/ia64/ia64.h (AR_UNAT_REGNUM): New.
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(FIRST_PSEUDO_REGISTER): Update.
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(AR_M_REGNO_P): Update.
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(FIXED_REGS): Don't mark three local registers as used.
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(EXTRA_CC_MODES): New.
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(SELECT_CC_MODE): New.
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(HARD_REGNO_NREGS): Allow DImode in p0; handle CCImode.
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(HARD_REGNO_MODE_OK): Disallow CCImode from non-predicates.
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(FRAME_GROWS_DOWNWARD): Unset.
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(STARTING_FRAME_OFFSET): Zero.
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(ELIMINABLE_REGS): Eliminate from the soft to hard frame pointer.
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(INITIAL_ELIMINATION_OFFSET): Defer to out of line function.
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(HARD_FRAME_POINTER_REGNUM): New.
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(CAN_DEBUG_WITHOUT_FP): Define.
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(TRAMPOLINE_TEMPLATE): Remove.
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(TRAMPOLINE_SIZE): Lower to 32.
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(TRAMPOLINE_ALIGNMENT): Lower to 64.
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(INITIALIZE_TRAMPOLINE): Defer to out of line function.
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(PREDICATE_CODES): Update.
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(struct machine_function): Add ia64_gp_save.
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* config/ia64/ia64.md: Purge unused unspecs.
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(movsi patterns): Allow moves to/from AR_M_REGS.
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(movdi patterns): Allow moves to/from p0.
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(call patterns): Move most setjmp hackery to ia64_gp_save_reg.
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(gr_spill, gr_restore): Indicate ar.unat read/written.
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(nonlocal_goto): Don't pass old frame_pointer.
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(nonlocal_goto_receiver): Remove.
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(exception_receiver): New.
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(builtin_setjmp_setup): New.
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(builtin_setjmp_receiver): New.
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* config/ia64/lib1funcs.asm (__ia64_save_stack_nonlocal): Bundle.
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(__ia64_nonlocal_goto): Bundle. Don't kill r7.
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(__ia64_restore_stack_nonlocal): Likewise.
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(__ia64_trampoline): New.
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* config/ia64/sysv4.h (DBX_REGISTER_NUMBER): Defer to out of line
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function.
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* config/ia64/t-ia64 (LIB1ASMFUNCS): Add __trampoline.
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2000-08-08 Richard Henderson <rth@cygnus.com>
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* frame.h (ia64_frame_state): Add my_psp.
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@ -50,18 +50,18 @@ extern int normal_comparison_operator PARAMS((rtx, enum machine_mode));
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extern int adjusted_comparison_operator PARAMS((rtx, enum machine_mode));
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extern int call_multiple_values_operation PARAMS((rtx, enum machine_mode));
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extern int destination_operand PARAMS((rtx, enum machine_mode));
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extern int ia64_rap_fp_offset PARAMS((void));
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extern unsigned int ia64_compute_frame_size PARAMS((int));
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extern void save_restore_insns PARAMS((int));
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extern HOST_WIDE_INT ia64_initial_elimination_offset PARAMS((int, int));
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extern void ia64_expand_prologue PARAMS((void));
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extern void ia64_expand_epilogue PARAMS((void));
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extern void ia64_function_prologue PARAMS((FILE *, int));
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extern void ia64_funtion_epilogue PARAMS((FILE *, int));
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extern void ia64_function_epilogue PARAMS((FILE *, int));
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extern int ia64_direct_return PARAMS((void));
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extern int predicate_operator PARAMS((rtx, enum machine_mode));
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extern int ar_lc_reg_operand PARAMS((rtx, enum machine_mode));
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extern int ar_ccv_reg_operand PARAMS((rtx, enum machine_mode));
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extern int ia64_move_ok PARAMS((rtx, rtx));
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extern rtx ia64_gp_save_reg PARAMS((int));
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extern void ia64_expand_load_address PARAMS((rtx, rtx));
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extern void ia64_expand_fetch_and_op PARAMS ((enum fetchop_code,
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@ -69,6 +69,7 @@ extern void ia64_expand_fetch_and_op PARAMS ((enum fetchop_code,
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extern void ia64_expand_op_and_fetch PARAMS ((enum fetchop_code,
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enum machine_mode, rtx []));
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extern void ia64_initialize_trampoline PARAMS((rtx, rtx, rtx));
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extern void ia64_print_operand_address PARAMS((FILE *, rtx));
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extern void ia64_print_operand PARAMS((FILE *, rtx, int));
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extern enum reg_class ia64_secondary_reload_class PARAMS((enum reg_class,
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@ -107,17 +108,10 @@ extern void ia64_encode_section_info PARAMS((tree));
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extern int ia64_register_move_cost PARAMS((enum reg_class, enum reg_class));
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extern int ia64_epilogue_uses PARAMS((int));
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extern void ia64_file_start PARAMS((FILE *));
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extern void ia64_expand_prologue PARAMS((void));
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extern void ia64_expand_epilogue PARAMS((void));
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extern void ia64_function_prologue PARAMS((FILE *, int));
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extern void ia64_output_end_prologue PARAMS((FILE *));
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extern void ia64_function_epilogue PARAMS((FILE *, int));
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extern int ia64_direct_return PARAMS((void));
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extern int ia64_rap_fp_offset PARAMS((void));
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extern void ia64_init_builtins PARAMS((void));
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extern void ia64_override_options PARAMS((void));
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extern unsigned int ia64_compute_frame_size PARAMS((int));
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extern void save_restore_insns PARAMS((int));
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extern int ia64_dbx_register_number PARAMS((int));
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/* ??? Flag defined in toplev.c, for ia64.md -fssa hack. */
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extern int flag_ssa;
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File diff suppressed because it is too large
Load Diff
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@ -20,19 +20,12 @@ along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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/* ??? Use of the upper 32 FP registers for integer values will make context
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switching slower, because the kernel only saves any registers past f32 if
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it has to. */
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/* ??? Look at ABI group documents for list of preprocessor macros and
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other features required for ABI compliance. */
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/* ??? Functions containing a non-local goto target save many registers. Why?
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See for instance execute/920428-2.c. */
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/* ??? Get CAN_DEBUG_WITHOUT_FP working so that -fomit-frame-pointer is not
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needed. */
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/* ??? Add support for short data/bss sections. */
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@ -178,13 +171,6 @@ extern const char *ia64_fixed_range_string;
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default values for the other command line options. */
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/* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */
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/* Define this macro if debugging can be performed even without a frame
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pointer. If this macro is defined, GNU CC will turn on the
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`-fomit-frame-pointer' option whenever `-O' is specified. */
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/* ??? Need to define this. */
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/* #define CAN_DEBUG_WITHOUT_FP */
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/* Driver configuration */
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@ -539,7 +525,7 @@ while (0)
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64 predicate registers, 8 branch registers, one frame pointer,
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and several "application" registers. */
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#define FIRST_PSEUDO_REGISTER 334
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#define FIRST_PSEUDO_REGISTER 335
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/* Ranges for the various kinds of registers. */
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#define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
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@ -561,22 +547,23 @@ while (0)
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#define LOC_REG(REGNO) ((REGNO) + 32)
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#define AR_CCV_REGNUM 330
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#define AR_LC_REGNUM 331
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#define AR_EC_REGNUM 332
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#define AR_PFS_REGNUM 333
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#define AR_UNAT_REGNUM 331
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#define AR_PFS_REGNUM 332
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#define AR_LC_REGNUM 333
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#define AR_EC_REGNUM 334
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#define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
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#define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
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#define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
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#define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM)
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#define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_LC_REGNUM \
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#define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
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|| (REGNO) == AR_UNAT_REGNUM)
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#define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
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&& (REGNO) < FIRST_PSEUDO_REGISTER)
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#define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
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&& (REGNO) < FIRST_PSEUDO_REGISTER)
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/* ??? Don't really need two sets of macros. I like this one better because
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it is less typing. */
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#define R_GR(REGNO) GR_REG (REGNO)
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@ -600,11 +587,6 @@ while (0)
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/* The last 16 stacked regs are reserved for the 8 input and 8 output
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registers. */
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/* ??? Must mark the next 3 stacked regs as fixed, because ia64_expand_prologue
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assumes that three locals are available for fp, b0, and ar.pfs. */
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/* ??? Should mark b0 as fixed? */
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#define FIXED_REGISTERS \
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{ /* General registers. */ \
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1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
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@ -613,7 +595,7 @@ while (0)
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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/* Floating-point registers. */ \
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1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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@ -631,8 +613,8 @@ while (0)
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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/* Branch registers. */ \
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0, 0, 0, 0, 0, 0, 0, 0, \
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/*FP RA CCV LC EC PFS */ \
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1, 1, 1, 1, 1, 1 \
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/*FP RA CCV UNAT PFS LC EC */ \
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1, 1, 1, 1, 1, 0, 1 \
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}
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/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
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@ -648,7 +630,7 @@ while (0)
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
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/* Floating-point registers. */ \
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1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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@ -666,8 +648,8 @@ while (0)
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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/* Branch registers. */ \
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1, 0, 0, 0, 0, 0, 1, 1, \
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/*FP RA CCV LC EC PFS */ \
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1, 1, 1, 1, 1, 1 \
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/*FP RA CCV UNAT PFS LC EC */ \
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1, 1, 1, 1, 1, 0, 1 \
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}
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/* Define this macro if the target machine has register windows. This C
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@ -692,6 +674,20 @@ while (0)
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#define LOCAL_REGNO(REGNO) \
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(IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
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/* Add any extra modes needed to represent the condition code.
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CCImode is used to mark a single predicate register instead
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of a register pair. This is currently only used in reg_raw_mode
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so that flow doesn't do something stupid. */
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#define EXTRA_CC_MODES CC(CCImode, "CCI")
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/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
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return the mode to be used for the comparison. Must be defined if
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EXTRA_CC_MODES is defined. */
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#define SELECT_CC_MODE(OP,X,Y) CCmode
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/* Order of allocation of registers */
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@ -711,72 +707,72 @@ while (0)
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/* ??? Should the GR return value registers come before or after the rest
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of the caller-save GRs? */
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#define REG_ALLOC_ORDER \
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#define REG_ALLOC_ORDER \
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{ \
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||||
/* Caller-saved general registers. */ \
|
||||
R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
|
||||
R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
|
||||
R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
|
||||
R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
|
||||
R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
|
||||
R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
|
||||
R_GR (30), R_GR (31), \
|
||||
/* Output registers. */ \
|
||||
R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
|
||||
R_GR (126), R_GR (127), \
|
||||
R_GR (126), R_GR (127), \
|
||||
/* Caller-saved general registers, also used for return values. */ \
|
||||
R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
|
||||
R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
|
||||
/* addl caller-saved general registers. */ \
|
||||
R_GR (2), R_GR (3), \
|
||||
/* Caller-saved FP registers. */ \
|
||||
R_FR (6), R_FR (7), \
|
||||
/* Caller-saved FP registers, used for parameters and return values. */ \
|
||||
R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
|
||||
R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
|
||||
R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
|
||||
R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
|
||||
/* Rotating caller-saved FP registers. */ \
|
||||
R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
|
||||
R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
|
||||
R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
|
||||
R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
|
||||
R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
|
||||
R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
|
||||
R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
|
||||
R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
|
||||
R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
|
||||
R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
|
||||
R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
|
||||
R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
|
||||
R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
|
||||
R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
|
||||
R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
|
||||
R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
|
||||
R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
|
||||
R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
|
||||
R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
|
||||
R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
|
||||
R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
|
||||
R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
|
||||
R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
|
||||
R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
|
||||
R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
|
||||
R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
|
||||
R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
|
||||
R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
|
||||
R_FR (126), R_FR (127), \
|
||||
R_FR (126), R_FR (127), \
|
||||
/* Caller-saved predicate registers. */ \
|
||||
R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
|
||||
R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
|
||||
R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
|
||||
/* Rotating caller-saved predicate registers. */ \
|
||||
R_PR (16), R_PR (17), \
|
||||
R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
|
||||
R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
|
||||
R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
|
||||
R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
|
||||
R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
|
||||
R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
|
||||
R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
|
||||
R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
|
||||
R_PR (16), R_PR (17), \
|
||||
R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
|
||||
R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
|
||||
R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
|
||||
R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
|
||||
R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
|
||||
R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
|
||||
R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
|
||||
R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
|
||||
/* Caller-saved branch registers. */ \
|
||||
R_BR (6), R_BR (7), \
|
||||
\
|
||||
/* Stacked callee-saved general registers. */ \
|
||||
R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
|
||||
R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
|
||||
R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
|
||||
R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
|
||||
R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
|
||||
R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
|
||||
R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
|
||||
R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
|
||||
R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
|
||||
R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
|
||||
R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
|
||||
R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
|
||||
R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
|
||||
R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
|
||||
R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
|
||||
R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
|
||||
R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
|
||||
R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
|
||||
R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
|
||||
R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
|
||||
R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
|
||||
R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
|
||||
R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
|
||||
R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
|
||||
R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
|
||||
R_GR (108), \
|
||||
/* Input registers. */ \
|
||||
|
|
@ -785,12 +781,12 @@ while (0)
|
|||
/* Callee-saved general registers. */ \
|
||||
R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
|
||||
/* Callee-saved FP registers. */ \
|
||||
R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
|
||||
R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
|
||||
R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
|
||||
R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
|
||||
R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
|
||||
R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
|
||||
R_FR (30), R_FR (31), \
|
||||
/* Callee-saved predicate registers. */ \
|
||||
R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
|
||||
R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
|
||||
/* Callee-saved branch registers. */ \
|
||||
R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
|
||||
\
|
||||
|
|
@ -798,7 +794,7 @@ while (0)
|
|||
R_GR (109), R_GR (110), R_GR (111), \
|
||||
\
|
||||
/* Special general registers. */ \
|
||||
R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
|
||||
R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
|
||||
/* Special FP registers. */ \
|
||||
R_FR (0), R_FR (1), \
|
||||
/* Special predicate registers. */ \
|
||||
|
|
@ -807,7 +803,8 @@ while (0)
|
|||
R_BR (0), \
|
||||
/* Other fixed registers. */ \
|
||||
FRAME_POINTER_REGNUM, RETURN_ADDRESS_POINTER_REGNUM, \
|
||||
AR_CCV_REGNUM, AR_LC_REGNUM, AR_EC_REGNUM, AR_PFS_REGNUM \
|
||||
AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
|
||||
AR_EC_REGNUM \
|
||||
}
|
||||
|
||||
/* How Values Fit in Registers */
|
||||
|
|
@ -817,11 +814,13 @@ while (0)
|
|||
|
||||
/* ??? x86 80-bit FP values only require 1 register. */
|
||||
/* ??? We say that CCmode values require two registers. This allows us to
|
||||
easily store the normal and inverted values. If we want single register
|
||||
predicates, we can use EXTRA_CC_MODES to give them a different mode. */
|
||||
easily store the normal and inverted values. We use CCImode to indicate
|
||||
a single predicate register. */
|
||||
|
||||
#define HARD_REGNO_NREGS(REGNO, MODE) \
|
||||
((MODE) == CCmode && PR_REGNO_P (REGNO) ? 2 \
|
||||
#define HARD_REGNO_NREGS(REGNO, MODE) \
|
||||
((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
|
||||
: PR_REGNO_P (REGNO) && (MODE) == CCmode ? 2 \
|
||||
: PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
|
||||
: FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \
|
||||
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
|
||||
|
||||
|
|
@ -830,9 +829,9 @@ while (0)
|
|||
that one). */
|
||||
|
||||
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
|
||||
(FR_REGNO_P (REGNO) ? (MODE) != CCmode \
|
||||
: PR_REGNO_P (REGNO) ? (MODE) == CCmode \
|
||||
: GR_REGNO_P (REGNO) ? (MODE) != XFmode \
|
||||
(FR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) != MODE_CC \
|
||||
: PR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
|
||||
: GR_REGNO_P (REGNO) ? (MODE) != XFmode && (MODE) != CCImode \
|
||||
: AR_REGNO_P (REGNO) ? (MODE) == DImode \
|
||||
: 1)
|
||||
|
||||
|
|
@ -951,15 +950,15 @@ enum reg_class
|
|||
/* AR_M_REGS. */ \
|
||||
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x0400 }, \
|
||||
0x00000000, 0x00000000, 0x0C00 }, \
|
||||
/* AR_I_REGS. */ \
|
||||
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
|
||||
0x00000000, 0x00000000, 0x3800 }, \
|
||||
0x00000000, 0x00000000, 0x7000 }, \
|
||||
/* ALL_REGS. */ \
|
||||
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x7FFF }, \
|
||||
}
|
||||
|
||||
/* A C expression whose value is a register class containing hard register
|
||||
|
|
@ -974,8 +973,8 @@ enum reg_class
|
|||
: FR_REGNO_P (REGNO) ? FR_REGS \
|
||||
: PR_REGNO_P (REGNO) ? PR_REGS \
|
||||
: BR_REGNO_P (REGNO) ? BR_REGS \
|
||||
: AR_M_REGNO_P (REGNO) ? AR_I_REGS \
|
||||
: AR_I_REGNO_P (REGNO) ? AR_M_REGS \
|
||||
: AR_M_REGNO_P (REGNO) ? AR_M_REGS \
|
||||
: AR_I_REGNO_P (REGNO) ? AR_I_REGS \
|
||||
: NO_REGS)
|
||||
|
||||
/* A macro whose definition is the name of the class to which a valid base
|
||||
|
|
@ -1068,8 +1067,9 @@ enum reg_class
|
|||
|
||||
#define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) 1
|
||||
|
||||
/* A C expression that defines the machine-dependent operand constraint letters
|
||||
(`I', `J', `K', .. 'P') that specify particular ranges of integer values. */
|
||||
/* A C expression that defines the machine-dependent operand constraint
|
||||
letters (`I', `J', `K', .. 'P') that specify particular ranges of
|
||||
integer values. */
|
||||
|
||||
/* 14 bit signed immediate for arithmetic instructions. */
|
||||
#define CONST_OK_FOR_I(VALUE) \
|
||||
|
|
@ -1084,7 +1084,6 @@ enum reg_class
|
|||
/* 6 bit unsigned immediate for shift counts. */
|
||||
#define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
|
||||
/* 9 bit signed immediate for load/store post-increments. */
|
||||
/* ??? N is currently not used. */
|
||||
#define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
|
||||
/* 0 for r0. Used by Linux kernel, do not change. */
|
||||
#define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
|
||||
|
|
@ -1131,18 +1130,11 @@ enum reg_class
|
|||
|
||||
/* Define this macro if the addresses of local variable slots are at negative
|
||||
offsets from the frame pointer. */
|
||||
#define FRAME_GROWS_DOWNWARD
|
||||
/* #define FRAME_GROWS_DOWNWARD */
|
||||
|
||||
/* Offset from the frame pointer to the first local variable slot to be
|
||||
allocated. */
|
||||
/* ??? This leaves 16 bytes unused normally, but it looks funny to store locals
|
||||
into the 16-byte reserved area. */
|
||||
/* ??? This isn't very efficient use of the frame pointer. Better would be
|
||||
to move it down a ways, so that we have positive and negative offsets. */
|
||||
#define STARTING_FRAME_OFFSET \
|
||||
(current_function_pretend_args_size \
|
||||
? 16 - current_function_pretend_args_size \
|
||||
: 0)
|
||||
/* Offset from the frame pointer to the first local variable slot to
|
||||
be allocated. */
|
||||
#define STARTING_FRAME_OFFSET 0
|
||||
|
||||
/* Offset from the stack pointer register to the first location at which
|
||||
outgoing arguments are placed. If not specified, the default value of zero
|
||||
|
|
@ -1207,16 +1199,8 @@ enum reg_class
|
|||
|
||||
#define FRAME_POINTER_REGNUM 328
|
||||
|
||||
/* Register number where frame pointer was saved in the prologue, or zero
|
||||
if it was not saved. */
|
||||
|
||||
extern int ia64_fp_regno;
|
||||
|
||||
/* Number of input and local registers used. This is needed for the .regstk
|
||||
directive, and also for debugging info. */
|
||||
|
||||
extern int ia64_input_regs;
|
||||
extern int ia64_local_regs;
|
||||
/* Base register for access to local variables of the function. */
|
||||
#define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
|
||||
|
||||
/* The register number of the arg pointer register, which is used to access the
|
||||
function's argument list. */
|
||||
|
|
@ -1224,76 +1208,52 @@ extern int ia64_local_regs;
|
|||
in it. */
|
||||
#define ARG_POINTER_REGNUM R_GR(0)
|
||||
|
||||
/* The register number for the return address register. This is not actually
|
||||
a pointer as the name suggests, but that's a name that gen_rtx_REG
|
||||
already takes care to keep unique. We modify return_address_pointer_rtx
|
||||
in ia64_expand_prologue to reference the final output regnum. */
|
||||
|
||||
/* The register number for the return address register. For IA-64, this
|
||||
is not actually a pointer as the name suggests, but that's a name that
|
||||
gen_rtx_REG already takes care to keep unique. We modify
|
||||
return_address_pointer_rtx in ia64_expand_prologue to reference the
|
||||
final output regnum. */
|
||||
#define RETURN_ADDRESS_POINTER_REGNUM 329
|
||||
|
||||
/* Register numbers used for passing a function's static chain pointer. */
|
||||
|
||||
/* ??? The ABI sez the static chain should be passed as a normal parameter. */
|
||||
#define STATIC_CHAIN_REGNUM 15
|
||||
|
||||
|
||||
/* Eliminating the Frame Pointer and the Arg Pointer */
|
||||
|
||||
/* A C expression which is nonzero if a function must have and use a frame
|
||||
pointer. This expression is evaluated in the reload pass. If its value is
|
||||
nonzero the function will have a frame pointer. */
|
||||
|
||||
#define FRAME_POINTER_REQUIRED 0
|
||||
|
||||
/* Show we can debug even without a frame pointer. */
|
||||
#define CAN_DEBUG_WITHOUT_FP
|
||||
|
||||
/* If defined, this macro specifies a table of register pairs used to eliminate
|
||||
unneeded registers that point into the stack frame. */
|
||||
|
||||
#define ELIMINABLE_REGS \
|
||||
{ \
|
||||
{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
||||
{ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
|
||||
{ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
|
||||
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
||||
{RETURN_ADDRESS_POINTER_REGNUM, BR_REG (0)} \
|
||||
{FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
|
||||
{RETURN_ADDRESS_POINTER_REGNUM, BR_REG (0)}, \
|
||||
}
|
||||
|
||||
/* A C expression that returns non-zero if the compiler is allowed to try to
|
||||
replace register number FROM with register number TO. */
|
||||
replace register number FROM with register number TO. The frame pointer
|
||||
is automatically handled. */
|
||||
|
||||
#define CAN_ELIMINATE(FROM, TO) \
|
||||
(TO == BR_REG (0) ? current_function_is_leaf : 1)
|
||||
|
||||
/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
|
||||
initial difference between the specified pair of registers. This macro must
|
||||
be defined if `ELIMINABLE_REGS' is defined. */
|
||||
/* ??? I need to decide whether the frame pointer is the old frame SP
|
||||
or the new frame SP before dynamic allocs. */
|
||||
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
||||
{ \
|
||||
unsigned int size = ia64_compute_frame_size (get_frame_size ()); \
|
||||
\
|
||||
if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
|
||||
(OFFSET) = size; \
|
||||
else if ((FROM) == ARG_POINTER_REGNUM) \
|
||||
{ \
|
||||
switch (TO) \
|
||||
{ \
|
||||
case FRAME_POINTER_REGNUM: \
|
||||
/* Arguments start above the 16 byte save area, unless stdarg \
|
||||
in which case we store through the 16 byte save area. */ \
|
||||
(OFFSET) = 16 - current_function_pretend_args_size; \
|
||||
break; \
|
||||
case STACK_POINTER_REGNUM: \
|
||||
(OFFSET) = size + 16 - current_function_pretend_args_size; \
|
||||
break; \
|
||||
default: \
|
||||
abort (); \
|
||||
} \
|
||||
} \
|
||||
else if ((TO) == BR_REG (0)) \
|
||||
(OFFSET) = 0; \
|
||||
else \
|
||||
abort (); \
|
||||
}
|
||||
|
||||
/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
|
||||
specifies the initial difference between the specified pair of
|
||||
registers. This macro must be defined if `ELIMINABLE_REGS' is
|
||||
defined. */
|
||||
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
||||
((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
|
||||
|
||||
/* Passing Function Arguments on the Stack */
|
||||
|
||||
|
|
@ -1688,108 +1648,39 @@ do { \
|
|||
a trampoline, leaving space for the variable parts.
|
||||
|
||||
The trampoline should set the static chain pointer to value placed
|
||||
into the trampoline and should branch to the specified routine. The
|
||||
gp doesn't have to be set since that is already done by the caller
|
||||
of the trampoline. To make the normal indirect-subroutine calling
|
||||
convention work, the trampoline must look like a function descriptor.
|
||||
That is, the first word must be the target address, the second
|
||||
word must be the target's global pointer. The complete trampoline
|
||||
into the trampoline and should branch to the specified routine.
|
||||
To make the normal indirect-subroutine calling convention work,
|
||||
the trampoline must look like a function descriptor; the first
|
||||
word being the target address and the second being the target's
|
||||
global pointer.
|
||||
|
||||
We abuse the concept of a global pointer by arranging for it
|
||||
to point to the data we need to load. The complete trampoline
|
||||
has the following form:
|
||||
|
||||
+----------------+ \
|
||||
TRAMP: | TRAMP+32 | |
|
||||
+----------------+ > fake function descriptor
|
||||
| gp | |
|
||||
+----------------+ /
|
||||
| target addr |
|
||||
+----------------+
|
||||
| static link |
|
||||
+----------------+
|
||||
| mov r2=ip |
|
||||
+ +
|
||||
| ;; |
|
||||
+----------------+
|
||||
| adds r4=-16,r2 |
|
||||
+ adds r15=-8,r2 +
|
||||
| ;; |
|
||||
+----------------+
|
||||
| ld8 r4=[r4];; |
|
||||
+ ld8 r15=[r15] +
|
||||
| mov b6=r4;; |
|
||||
+----------------+
|
||||
| br b6 |
|
||||
+----------------+
|
||||
+-------------------+ \
|
||||
TRAMP: | __ia64_trampoline | |
|
||||
+-------------------+ > fake function descriptor
|
||||
| TRAMP+16 | |
|
||||
+-------------------+ /
|
||||
| target descriptor |
|
||||
+-------------------+
|
||||
| static link |
|
||||
+-------------------+
|
||||
*/
|
||||
|
||||
/* ??? Need a version of this and INITIALIZE_TRAMPOLINE for -mno-pic. */
|
||||
|
||||
#define TRAMPOLINE_TEMPLATE(FILE) \
|
||||
{ \
|
||||
fprintf (FILE, \
|
||||
"\tdata8 0,0,0,0\n" \
|
||||
"\t{ mov r2=ip }\n" \
|
||||
"\t;;\n" \
|
||||
"\t{ adds r4=-16,r2; adds r%d=-8,r2 }\n" \
|
||||
"\t;;\n" \
|
||||
"\t{ ld8 r4=[r4];; ld8 r%d=[r%d]; mov b6=r4 }\n" \
|
||||
"\t;;\n" \
|
||||
"\t{ br b6 }\n" \
|
||||
"\t;;\n", \
|
||||
STATIC_CHAIN_REGNUM, STATIC_CHAIN_REGNUM, \
|
||||
STATIC_CHAIN_REGNUM); \
|
||||
}
|
||||
|
||||
/* The name of a subroutine to switch to the section in which the trampoline
|
||||
template is to be placed.
|
||||
|
||||
On ia64, instructions may only be placed in a text segment. */
|
||||
|
||||
#define TRAMPOLINE_SECTION text_section
|
||||
|
||||
/* A C expression for the size in bytes of the trampoline, as an integer. */
|
||||
|
||||
#define TRAMPOLINE_SIZE 96
|
||||
#define TRAMPOLINE_SIZE 32
|
||||
|
||||
/* Alignment required for trampolines, in bits. */
|
||||
|
||||
#define TRAMPOLINE_ALIGNMENT 256
|
||||
#define TRAMPOLINE_ALIGNMENT 64
|
||||
|
||||
/* A C statement to initialize the variable parts of a trampoline. */
|
||||
|
||||
#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
|
||||
{ \
|
||||
rtx addr, addr2, addr_reg, fdesc_addr; \
|
||||
\
|
||||
/* Load function descriptor address into a pseudo. */ \
|
||||
fdesc_addr = gen_reg_rtx (DImode); \
|
||||
emit_move_insn (fdesc_addr, FNADDR); \
|
||||
\
|
||||
/* Read target address from function descriptor and store in \
|
||||
trampoline. */ \
|
||||
addr = memory_address (Pmode, plus_constant (ADDR, 16)); \
|
||||
emit_move_insn (gen_rtx_MEM (Pmode, addr), \
|
||||
gen_rtx_MEM (Pmode, fdesc_addr)); \
|
||||
/* Store static chain in trampoline. */ \
|
||||
addr = memory_address (Pmode, plus_constant (ADDR, 24)); \
|
||||
emit_move_insn (gen_rtx_MEM (Pmode, addr), STATIC_CHAIN); \
|
||||
\
|
||||
/* Load GP value from function descriptor and store in trampoline. */\
|
||||
addr = memory_address (Pmode, plus_constant (ADDR, 8)); \
|
||||
addr2 = memory_address (Pmode, plus_constant (fdesc_addr, 8)); \
|
||||
emit_move_insn (gen_rtx_MEM (Pmode, addr), \
|
||||
gen_rtx_MEM (Pmode, addr2)); \
|
||||
\
|
||||
/* Store trampoline entry address in trampoline. */ \
|
||||
addr = memory_address (Pmode, ADDR); \
|
||||
addr2 = memory_address (Pmode, plus_constant (ADDR, 32)); \
|
||||
emit_move_insn (gen_rtx_MEM (Pmode, addr), addr2); \
|
||||
\
|
||||
/* Flush the relevant 64 bytes from the i-cache. */ \
|
||||
addr_reg = force_reg (DImode, plus_constant (ADDR, 0)); \
|
||||
emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, \
|
||||
gen_rtvec (1, addr_reg), 3)); \
|
||||
}
|
||||
|
||||
ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN))
|
||||
|
||||
/* Implicit Calls to Library Routines */
|
||||
|
||||
|
|
@ -2394,7 +2285,7 @@ do { \
|
|||
/* Branch registers. */ \
|
||||
"b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
|
||||
/* Frame pointer. Return address. */ \
|
||||
"sfp", "retaddr", "ar.ccv", "ar.lc", "ar.ec", "ar.pfs" \
|
||||
"sfp", "retaddr", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
|
||||
}
|
||||
|
||||
/* If defined, a C initializer for an array of structures containing a name and
|
||||
|
|
@ -2781,7 +2672,8 @@ do { \
|
|||
{ "adjusted_comparison_operator", {LT, GE, LTU, GEU}}, \
|
||||
{ "call_multiple_values_operation", {PARALLEL}}, \
|
||||
{ "predicate_operator", {NE, EQ}}, \
|
||||
{ "ar_lc_reg_operand", {REG}},
|
||||
{ "ar_lc_reg_operand", {REG}}, \
|
||||
{ "ar_ccv_reg_operand", {REG}},
|
||||
|
||||
/* An alias for a machine mode name. This is the machine mode that elements of
|
||||
a jump-table should have. */
|
||||
|
|
@ -2892,6 +2784,9 @@ struct machine_function
|
|||
|
||||
/* The new bsp value when unwinding from EH. */
|
||||
struct rtx_def* ia64_eh_epilogue_bsp;
|
||||
|
||||
/* The GP value save register. */
|
||||
struct rtx_def* ia64_gp_save;
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -59,15 +59,9 @@
|
|||
;; 2 gr_restore
|
||||
;; 3 fr_spill
|
||||
;; 4 fr_restore
|
||||
;; 5 pr_spill
|
||||
;; 8 popcnt
|
||||
;; 9 unat_spill
|
||||
;; 10 unat_restore
|
||||
;; 12 mf
|
||||
;; 13 cmpxchg_acq
|
||||
;; 14 val_compare_and_swap
|
||||
;; 16 lock_test_and_set
|
||||
;; 17 op_and_fetch
|
||||
;; 18 fetch_and_op
|
||||
;; 19 fetchadd_acq
|
||||
;; 20 bsp_value
|
||||
;; 21 flushrs
|
||||
|
|
@ -76,10 +70,7 @@
|
|||
;; 0 alloc
|
||||
;; 1 blockage
|
||||
;; 2 insn_group_barrier
|
||||
;; 3 flush_cache
|
||||
;; 4 pfs_restore
|
||||
;; 5 set_bsp
|
||||
;; 6 pr_restore
|
||||
;; 7 pred.rel.mutex
|
||||
|
||||
;; ::::::::::::::::::::
|
||||
|
|
@ -302,10 +293,10 @@
|
|||
(define_insn "*movsicc_astep"
|
||||
[(cond_exec
|
||||
(match_operator 2 "predicate_operator"
|
||||
[(match_operand:CC 3 "register_operand" "c,c,c,c,c,c")
|
||||
[(match_operand:CC 3 "register_operand" "c,c,c,c,c,c,c,c")
|
||||
(const_int 0)])
|
||||
(set (match_operand:SI 0 "register_operand" "=r,r,r, r,*f,*f")
|
||||
(match_operand:SI 1 "nonmemory_operand" "rO,J,i,*f,rO,*f")))]
|
||||
(set (match_operand:SI 0 "register_operand" "=r,r,r, r,*f,*f, r,*d")
|
||||
(match_operand:SI 1 "nonmemory_operand" "rO,J,i,*f,rO,*f,*d,rO")))]
|
||||
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
|
||||
"@
|
||||
(%J2) mov %0 = %r1
|
||||
|
|
@ -313,13 +304,15 @@
|
|||
(%J2) movl %0 = %1
|
||||
(%J2) getf.sig %0 = %1
|
||||
(%J2) setf.sig %0 = %r1
|
||||
(%J2) mov %0 = %1"
|
||||
[(set_attr "type" "A,A,L,M,M,F")
|
||||
(%J2) mov %0 = %1
|
||||
(%J2) mov %0 = %1
|
||||
(%J2) mov %0 = %r1"
|
||||
[(set_attr "type" "A,A,L,M,M,F,M,M")
|
||||
(set_attr "predicable" "no")])
|
||||
|
||||
(define_insn "*movsi_internal_astep"
|
||||
[(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f")
|
||||
(match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f"))]
|
||||
[(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
|
||||
(match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rO"))]
|
||||
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
|
||||
"@
|
||||
mov %0 = %r1
|
||||
|
|
@ -329,13 +322,15 @@
|
|||
st4%Q0 %0 = %r1%P0
|
||||
getf.sig %0 = %1
|
||||
setf.sig %0 = %r1
|
||||
mov %0 = %1"
|
||||
[(set_attr "type" "A,A,L,M,M,M,M,F")
|
||||
mov %0 = %1
|
||||
mov %0 = %1
|
||||
mov %0 = %r1"
|
||||
[(set_attr "type" "A,A,L,M,M,M,M,F,M,M")
|
||||
(set_attr "predicable" "no")])
|
||||
|
||||
(define_insn "*movsi_internal"
|
||||
[(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f")
|
||||
(match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f"))]
|
||||
[(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
|
||||
(match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rO"))]
|
||||
"! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
|
||||
"@
|
||||
mov %0 = %r1
|
||||
|
|
@ -345,8 +340,10 @@
|
|||
st4%Q0 %0 = %r1%P0
|
||||
getf.sig %0 = %1
|
||||
setf.sig %0 = %r1
|
||||
mov %0 = %1"
|
||||
[(set_attr "type" "A,A,L,M,M,M,M,F")])
|
||||
mov %0 = %1
|
||||
mov %0 = %1
|
||||
mov %0 = %r1"
|
||||
[(set_attr "type" "A,A,L,M,M,M,M,F,M,M")])
|
||||
|
||||
(define_expand "movdi"
|
||||
[(set (match_operand:DI 0 "general_operand" "")
|
||||
|
|
@ -412,9 +409,9 @@
|
|||
|
||||
(define_insn "*movdi_internal_astep"
|
||||
[(set (match_operand:DI 0 "destination_operand"
|
||||
"=r,r,r,r, m, r,*f,*f,*f, Q, r,*b*e, r,*d")
|
||||
"=r,r,r,r, m, r,*f,*f,*f, Q, r,*b*e, r,*d, r,*c")
|
||||
(match_operand:DI 1 "move_operand"
|
||||
"rO,J,i,m,rO,*f,rO,*f, Q,*f,*b*e, rO,*d,rO"))]
|
||||
"rO,J,i,m,rO,*f,rO,*f, Q,*f,*b*e, rO,*d,rO,*c,rO"))]
|
||||
"TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
|
||||
"*
|
||||
{
|
||||
|
|
@ -432,7 +429,9 @@
|
|||
\"mov %0 = %1\",
|
||||
\"mov %0 = %r1\",
|
||||
\"mov %0 = %1\",
|
||||
\"mov %0 = %r1\"
|
||||
\"mov %0 = %r1\",
|
||||
\"mov %0 = pr\",
|
||||
\"mov pr = %1, -1\"
|
||||
};
|
||||
|
||||
if (which_alternative == 2 && ! TARGET_NO_PIC
|
||||
|
|
@ -441,14 +440,14 @@
|
|||
|
||||
return alt[which_alternative];
|
||||
}"
|
||||
[(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I,M,M")
|
||||
[(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I,M,M,I,I")
|
||||
(set_attr "predicable" "no")])
|
||||
|
||||
(define_insn "*movdi_internal"
|
||||
[(set (match_operand:DI 0 "destination_operand"
|
||||
"=r,r,r,r, m, r,*f,*f,*f, Q, r,*b*e, r,*d")
|
||||
"=r,r,r,r, m, r,*f,*f,*f, Q, r,*b*e, r,*d, r,*c")
|
||||
(match_operand:DI 1 "move_operand"
|
||||
"rO,J,i,m,rO,*f,rO,*f, Q,*f,*b*e, rO,*d,rO"))]
|
||||
"rO,J,i,m,rO,*f,rO,*f, Q,*f,*b*e, rO,*d,rO,*c,rO"))]
|
||||
"! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
|
||||
"*
|
||||
{
|
||||
|
|
@ -466,7 +465,9 @@
|
|||
\"%,mov %0 = %1\",
|
||||
\"%,mov %0 = %r1\",
|
||||
\"%,mov %0 = %1\",
|
||||
\"%,mov %0 = %r1\"
|
||||
\"%,mov %0 = %r1\",
|
||||
\"mov %0 = pr\",
|
||||
\"mov pr = %1, -1\"
|
||||
};
|
||||
|
||||
if (which_alternative == 2 && ! TARGET_NO_PIC
|
||||
|
|
@ -475,7 +476,7 @@
|
|||
|
||||
return alt[which_alternative];
|
||||
}"
|
||||
[(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I,M,M")])
|
||||
[(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I,M,M,I,I")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DI 0 "register_operand" "")
|
||||
|
|
@ -2780,16 +2781,16 @@
|
|||
;; Errata 72 workaround.
|
||||
(define_insn "*cmovdi_internal_astep"
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand"
|
||||
"=r,*f,Q,*b*d*e,r,*f,Q,*b*d*e,r,*f,Q,*b*d*e")
|
||||
"=r,*f,Q,*b,r,*f,Q,*b,r,*f,Q,*b")
|
||||
(if_then_else:DI
|
||||
(match_operator:CC 4 "predicate_operator"
|
||||
[(match_operand:CC 1 "register_operand"
|
||||
"c,c,c,c,c,c,c,c,c,c,c,c")
|
||||
(const_int 0)])
|
||||
(match_operand:DI 2 "general_operand"
|
||||
"0,0,0,0,ri*f*b*d*e,rO,*f,r,ri*f*b*d*e,rO,*f,r")
|
||||
"0,0,0,0,ri*f*b,rO,*f,r,ri*f*b,rO,*f,r")
|
||||
(match_operand:DI 3 "general_operand"
|
||||
"ri*f*b*d*e,rO,*f,r,0,0,0,0,ri*f*b*d*e,rO,*f,r")))]
|
||||
"ri*f*b,rO,*f,r,0,0,0,0,ri*f*b,rO,*f,r")))]
|
||||
"TARGET_A_STEP"
|
||||
"* abort ();"
|
||||
[(set_attr "predicable" "no")])
|
||||
|
|
@ -3012,9 +3013,6 @@
|
|||
else if (TARGET_CONST_GP)
|
||||
emit_call_insn (gen_call_internal (addr, operands[1],
|
||||
gen_rtx_REG (DImode, R_BR (0))));
|
||||
/* ??? This is an unsatisfying solution. Should rethink. */
|
||||
else if (setjmp_operand (addr, mode))
|
||||
emit_insn (gen_setjmp_call_pic (addr, operands[1]));
|
||||
else
|
||||
emit_insn (gen_call_pic (addr, operands[1]));
|
||||
|
||||
|
|
@ -3033,32 +3031,11 @@
|
|||
""
|
||||
"
|
||||
{
|
||||
operands[2] = gen_reg_rtx (DImode);
|
||||
operands[2] = ia64_gp_save_reg (0);
|
||||
operands[3] = gen_reg_rtx (DImode);
|
||||
operands[4] = gen_reg_rtx (DImode);
|
||||
}")
|
||||
|
||||
;; We can't save GP in a pseudo if we are calling setjmp, because pseudos
|
||||
;; won't be restored by longjmp. For now, we save it in r4.
|
||||
|
||||
;; ??? It would be more efficient to save this directly into a stack slot.
|
||||
;; Unfortunately, the stack slot address gets cse'd across the setjmp call
|
||||
;; because the NOTE_INSN_SETJMP note is in the wrong place.
|
||||
|
||||
;; ??? This is an unsatisfying solution. Should rethink.
|
||||
|
||||
(define_expand "setjmp_call_pic"
|
||||
[(set (match_dup 2) (reg:DI 1))
|
||||
(parallel [(call (mem:DI (match_operand 0 "" "")) (match_operand 1 "" ""))
|
||||
(use (reg:DI 1))
|
||||
(clobber (reg:DI 320))])
|
||||
(set (reg:DI 1) (match_dup 2))]
|
||||
""
|
||||
"
|
||||
{
|
||||
operands[2] = gen_rtx_REG (DImode, GR_REG (4));
|
||||
}")
|
||||
|
||||
;; ??? Saving/restoring the GP register is not needed if we are calling
|
||||
;; a function in the same module.
|
||||
|
||||
|
|
@ -3071,7 +3048,9 @@
|
|||
""
|
||||
"
|
||||
{
|
||||
operands[2] = gen_reg_rtx (DImode);
|
||||
/* ??? Using setjmp_operand is an unsatisfying solution. Should rethink. */
|
||||
operands[2] = ia64_gp_save_reg (setjmp_operand (XEXP (operands[0], 0),
|
||||
VOIDmode));
|
||||
}")
|
||||
|
||||
(define_insn "call_internal"
|
||||
|
|
@ -3129,9 +3108,6 @@
|
|||
else if (TARGET_CONST_GP)
|
||||
emit_call_insn (gen_call_value_internal (operands[0], addr, operands[2],
|
||||
gen_rtx_REG (DImode, R_BR (0))));
|
||||
/* ??? This is an unsatisfying solution. Should rethink. */
|
||||
else if (setjmp_operand (addr, mode))
|
||||
emit_insn (gen_setjmp_call_value_pic (operands[0], addr, operands[2]));
|
||||
/* This is for HFA returns. */
|
||||
else if (GET_CODE (operands[0]) == PARALLEL)
|
||||
emit_insn (gen_call_multiple_values_pic (operands[0], addr, operands[2]));
|
||||
|
|
@ -3154,7 +3130,7 @@
|
|||
""
|
||||
"
|
||||
{
|
||||
operands[3] = gen_reg_rtx (DImode);
|
||||
operands[3] = ia64_gp_save_reg (0);
|
||||
operands[4] = gen_reg_rtx (DImode);
|
||||
operands[5] = gen_reg_rtx (DImode);
|
||||
}")
|
||||
|
|
@ -3177,7 +3153,7 @@
|
|||
int i;
|
||||
rtx call;
|
||||
|
||||
operands[3] = gen_reg_rtx (DImode);
|
||||
operands[3] = ia64_gp_save_reg (0);
|
||||
operands[4] = gen_reg_rtx (DImode);
|
||||
operands[5] = gen_reg_rtx (DImode);
|
||||
|
||||
|
|
@ -3203,29 +3179,6 @@
|
|||
|
||||
}")
|
||||
|
||||
;; We can't save GP in a pseudo if we are calling setjmp, because pseudos
|
||||
;; won't be restored by longjmp. For now, we save it in r4.
|
||||
|
||||
;; ??? It would be more efficient to save this directly into a stack slot.
|
||||
;; Unfortunately, the stack slot address gets cse'd across the setjmp call
|
||||
;; because the NOTE_INSN_SETJMP note is in the wrong place.
|
||||
|
||||
;; ??? This is an unsatisfying solution. Should rethink.
|
||||
|
||||
(define_expand "setjmp_call_value_pic"
|
||||
[(set (match_dup 3) (reg:DI 1))
|
||||
(parallel [(set (match_operand 0 "" "")
|
||||
(call (mem:DI (match_operand 1 "" ""))
|
||||
(match_operand 2 "" "")))
|
||||
(use (reg:DI 1))
|
||||
(clobber (reg:DI 320))])
|
||||
(set (reg:DI 1) (match_dup 3))]
|
||||
""
|
||||
"
|
||||
{
|
||||
operands[3] = gen_rtx_REG (DImode, GR_REG (4));
|
||||
}")
|
||||
|
||||
;; ??? Saving/restoring the GP register is not needed if we are calling
|
||||
;; a function in the same module.
|
||||
|
||||
|
|
@ -3240,7 +3193,9 @@
|
|||
""
|
||||
"
|
||||
{
|
||||
operands[3] = gen_reg_rtx (DImode);
|
||||
/* ??? Using setjmp_operand is an unsatisfying solution. Should rethink. */
|
||||
operands[3] = ia64_gp_save_reg (setjmp_operand (XEXP (operands[1], 0),
|
||||
VOIDmode));
|
||||
}")
|
||||
|
||||
;; ??? Saving/restoring the GP register is not needed if we are calling
|
||||
|
|
@ -3261,7 +3216,7 @@
|
|||
int i;
|
||||
rtx call;
|
||||
|
||||
operands[4] = gen_reg_rtx (DImode);
|
||||
operands[4] = ia64_gp_save_reg (0);
|
||||
|
||||
call = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (DImode, operands[1]),
|
||||
operands[2]);
|
||||
|
|
@ -3478,16 +3433,36 @@
|
|||
[(set_attr "type" "M")
|
||||
(set_attr "predicable" "no")])
|
||||
|
||||
(define_insn "gr_spill"
|
||||
;; Modifies ar.unat
|
||||
(define_expand "gr_spill"
|
||||
[(parallel
|
||||
[(set (match_operand:DI 0 "memory_operand" "=m")
|
||||
(unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))
|
||||
(clobber (match_dup 2))])]
|
||||
""
|
||||
"operands[2] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
|
||||
|
||||
(define_insn "*gr_spill_internal"
|
||||
[(set (match_operand:DI 0 "memory_operand" "=m")
|
||||
(unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))]
|
||||
(unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))
|
||||
(clobber (match_operand:DI 2 "register_operand" ""))]
|
||||
""
|
||||
"st8.spill %0 = %1%P0"
|
||||
[(set_attr "type" "M")])
|
||||
|
||||
(define_insn "gr_restore"
|
||||
;; Reads ar.unat
|
||||
(define_expand "gr_restore"
|
||||
[(parallel
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")] 2))
|
||||
(use (match_dup 2))])]
|
||||
""
|
||||
"operands[2] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
|
||||
|
||||
(define_insn "*gr_restore_internal"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")] 2))]
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")] 2))
|
||||
(use (match_operand:DI 2 "register_operand" ""))]
|
||||
""
|
||||
"ld8.fill %0 = %1%P1"
|
||||
[(set_attr "type" "M")])
|
||||
|
|
@ -3506,47 +3481,6 @@
|
|||
"ldf.fill %0 = %1%P1"
|
||||
[(set_attr "type" "M")])
|
||||
|
||||
(define_insn "pr_spill"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(unspec:DI [(const_int 0)] 5))]
|
||||
""
|
||||
"mov %0 = pr"
|
||||
[(set_attr "type" "I")])
|
||||
|
||||
;; ??? This is volatile to prevent it from being moved before a conditional
|
||||
;; expression that calculates the return value.
|
||||
|
||||
(define_insn "pr_restore"
|
||||
[(unspec_volatile [(const_int 0)] 6)
|
||||
(use (match_operand:DI 0 "register_operand" "r"))]
|
||||
""
|
||||
"mov pr = %0, -1"
|
||||
[(set_attr "type" "I")])
|
||||
|
||||
;; ??? This is volatile to prevent it from being moved before a call.
|
||||
;; Should instead add a ar.pfs hard register which is call clobbered.
|
||||
|
||||
(define_insn "pfs_restore"
|
||||
[(unspec_volatile [(const_int 0)] 4)
|
||||
(use (match_operand:DI 0 "register_operand" "r"))]
|
||||
""
|
||||
"mov ar.pfs = %0"
|
||||
[(set_attr "type" "I")])
|
||||
|
||||
(define_insn "unat_spill"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(unspec:DI [(const_int 0)] 9))]
|
||||
""
|
||||
"mov %0 = ar.unat"
|
||||
[(set_attr "type" "M")])
|
||||
|
||||
(define_insn "unat_restore"
|
||||
[(unspec [(const_int 0)] 10)
|
||||
(use (match_operand:DI 0 "register_operand" "r"))]
|
||||
""
|
||||
"mov ar.unat = %0"
|
||||
[(set_attr "type" "M")])
|
||||
|
||||
(define_insn "bsp_value"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(unspec:DI [(const_int 0)] 20))]
|
||||
|
|
@ -3624,31 +3558,39 @@
|
|||
""
|
||||
"
|
||||
{
|
||||
if (GET_CODE (operands[0]) != REG)
|
||||
operands[0] = force_reg (Pmode, operands[0]);
|
||||
emit_move_insn (virtual_stack_vars_rtx, operands[0]);
|
||||
emit_insn (gen_rtx_USE (VOIDmode, frame_pointer_rtx));
|
||||
emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
|
||||
emit_insn (gen_rtx_USE (VOIDmode, static_chain_rtx));
|
||||
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
|
||||
0, VOIDmode, 4,
|
||||
operands[0], Pmode, operands[1], Pmode,
|
||||
0, VOIDmode, 3,
|
||||
operands[1], Pmode,
|
||||
copy_to_reg (XEXP (operands[2], 0)), Pmode,
|
||||
operands[3], Pmode);
|
||||
emit_barrier ();
|
||||
DONE;
|
||||
}")
|
||||
|
||||
;; ??? We need this because the function __ia64_nonlocal_goto can't easily
|
||||
;; access the FP which is currently stored in a local register. Maybe move
|
||||
;; the FP to a global register to avoid this problem?
|
||||
;; Restore the GP after the exception/longjmp. The preceeding call will
|
||||
;; have tucked it away.
|
||||
(define_expand "exception_receiver"
|
||||
[(set (reg:DI 1) (match_dup 0))]
|
||||
""
|
||||
"operands[0] = ia64_gp_save_reg (0);")
|
||||
|
||||
(define_expand "nonlocal_goto_receiver"
|
||||
[(use (const_int 0))]
|
||||
;; The rest of the setjmp processing happens with the nonlocal_goto expander.
|
||||
;; ??? This is not tested.
|
||||
(define_expand "builtin_setjmp_setup"
|
||||
[(use (match_operand:DI 0 "" ""))]
|
||||
""
|
||||
"
|
||||
{
|
||||
emit_move_insn (frame_pointer_rtx, gen_rtx_REG (DImode, GR_REG (7)));
|
||||
emit_move_insn (ia64_gp_save_reg (0), gen_rtx_REG (DImode, GR_REG (1)));
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "builtin_setjmp_receiver"
|
||||
[(use (match_operand:DI 0 "" ""))]
|
||||
""
|
||||
"
|
||||
{
|
||||
emit_move_insn (gen_rtx_REG (DImode, GR_REG (1)), ia64_gp_save_reg (0));
|
||||
DONE;
|
||||
}")
|
||||
|
||||
|
|
@ -3677,20 +3619,7 @@
|
|||
|
||||
cfun->machine->ia64_eh_epilogue_sp = sp;
|
||||
cfun->machine->ia64_eh_epilogue_bsp = bsp;
|
||||
|
||||
}")
|
||||
|
||||
;; This flushes at least 64 bytes starting from the address pointed
|
||||
;; to by operand[0].
|
||||
|
||||
;; ??? This should be a define expand.
|
||||
|
||||
(define_insn "flush_cache"
|
||||
[(unspec_volatile [(match_operand:DI 0 "register_operand" "=&r")] 3)]
|
||||
""
|
||||
"fc %0\;;;\;adds %0=31,%0\;;;\;fc %0\;;;\;sync.i\;srlz.i"
|
||||
[(set_attr "type" "unknown")
|
||||
(set_attr "predicable" "no")])
|
||||
|
||||
;; Builtin apply support.
|
||||
|
||||
|
|
@ -3710,20 +3639,6 @@
|
|||
|
||||
;;; Intrinsics support.
|
||||
|
||||
(define_insn "ccv_restore_si"
|
||||
[(unspec [(const_int 0)] 11)
|
||||
(use (match_operand:SI 0 "register_operand" "r"))]
|
||||
""
|
||||
"mov ar.ccv = %0"
|
||||
[(set_attr "type" "M")])
|
||||
|
||||
(define_insn "ccv_restore_di"
|
||||
[(unspec [(const_int 0)] 11)
|
||||
(use (match_operand:DI 0 "register_operand" "r"))]
|
||||
""
|
||||
"mov ar.ccv = %0"
|
||||
[(set_attr "type" "M")])
|
||||
|
||||
(define_insn "mf"
|
||||
[(unspec [(match_operand:BLK 0 "memory_operand" "m")] 12)]
|
||||
""
|
||||
|
|
@ -3749,50 +3664,50 @@
|
|||
(define_insn "cmpxchg_acq_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "register_operand" "r")] 13))]
|
||||
(match_operand:SI 2 "register_operand" "r")
|
||||
(match_operand:SI 3 "ar_ccv_reg_operand" "")] 13))]
|
||||
""
|
||||
"cmpxchg4.acq %0 = %1, %2, ar.ccv"
|
||||
"cmpxchg4.acq %0 = %1, %2, %3"
|
||||
[(set_attr "type" "M")])
|
||||
|
||||
(define_insn "cmpxchg_acq_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "r")] 13))]
|
||||
(match_operand:DI 2 "register_operand" "r")
|
||||
(match_operand:DI 3 "ar_ccv_reg_operand" "")] 13))]
|
||||
""
|
||||
"cmpxchg8.acq %0 = %1, %2, ar.ccv"
|
||||
"cmpxchg8.acq %0 = %1, %2, %3"
|
||||
[(set_attr "type" "M")])
|
||||
|
||||
(define_expand "val_compare_and_swap_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "register_operand" "r")
|
||||
(match_operand:SI 3 "register_operand" "r")] 14))]
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")
|
||||
(match_operand:SI 3 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
rtx tmp_reg = gen_rtx_REG (DImode, GR_REG(0));
|
||||
rtx target = gen_rtx_MEM (BLKmode, tmp_reg);
|
||||
RTX_UNCHANGING_P (target) = 1;
|
||||
emit_insn (gen_ccv_restore_si (operands[2]));
|
||||
rtx target = gen_rtx_MEM (BLKmode, gen_rtx_REG (DImode, GR_REG (1)));
|
||||
rtx ccv = gen_rtx_REG (SImode, AR_CCV_REGNUM);
|
||||
emit_move_insn (ccv, operands[2]);
|
||||
emit_insn (gen_mf (target));
|
||||
emit_insn (gen_cmpxchg_acq_si (operands[0], operands[1], operands[3]));
|
||||
emit_insn (gen_cmpxchg_acq_si (operands[0], operands[1], operands[3], ccv));
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "val_compare_and_swap_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "r")
|
||||
(match_operand:DI 3 "register_operand" "r")] 14))]
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "register_operand" "")
|
||||
(match_operand:DI 3 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
rtx tmp_reg = gen_rtx_REG (DImode, GR_REG(0));
|
||||
rtx target = gen_rtx_MEM (BLKmode, tmp_reg);
|
||||
RTX_UNCHANGING_P (target) = 1;
|
||||
emit_insn (gen_ccv_restore_di (operands[2]));
|
||||
rtx target = gen_rtx_MEM (BLKmode, gen_rtx_REG (DImode, GR_REG (1)));
|
||||
rtx ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
|
||||
emit_move_insn (ccv, operands[2]);
|
||||
emit_insn (gen_mf (target));
|
||||
emit_insn (gen_cmpxchg_acq_di (operands[0], operands[1], operands[3]));
|
||||
emit_insn (gen_cmpxchg_acq_di (operands[0], operands[1], operands[3], ccv));
|
||||
DONE;
|
||||
}")
|
||||
|
||||
|
|
@ -3815,9 +3730,9 @@
|
|||
[(set_attr "type" "M")])
|
||||
|
||||
(define_expand "lock_test_and_set_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "register_operand" "r")] 16))]
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -3826,9 +3741,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "lock_test_and_set_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "r")] 16))]
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -3837,9 +3752,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "fetch_and_add_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "nonmemory_operand" "")] 18))]
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "nonmemory_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -3851,7 +3766,8 @@
|
|||
if (x == -16 || x == -8 || x == -4 || x == -1 ||
|
||||
x == 16 || x == 8 || x == 4 || x == 1)
|
||||
{
|
||||
emit_insn (gen_fetchadd_acq_si (operands[0], operands[1], operands[2]));
|
||||
emit_insn (gen_fetchadd_acq_si (operands[0], operands[1],
|
||||
operands[2]));
|
||||
DONE;
|
||||
}
|
||||
}
|
||||
|
|
@ -3861,9 +3777,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "fetch_and_sub_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "register_operand" "r")] 18))]
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -3872,9 +3788,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "fetch_and_or_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "register_operand" "r")] 18))]
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -3883,9 +3799,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "fetch_and_and_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "register_operand" "r")] 18))]
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -3894,9 +3810,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "fetch_and_xor_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "register_operand" "r")] 18))]
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -3905,9 +3821,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "fetch_and_nand_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "register_operand" "r")] 18))]
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -3916,9 +3832,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "fetch_and_add_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "nonmemory_operand" "")] 18))]
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "nonmemory_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -3930,7 +3846,8 @@
|
|||
if (x == -16 || x == -8 || x == -4 || x == -1 ||
|
||||
x == 16 || x == 8 || x == 4 || x == 1)
|
||||
{
|
||||
emit_insn (gen_fetchadd_acq_di (operands[0], operands[1], operands[2]));
|
||||
emit_insn (gen_fetchadd_acq_di (operands[0], operands[1],
|
||||
operands[2]));
|
||||
DONE;
|
||||
}
|
||||
}
|
||||
|
|
@ -3940,9 +3857,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "fetch_and_sub_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "r")] 18))]
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -3951,9 +3868,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "fetch_and_or_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "r")] 18))]
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -3962,9 +3879,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "fetch_and_and_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "r")] 18))]
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -3973,9 +3890,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "fetch_and_xor_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "r")] 18))]
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -3984,9 +3901,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "fetch_and_nand_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "r")] 18))]
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -3995,9 +3912,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "add_and_fetch_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "r")] 17))]
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -4006,9 +3923,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "sub_and_fetch_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "r")] 17))]
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -4017,9 +3934,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "or_and_fetch_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "r")] 17))]
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -4028,9 +3945,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "and_and_fetch_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "r")] 17))]
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -4039,9 +3956,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "xor_and_fetch_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "r")] 17))]
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -4050,9 +3967,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "nand_and_fetch_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "r")
|
||||
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
|
||||
(match_operand:DI 2 "register_operand" "r")] 17))]
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -4061,9 +3978,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "add_and_fetch_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "register_operand" "r")] 17))]
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -4072,9 +3989,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "sub_and_fetch_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "register_operand" "r")] 17))]
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -4083,9 +4000,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "or_and_fetch_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "register_operand" "r")] 17))]
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -4094,9 +4011,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "and_and_fetch_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "register_operand" "r")] 17))]
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -4105,9 +4022,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "xor_and_fetch_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "register_operand" "r")] 17))]
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
@ -4116,9 +4033,9 @@
|
|||
}")
|
||||
|
||||
(define_expand "nand_and_fetch_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "r")
|
||||
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")
|
||||
(match_operand:SI 2 "register_operand" "r")] 17))]
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "register_operand" "")]
|
||||
""
|
||||
"
|
||||
{
|
||||
|
|
|
|||
|
|
@ -563,33 +563,43 @@ __umodsi3:
|
|||
.global __ia64_save_stack_nonlocal
|
||||
.proc __ia64_save_stack_nonlocal
|
||||
__ia64_save_stack_nonlocal:
|
||||
alloc r18=ar.pfs,2,0,0,0
|
||||
st8 [in0]=in1,8
|
||||
mov r19=ar.rsc
|
||||
;;
|
||||
flushrs
|
||||
and r19=0x1c,r19
|
||||
mov ar.pfs=r18
|
||||
;;
|
||||
mov ar.rsc=r19
|
||||
mov r16=ar.bsp
|
||||
adds r2=16,in0
|
||||
;;
|
||||
mov r17=ar.rnat
|
||||
st8 [in0]=r16,8
|
||||
or r19=0x3,r19
|
||||
;;
|
||||
st8 [in0]=r17
|
||||
mov ar.rsc=r19
|
||||
st8 [r2]=r18
|
||||
mov ar.pfs=r18
|
||||
br.ret.sptk.few rp
|
||||
;;
|
||||
{ .mmf
|
||||
alloc r18 = ar.pfs, 2, 0, 0, 0
|
||||
mov r19 = ar.rsc
|
||||
;;
|
||||
}
|
||||
{ .mmi
|
||||
flushrs
|
||||
st8 [in0] = in1, 24
|
||||
and r19 = 0x1c, r19
|
||||
;;
|
||||
}
|
||||
{ .mmi
|
||||
st8 [in0] = r18, -16
|
||||
mov ar.rsc = r19
|
||||
or r19 = 0x3, r19
|
||||
;;
|
||||
}
|
||||
{ .mmi
|
||||
mov r16 = ar.bsp
|
||||
mov r17 = ar.rnat
|
||||
adds r2 = 8, in0
|
||||
;;
|
||||
}
|
||||
{ .mmi
|
||||
st8 [in0] = r16
|
||||
st8 [r2] = r17
|
||||
}
|
||||
{ .mib
|
||||
mov ar.rsc = r19
|
||||
br.ret.sptk.few rp
|
||||
;;
|
||||
}
|
||||
.endp __ia64_save_stack_nonlocal
|
||||
#endif
|
||||
|
||||
#ifdef L__nonlocal_goto
|
||||
// void __ia64_nonlocal_goto(void *fp, void *target_label, void *save_area,
|
||||
// void __ia64_nonlocal_goto(void *target_label, void *save_area,
|
||||
// void *static_chain);
|
||||
|
||||
.text
|
||||
|
|
@ -597,35 +607,47 @@ __ia64_save_stack_nonlocal:
|
|||
.global __ia64_nonlocal_goto
|
||||
.proc __ia64_nonlocal_goto
|
||||
__ia64_nonlocal_goto:
|
||||
alloc r20=ar.pfs,4,0,0,0
|
||||
mov r19=ar.rsc
|
||||
adds r2=8,in2
|
||||
ld8 r12=[in2],16
|
||||
mov.ret.sptk rp = r33, .L0
|
||||
;;
|
||||
flushrs
|
||||
ld8 r16=[r2],16
|
||||
and r19=0x1c,r19
|
||||
ld8 r17=[in2]
|
||||
;;
|
||||
ld8 r18=[r2]
|
||||
mov ar.rsc=r19
|
||||
;;
|
||||
mov ar.bspstore=r16
|
||||
;;
|
||||
mov ar.rnat=r17
|
||||
mov ar.pfs=r18
|
||||
or r19=0x3,r19
|
||||
;;
|
||||
loadrs
|
||||
invala
|
||||
mov r7=r32
|
||||
.L0: {
|
||||
mov ar.rsc=r19
|
||||
mov r15=r35
|
||||
br.ret.sptk.few rp
|
||||
{ .mmi
|
||||
alloc r20 = ar.pfs, 3, 0, 0, 0
|
||||
ld8 r12 = [in1], 8
|
||||
mov.ret.sptk rp = in0, .L0
|
||||
;;
|
||||
}
|
||||
{ .mmf
|
||||
ld8 r16 = [in1], 8
|
||||
mov r19 = ar.rsc
|
||||
;;
|
||||
}
|
||||
{ .mmi
|
||||
flushrs
|
||||
ld8 r17 = [in1], 8
|
||||
and r19 = 0x1c, r19
|
||||
;;
|
||||
}
|
||||
{ .mmi
|
||||
ld8 r18 = [in1]
|
||||
mov ar.rsc = r19
|
||||
or r19 = 0x3, r19
|
||||
;;
|
||||
}
|
||||
{ .mmi
|
||||
mov ar.bspstore = r16
|
||||
;;
|
||||
mov ar.rnat = r17
|
||||
;;
|
||||
}
|
||||
{ .mmi
|
||||
loadrs
|
||||
invala
|
||||
mov r15 = in2
|
||||
;;
|
||||
}
|
||||
.L0: { .mib
|
||||
mov ar.rsc = r19
|
||||
mov ar.pfs = r18
|
||||
br.ret.sptk.few rp
|
||||
;;
|
||||
}
|
||||
;;
|
||||
.endp __ia64_nonlocal_goto
|
||||
#endif
|
||||
|
||||
|
|
@ -640,31 +662,84 @@ __ia64_nonlocal_goto:
|
|||
.global __ia64_restore_stack_nonlocal
|
||||
.proc __ia64_restore_stack_nonlocal
|
||||
__ia64_restore_stack_nonlocal:
|
||||
alloc r20=ar.pfs,4,0,0,0
|
||||
mov r19=ar.rsc
|
||||
adds r2=8,in0
|
||||
ld8 r12=[in0],16
|
||||
;;
|
||||
flushrs
|
||||
ld8 r16=[r2],16
|
||||
and r19=0x1c,r19
|
||||
ld8 r17=[in0]
|
||||
;;
|
||||
ld8 r18=[r2]
|
||||
mov ar.rsc=r19
|
||||
;;
|
||||
mov ar.bspstore=r16
|
||||
;;
|
||||
mov ar.rnat=r17
|
||||
mov ar.pfs=r18
|
||||
or r19=0x3,r19
|
||||
;;
|
||||
loadrs
|
||||
invala
|
||||
.L0: {
|
||||
mov ar.rsc=r19
|
||||
br.ret.sptk.few rp
|
||||
{ .mmf
|
||||
alloc r20 = ar.pfs, 4, 0, 0, 0
|
||||
ld8 r12 = [in0], 8
|
||||
;;
|
||||
}
|
||||
{ .mmb
|
||||
ld8 r16=[in0], 8
|
||||
mov r19 = ar.rsc
|
||||
;;
|
||||
}
|
||||
{ .mmi
|
||||
flushrs
|
||||
ld8 r17 = [in0], 8
|
||||
and r19 = 0x1c, r19
|
||||
;;
|
||||
}
|
||||
{ .mmf
|
||||
ld8 r18 = [in0]
|
||||
mov ar.rsc = r19
|
||||
;;
|
||||
}
|
||||
{ .mmi
|
||||
mov ar.bspstore = r16
|
||||
;;
|
||||
mov ar.rnat = r17
|
||||
or r19 = 0x3, r19
|
||||
;;
|
||||
}
|
||||
{ .mmf
|
||||
loadrs
|
||||
invala
|
||||
;;
|
||||
}
|
||||
.L0: { .mib
|
||||
mov ar.rsc = r19
|
||||
mov ar.pfs = r18
|
||||
br.ret.sptk.few rp
|
||||
;;
|
||||
}
|
||||
;;
|
||||
.endp __ia64_restore_stack_nonlocal
|
||||
#endif
|
||||
|
||||
#ifdef L__trampoline
|
||||
// Implement the nested function trampoline. This is out of line
|
||||
// so that we don't have to bother with flushing the icache, as
|
||||
// well as making the on-stack trampoline smaller.
|
||||
//
|
||||
// The trampoline has the following form:
|
||||
//
|
||||
// +-------------------+ \
|
||||
// TRAMP: | __ia64_trampoline | |
|
||||
// +-------------------+ > fake function descriptor
|
||||
// | TRAMP+16 | |
|
||||
// +-------------------+ /
|
||||
// | target descriptor |
|
||||
// +-------------------+
|
||||
// | static link |
|
||||
// +-------------------+
|
||||
|
||||
.text
|
||||
.align 16
|
||||
.global __ia64_trampoline
|
||||
.proc __ia64_trampoline
|
||||
__ia64_trampoline:
|
||||
{ .mmi
|
||||
ld8 r2 = [r1], 8
|
||||
;;
|
||||
ld8 r15 = [r1]
|
||||
}
|
||||
{ .mmi
|
||||
ld8 r3 = [r2], 8
|
||||
;;
|
||||
ld8 r1 = [r2]
|
||||
mov b6 = r3
|
||||
}
|
||||
{ .bbb
|
||||
br.sptk.many b6
|
||||
;;
|
||||
}
|
||||
.endp __ia64_trampoline
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -115,14 +115,8 @@ while (0)
|
|||
} while (0)
|
||||
|
||||
/* svr4.h undefines this, so we need to define it here. */
|
||||
#define DBX_REGISTER_NUMBER(REGNO) \
|
||||
(IN_REGNO_P (REGNO) ? (32 + (REGNO) - IN_REG (0)) \
|
||||
: LOC_REGNO_P (REGNO) ? (32 + ia64_input_regs + \
|
||||
(REGNO) - LOC_REG (0)) \
|
||||
: OUT_REGNO_P (REGNO) ? (32 + ia64_input_regs + ia64_local_regs \
|
||||
+ (REGNO) - OUT_REG (0)) \
|
||||
: (REGNO) == FRAME_POINTER_REGNUM ? ia64_fp_regno \
|
||||
: (REGNO))
|
||||
#define DBX_REGISTER_NUMBER(REGNO) \
|
||||
ia64_dbx_register_number(REGNO)
|
||||
|
||||
/* Things that svr4.h defines to the wrong type, because it assumes 32 bit
|
||||
ints and 32 bit longs. */
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ LIB1ASMSRC = ia64/lib1funcs.asm
|
|||
LIB1ASMFUNCS = __divdf3 __divsf3 \
|
||||
__divdi3 __moddi3 __udivdi3 __umoddi3 \
|
||||
__divsi3 __modsi3 __udivsi3 __umodsi3 __save_stack_nonlocal \
|
||||
__nonlocal_goto __restore_stack_nonlocal
|
||||
__nonlocal_goto __restore_stack_nonlocal __trampoline
|
||||
|
||||
# ??? Hack to get -P option used when compiling lib1funcs.asm, because Intel
|
||||
# assembler does not accept # line number as a comment.
|
||||
|
|
|
|||
Loading…
Reference in New Issue