i386: Always use TARGET_DEEP_BRANCH_PREDICTION.
While it could be possible to output_set_got such that we can
individually annotate the instructions, it's simpler to simply
admit that all processors currently being manufactured do want
deep branch prediction. At which point all of the complication
simply goes away.
* config/i386/i386.h (X86_TUNE_DEEP_BRANCH_PREDICTION): Remove.
(TARGET_DEEP_BRANCH_PREDICTION): Remove.
* config/i386/i386.c: Don't include dwarf2out.h.
(initial_ix86_tune_features): Remove X86_TUNE_DEEP_BRANCH_PREDICTION.
(output_set_got): Don't test TARGET_DEEP_BRANCH_PREDICTION, delete
all code dead thereafter. Don't do dwarf2out_flush_queued_reg_saves.
(ix86_expand_prologue): Set REG_CFA_FLUSH_QUEUE on set_got insn.
(machopic_output_stub): Don't test TARGET_DEEP_BRANCH_PREDICTION.
From-SVN: r175730
This commit is contained in:
Richard Henderson
Richard Henderson
parent
ef284364b4
commit
97f309c3e2
@ -1,3 +1,14 @@
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2011-06-30 Richard Henderson <rth@redhat.com>
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* config/i386/i386.h (X86_TUNE_DEEP_BRANCH_PREDICTION): Remove.
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(TARGET_DEEP_BRANCH_PREDICTION): Remove.
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* config/i386/i386.c: Don't include dwarf2out.h.
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(initial_ix86_tune_features): Remove X86_TUNE_DEEP_BRANCH_PREDICTION.
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(output_set_got): Don't test TARGET_DEEP_BRANCH_PREDICTION, delete
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all code dead thereafter. Don't do dwarf2out_flush_queued_reg_saves.
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(ix86_expand_prologue): Set REG_CFA_FLUSH_QUEUE on set_got insn.
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(machopic_output_stub): Don't test TARGET_DEEP_BRANCH_PREDICTION.
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2011-06-30 Richard Henderson <rth@redhat.com>
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* reg-notes.def (REG_CFA_FLUSH_QUEUE): New.
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@ -55,7 +55,6 @@ along with GCC; see the file COPYING3. If not see
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#include "params.h"
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#include "cselib.h"
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#include "debug.h"
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#include "dwarf2out.h"
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#include "sched-int.h"
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#include "sbitmap.h"
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#include "fibheap.h"
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@ -1847,10 +1846,6 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
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| m_CORE2I7 | m_GENERIC,
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/* X86_TUNE_DEEP_BRANCH_PREDICTION */
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m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
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| m_CORE2I7 | m_GENERIC,
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/* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
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on simulation result. But after P4 was made, no performance benefit
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was observed with branch hints. It also increases the code size.
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@ -8331,31 +8326,11 @@ output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
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xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
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if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
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if (!flag_pic)
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{
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xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
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if (!flag_pic)
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output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
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else
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{
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output_asm_insn ("call\t%a2", xops);
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#ifdef DWARF2_UNWIND_INFO
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/* The call to next label acts as a push. */
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if (dwarf2out_do_frame ())
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{
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rtx insn;
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start_sequence ();
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insn = emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
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gen_rtx_PLUS (Pmode,
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stack_pointer_rtx,
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GEN_INT (-4))));
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RTX_FRAME_RELATED_P (insn) = 1;
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dwarf2out_frame_debug (insn, true);
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end_sequence ();
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}
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#endif
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}
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output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
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#if TARGET_MACHO
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/* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
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@ -8366,29 +8341,6 @@ output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
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targetm.asm_out.internal_label (asm_out_file, "L",
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CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
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if (flag_pic)
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{
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output_asm_insn ("pop%z0\t%0", xops);
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#ifdef DWARF2_UNWIND_INFO
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/* The pop is a pop and clobbers dest, but doesn't restore it
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for unwind info purposes. */
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if (dwarf2out_do_frame ())
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{
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rtx insn;
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start_sequence ();
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insn = emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
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dwarf2out_frame_debug (insn, true);
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insn = emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
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gen_rtx_PLUS (Pmode,
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stack_pointer_rtx,
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GEN_INT (4))));
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RTX_FRAME_RELATED_P (insn) = 1;
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dwarf2out_frame_debug (insn, true);
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end_sequence ();
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}
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#endif
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}
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}
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else
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{
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@ -8396,12 +8348,6 @@ output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
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get_pc_thunk_name (name, REGNO (dest));
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pic_labels_used |= 1 << REGNO (dest);
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#ifdef DWARF2_UNWIND_INFO
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/* Ensure all queued register saves are flushed before the
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call. */
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if (dwarf2out_do_frame ())
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dwarf2out_flush_queued_reg_saves ();
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#endif
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xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
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xops[2] = gen_rtx_MEM (QImode, xops[2]);
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output_asm_insn ("call\t%X2", xops);
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@ -8416,13 +8362,8 @@ output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
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#endif
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}
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if (TARGET_MACHO)
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return "";
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if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
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if (!TARGET_MACHO)
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output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
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else
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output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
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return "";
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}
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@ -10146,7 +10087,11 @@ ix86_expand_prologue (void)
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insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
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}
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else
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insn = emit_insn (gen_set_got (pic_offset_table_rtx));
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{
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insn = emit_insn (gen_set_got (pic_offset_table_rtx));
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RTX_FRAME_RELATED_P (insn) = 1;
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add_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL_RTX);
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}
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}
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/* In the pic_reg_used case, make sure that the got load isn't deleted
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@ -28987,12 +28932,7 @@ machopic_output_stub (FILE *file, const char *symb, const char *stub)
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if (MACHOPIC_ATT_STUB)
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switch_to_section (darwin_sections[machopic_picsymbol_stub3_section]);
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else if (MACHOPIC_PURE)
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{
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if (TARGET_DEEP_BRANCH_PREDICTION)
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switch_to_section (darwin_sections[machopic_picsymbol_stub2_section]);
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else
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switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
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}
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switch_to_section (darwin_sections[machopic_picsymbol_stub2_section]);
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else
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switch_to_section (darwin_sections[machopic_symbol_stub_section]);
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@ -29006,19 +28946,11 @@ machopic_output_stub (FILE *file, const char *symb, const char *stub)
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else if (MACHOPIC_PURE)
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{
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/* PIC stub. */
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if (TARGET_DEEP_BRANCH_PREDICTION)
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{
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/* 25-byte PIC stub using "CALL get_pc_thunk". */
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rtx tmp = gen_rtx_REG (SImode, 2 /* ECX */);
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output_set_got (tmp, NULL_RTX); /* "CALL ___<cpu>.get_pc_thunk.cx". */
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fprintf (file, "LPC$%d:\tmovl\t%s-LPC$%d(%%ecx),%%ecx\n", label, lazy_ptr_name, label);
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}
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else
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{
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/* 26-byte PIC stub using inline picbase: "CALL L42 ! L42: pop %eax". */
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fprintf (file, "\tcall LPC$%d\nLPC$%d:\tpopl %%ecx\n", label, label);
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fprintf (file, "\tmovl %s-LPC$%d(%%ecx),%%ecx\n", lazy_ptr_name, label);
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}
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/* 25-byte PIC stub using "CALL get_pc_thunk". */
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rtx tmp = gen_rtx_REG (SImode, 2 /* ECX */);
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output_set_got (tmp, NULL_RTX); /* "CALL ___<cpu>.get_pc_thunk.cx". */
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fprintf (file, "LPC$%d:\tmovl\t%s-LPC$%d(%%ecx),%%ecx\n",
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label, lazy_ptr_name, label);
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fprintf (file, "\tjmp\t*%%ecx\n");
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}
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else
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@ -29047,13 +28979,8 @@ machopic_output_stub (FILE *file, const char *symb, const char *stub)
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compatibility with existing dylibs. */
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if (MACHOPIC_PURE)
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{
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/* PIC stubs. */
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if (TARGET_DEEP_BRANCH_PREDICTION)
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/* 25-byte PIC stub using "CALL get_pc_thunk". */
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switch_to_section (darwin_sections[machopic_lazy_symbol_ptr2_section]);
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else
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/* 26-byte PIC stub using inline picbase: "CALL L42 ! L42: pop %ebx". */
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switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
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/* 25-byte PIC stub using "CALL get_pc_thunk". */
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switch_to_section (darwin_sections[machopic_lazy_symbol_ptr2_section]);
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}
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else
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/* 16-byte -mdynamic-no-pic stub. */
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@ -249,7 +249,6 @@ enum ix86_tune_indices {
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X86_TUNE_PUSH_MEMORY,
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X86_TUNE_ZERO_EXTEND_WITH_AND,
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X86_TUNE_UNROLL_STRLEN,
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X86_TUNE_DEEP_BRANCH_PREDICTION,
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X86_TUNE_BRANCH_PREDICTION_HINTS,
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X86_TUNE_DOUBLE_WITH_ADD,
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X86_TUNE_USE_SAHF,
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@ -324,8 +323,6 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
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#define TARGET_ZERO_EXTEND_WITH_AND \
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ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
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#define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
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#define TARGET_DEEP_BRANCH_PREDICTION \
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ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
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#define TARGET_BRANCH_PREDICTION_HINTS \
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ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
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#define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
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