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ChangeLog: Follow spelling conventions. 

* ChangeLog: Follow spelling conventions.
	* ChangeLog.0: Likewise.
	* ChangeLog.1: Likewise.
	* ChangeLog.2: Likewise.
	* ChangeLog.4: Likewise.
	* ChangeLog.6: Likewise.
	* config.gcc: Likewise.
	* dwarfout.c: Likewise.
	* reload1.c: Likewise.
	* simplify-rtx.c: Likewise.
	* unwind-sjlj.c: Likewise.
	* config/avr/avr.h: Likewise.
	* config/d30v/d30v.h: Likewise.
	* config/frv/frv.c: Likewise.
	* config/frv/frv.h: Likewise.
	* config/ip2k/ip2k.h: Likewise.
	* config/m88k/m88k-move.sh: Likewise.
	* config/stormy16/stormy16.c: Likewise.
	* config/stormy16/stormy16.h: Likewise.
	* doc/extend.texi: Likewise.
	* doc/interface.texi: Likewise.
	* doc/invoke.texi: Likewise.
	* doc/md.texi: Likewise.
	* doc/rtl.texi: Likewise.
	* doc/tm.texi: Likewise.
	* doc/trouble.texi: Likewise.
	* ginclude/float.h: Likewise.
	* treelang/treelang.texi: Likewise.

From-SVN: r57179
This commit is contained in:
Kazu Hirata 2002-09-15 22:48:06 +00:00
parent 6578c58188
commit 981f6289ab
28 changed files with 92 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
gcc/ChangeLog
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@ -1,3 +1,34 @@
2002-09-15 Kazu Hirata <kazu@cs.umass.edu>
* ChangeLog: Follow spelling conventions.
* ChangeLog.0: Likewise.
* ChangeLog.1: Likewise.
* ChangeLog.2: Likewise.
* ChangeLog.4: Likewise.
* ChangeLog.6: Likewise.
* config.gcc: Likewise.
* dwarfout.c: Likewise.
* reload1.c: Likewise.
* simplify-rtx.c: Likewise.
* unwind-sjlj.c: Likewise.
* config/avr/avr.h: Likewise.
* config/d30v/d30v.h: Likewise.
* config/frv/frv.c: Likewise.
* config/frv/frv.h: Likewise.
* config/ip2k/ip2k.h: Likewise.
* config/m88k/m88k-move.sh: Likewise.
* config/stormy16/stormy16.c: Likewise.
* config/stormy16/stormy16.h: Likewise.
* doc/extend.texi: Likewise.
* doc/interface.texi: Likewise.
* doc/invoke.texi: Likewise.
* doc/md.texi: Likewise.
* doc/rtl.texi: Likewise.
* doc/tm.texi: Likewise.
* doc/trouble.texi: Likewise.
* ginclude/float.h: Likewise.
* treelang/treelang.texi: Likewise.
2002-09-15 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* i386-protos.h (i386_pe_dllexport_name_p,
@ -15272,7 +15303,7 @@ Sat May 4 13:20:54 CEST 2002 Jan Hubicka <jh@suse.cz>
config/sparc/ultra1_2.md, config/sparc/ultra3.md: ... into here.
* config/sparc/sparc.c (LEAF_REGISTERS): Do not do ifdef
checks on it, always defined for Sparc.
checks on it, always defined for SPARC.
* config/sparc/sparc.h (REG_ALLOC_ORDER, REG_LEAF_ALLOC_ORDER):
Tweak, and add more detailed comments.
@ -15962,7 +15993,7 @@ Tue Apr 30 09:31:59 2002 Jeffrey A Law (law@redhat.com)
2001-09-25 David S. Miller <davem@redhat.com>
Convert all of Sparc scheduling to DFA
Convert all of SPARC scheduling to DFA
* config/sparc/sparc.md: Kill all define_function_unit
directives and replace with DFA equivalent.
* config/sparc/sparc.c (ultrasparc_adjust_cost,
@ -16695,7 +16726,7 @@ objc:
PR target/6420
* config/sparc/sparc.h (FUNCTION_OK_FOR_SIBCALL): Return false if
32-bit Sparc and current_function_returns_struct is true.
32-bit SPARC and current_function_returns_struct is true.
Wed Apr 24 13:48:25 CEST 2002 Jan Hubicka <jh@suse.cz>
@ -18138,7 +18169,7 @@ Tue Apr 9 09:35:45 2002 Richard Kenner <kenner@vlsi1.ultra.nyu.edu>
PR target/6082
* config/sparc/freebsd.h (SPARC_DEFAULT_CMODEL): Set to CM_MEDLOW
Make init_priority work on Sparc when using GNU ld.
Make init_priority work on SPARC when using GNU ld.
* config/sparc/linux.h, config/sparc/linux64.h,
config/sparc/netbsd-elf.h, config/sparc/freebsd.h
(CTORS_SECTION_ASM_OP, DTORS_SECTION_ASM_OP): Undefine.

2
gcc/ChangeLog.0
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@ -4435,7 +4435,7 @@ Sun May 3 23:57:25 1998 Robert Lipe <robertl@dgii.com>
Sun May 3 13:51:34 1998 Richard Henderson <rth@cygnus.com>
Support for official Sparc V9 ABI:
Support for official SPARC V9 ABI:
* sparc.c (sparc_override_options): Force stack bias off for !arch64.
Care for flag_pcc_struct_return default.
(output_move_quad): Rewrite to move by halves on v9 and in the

8
gcc/ChangeLog.1
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@ -7018,7 +7018,7 @@ Thu Jan 7 03:08:17 1999 Richard Henderson <rth@cygnus.com>
Thu Jan 7 03:03:42 1999 Stan Cox <scox@cygnus.com>
Richard Henderson <rth@cygnus.com>
Support for Hypersparc and Sparclite86x:
Support for HyperSPARC and SPARClite86x:
* sparc.h (TARGET_CPU_hypersparc, TARGET_CPU_sparclite86x): New.
(CPP_CPU32_DEFAULT_SPEC): Fix up for the new targets.
(ASM_CPU32_DEFAULT_SPEC): Likewise.
@ -15068,7 +15068,7 @@ Mon Aug 10 19:02:55 1998 John Carr <jfc@mit.edu>
Mon Aug 10 04:28:13 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
Richard Henderson <rth@cygnus.com>
Rewrite Sparc backend for better code generation and
Rewrite SPARC backend for better code generation and
improved sparc64 support.
* config/sparc/sp64-elf.h: Set JUMP_TABLES_IN_TEXT_SECTION to
zero.
@ -15155,7 +15155,7 @@ Mon Aug 10 04:28:13 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
(define_function_unit ieu1): New, executes compare, call, and
uncond_branch type insns.
(define_function_units for type fdivs, fdivd, fsqrt): These
execute in the fpu multiply unit not the adder on UltraSparc.
execute in the fpu multiply unit not the adder on UltraSPARC.
(define_expand cmpdi): Disallow TARGET_V8PLUS.
(define_insn cmpsi_insn): Rename to cmpsi_insn_sp32.
(define_insn cmpsi_insn_sp64): New, same as sp32 variant except it
@ -15570,7 +15570,7 @@ Mon Jul 27 14:22:36 1998 Dave Brolley <brolley@cygnus.com>
Mon Jul 27 11:43:54 1998 Stan Cox <scox@cygnus.com>
* longlong.h (count_leading_zeros): Sparclite scan instruction was
* longlong.h (count_leading_zeros): SPARClite scan instruction was
being invoked incorrectly.
* i386.c (ix86_prologue): Added SUBTARGET_PROLOGUE invocation.

4
gcc/ChangeLog.2
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@ -3184,13 +3184,13 @@ Wed Nov 3 15:11:27 1999 David S. Miller <davem@redhat.com>
* config/sparc/sparc.md: Remove insn type fpsqrt, add fpsqrts
and fpsqrtd. Use them and create fdiv function unit to more
accurately represent fpu sqrt pipeline semantics on UltraSparc.
accurately represent fpu sqrt pipeline semantics on UltraSPARC.
* config/sparc/sparc.c: Account for fpsqrt{s,d} changes.
Wed Nov 3 15:11:27 1999 Matteo Frigo <athena@fftw.org>
* config/sparc/sparc.md: Adjust FADD/FMUL result latencies to
3 on UltraSparc.
3 on UltraSPARC.
* config/sparc/sparc.c (ultra_schedule_insn): Insert launched
insn into ready list, do not use just a raw swap.

2
gcc/ChangeLog.4
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@ -3247,7 +3247,7 @@ Wed Nov 22 00:52:55 2000 J"orn Rennecke <amylaar@redhat.com>
2000-11-21 Jakub Jelinek <jakub@redhat.com>
* configure.in (HAVE_AS_DWARF2_DEBUG_LINE): Sparc has .file/.loc
* configure.in (HAVE_AS_DWARF2_DEBUG_LINE): SPARC has .file/.loc
support in as as well.
* configure: Regenerate.

2
gcc/ChangeLog.6
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@ -6891,7 +6891,7 @@ Sat Nov 3 10:37:56 2001 Richard Kenner <kenner@vlsi1.ultra.nyu.edu>
2001-11-01 David S. Miller <davem@redhat.com>
* doc/install.texi (Specific, sparc-sun-solaris2*): Bring
64-bit Sparc description more in line with reality.
64-bit SPARC description more in line with reality.
2001-11-01 Joseph S. Myers <jsm28@cam.ac.uk>

8
gcc/config.gcc
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@ -2330,17 +2330,17 @@ sparc-*-elf*)
tmake_file="sparc/t-elf sparc/t-crtfm"
extra_parts="crti.o crtn.o crtbegin.o crtend.o"
;;
sparc-*-linux*aout*) # Sparc's running GNU/Linux, a.out
sparc-*-linux*aout*) # SPARC's running GNU/Linux, a.out
tm_file="aoutos.h sparc/sparc.h sparc/aout.h sparc/linux-aout.h"
gnu_ld=yes
;;
sparc-*-linux*libc1*) # Sparc's running GNU/Linux, libc5
sparc-*-linux*libc1*) # SPARC's running GNU/Linux, libc5
tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/linux.h"
tmake_file="t-slibgcc-elf-ver t-linux t-linux-gnulibc1 sparc/t-crtfm"
extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o"
gnu_ld=yes
;;
sparc-*-linux*) # Sparc's running GNU/Linux, libc6
sparc-*-linux*) # SPARC's running GNU/Linux, libc6
tm_file="${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/linux.h"
tmake_file="t-slibgcc-elf-ver t-linux sparc/t-crtfm"
;;
@ -2524,7 +2524,7 @@ sparc64-*-freebsd*|ultrasparc-*-freebsd*)
*) echo "$with_cpu not supported for freebsd target"; exit 1 ;;
esac
;;
sparc64-*-linux*) # 64-bit Sparc's running GNU/Linux
sparc64-*-linux*) # 64-bit SPARC's running GNU/Linux
tmake_file="t-slibgcc-elf-ver t-linux sparc/t-linux64 sparc/t-crtfm"
tm_file="sparc/biarch64.h ${tm_file} dbxelf.h elfos.h svr4.h sparc/sysv4.h sparc/linux64.h"
;;

2
gcc/config/avr/avr.h
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@ -675,7 +675,7 @@ enum reg_class {
machines allow copying all registers to and from memory, but
require a scratch register for stores to some memory locations
(e.g., those with symbolic address on the RT, and those with
certain symbolic address on the Sparc when compiling PIC). In
certain symbolic address on the SPARC when compiling PIC). In
some cases, both an intermediate and a scratch register are
required.

8
gcc/config/d30v/d30v.h
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@ -823,7 +823,7 @@ extern enum reg_class reg_class_from_letter[256];
registers, but not memory. Some machines allow copying all registers to and
from memory, but require a scratch register for stores to some memory
locations (e.g., those with symbolic address on the RT, and those with
certain symbolic address on the Sparc when compiling PIC). In some cases,
certain symbolic address on the SPARC when compiling PIC). In some cases,
both an intermediate and a scratch register are required.
You should define these macros to indicate to the reload phase that it may
@ -1109,7 +1109,7 @@ typedef struct d30v_stack {
/* If defined, a C expression that produces the machine-specific code to setup
the stack so that arbitrary frames can be accessed. For example, on the
Sparc, we must flush all of the register windows to the stack before we can
SPARC, we must flush all of the register windows to the stack before we can
access arbitrary stack frames. This macro will seldom need to be defined. */
/* #define SETUP_FRAME_ADDRESSES() */
@ -2415,7 +2415,7 @@ do { \
/* #define EXTRA_CC_MODES */
/* Returns a mode from class `MODE_CC' to be used when comparison operation
code OP is applied to rtx X and Y. For example, on the Sparc,
code OP is applied to rtx X and Y. For example, on the SPARC,
`SELECT_CC_MODE' is defined as (see *note Jump Patterns::. for a
description of the reason for this definition)
@ -2453,7 +2453,7 @@ do { \
You need not define this macro if it would always returns zero or if the
floating-point format is anything other than `IEEE_FLOAT_FORMAT'. For
example, here is the definition used on the Sparc, where floating-point
example, here is the definition used on the SPARC, where floating-point
inequality comparisons are always given `CCFPEmode':
#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) */

2
gcc/config/frv/frv.c
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@ -7629,7 +7629,7 @@ frv_initialize_trampoline (addr, fnaddr, static_chain)
registers, but not memory. Some machines allow copying all registers to and
from memory, but require a scratch register for stores to some memory
locations (e.g., those with symbolic address on the RT, and those with
certain symbolic address on the Sparc when compiling PIC). In some cases,
certain symbolic address on the SPARC when compiling PIC). In some cases,
both an intermediate and a scratch register are required.
You should define these macros to indicate to the reload phase that it may

4
gcc/config/frv/frv.h
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@ -2568,7 +2568,7 @@ __asm__("\n" \
/* Returns a mode from class `MODE_CC' to be used when comparison operation
code OP is applied to rtx X and Y. For example, on the Sparc,
code OP is applied to rtx X and Y. For example, on the SPARC,
`SELECT_CC_MODE' is defined as (see *note Jump Patterns::. for a
description of the reason for this definition)
@ -2594,7 +2594,7 @@ __asm__("\n" \
You need not define this macro if it would always returns zero or if the
floating-point format is anything other than `IEEE_FLOAT_FORMAT'. For
example, here is the definition used on the Sparc, where floating-point
example, here is the definition used on the SPARC, where floating-point
inequality comparisons are always given `CCFPEmode':
#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) */

2
gcc/config/ip2k/ip2k.h
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@ -801,7 +801,7 @@ enum reg_class {
machines allow copying all registers to and from memory, but
require a scratch register for stores to some memory locations
(e.g., those with symbolic address on the RT, and those with
certain symbolic address on the Sparc when compiling PIC). In
certain symbolic address on the SPARC when compiling PIC). In
some cases, both an intermediate and a scratch register are
required.

2
gcc/config/m88k/m88k-move.sh
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@ -44,7 +44,7 @@
# 27-Aug-90 Vince Guarna/Tom Wood
# Version 3 assembler syntax (-abi).
# 16-Aug-90 Ron Guilmette
# Avoid problems on a Sparc. The common
# Avoid problems on a SPARC. The common
# denominator among shells seems to be '...\'
# rather than '...\\'.
# 15-Aug-90 Ron Guilmette

2
gcc/config/stormy16/stormy16.c
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@ -407,7 +407,7 @@ xstormy16_output_cbranch_si (op, label, reversed, insn)
registers, but not memory. Some machines allow copying all registers to and
from memory, but require a scratch register for stores to some memory
locations (e.g., those with symbolic address on the RT, and those with
certain symbolic address on the Sparc when compiling PIC). In some cases,
certain symbolic address on the SPARC when compiling PIC). In some cases,
both an intermediate and a scratch register are required.
You should define these macros to indicate to the reload phase that it may

8
gcc/config/stormy16/stormy16.h
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@ -576,7 +576,7 @@ enum reg_class
registers, but not memory. Some machines allow copying all registers to and
from memory, but require a scratch register for stores to some memory
locations (e.g., those with symbolic address on the RT, and those with
certain symbolic address on the Sparc when compiling PIC). In some cases,
certain symbolic address on the SPARC when compiling PIC). In some cases,
both an intermediate and a scratch register are required.
You should define these macros to indicate to the reload phase that it may
@ -841,7 +841,7 @@ enum reg_class
/* If defined, a C expression that produces the machine-specific code to setup
the stack so that arbitrary frames can be accessed. For example, on the
Sparc, we must flush all of the register windows to the stack before we can
SPARC, we must flush all of the register windows to the stack before we can
access arbitrary stack frames. This macro will seldom need to be defined. */
/* #define SETUP_FRAME_ADDRESSES() */
@ -2189,7 +2189,7 @@ do { \
/* #define EXTRA_CC_MODES */
/* Returns a mode from class `MODE_CC' to be used when comparison operation
code OP is applied to rtx X and Y. For example, on the Sparc,
code OP is applied to rtx X and Y. For example, on the SPARC,
`SELECT_CC_MODE' is defined as (see *note Jump Patterns::. for a
description of the reason for this definition)
@ -2227,7 +2227,7 @@ do { \
You need not define this macro if it would always returns zero or if the
floating-point format is anything other than `IEEE_FLOAT_FORMAT'. For
example, here is the definition used on the Sparc, where floating-point
example, here is the definition used on the SPARC, where floating-point
inequality comparisons are always given `CCFPEmode':
#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) */

4
gcc/doc/extend.texi
View File

@ -3235,7 +3235,7 @@ typedef int more_aligned_int __attribute__ ((aligned (8)));
@noindent
force the compiler to insure (as far as it can) that each variable whose
type is @code{struct S} or @code{more_aligned_int} will be allocated and
aligned @emph{at least} on a 8-byte boundary. On a Sparc, having all
aligned @emph{at least} on a 8-byte boundary. On a SPARC, having all
variables of type @code{struct S} aligned to 8-byte boundaries allows
the compiler to use the @code{ldd} and @code{std} (doubleword load and
store) instructions when copying one variable of type @code{struct S} to
@ -4140,7 +4140,7 @@ being used for other purposes in the preceding functions.
Global register variables may not have initial values, because an
executable file has no means to supply initial contents for a register.
On the Sparc, there are reports that g3 @dots{} g7 are suitable
On the SPARC, there are reports that g3 @dots{} g7 are suitable
registers, but certain library functions, such as @code{getwd}, as well
as the subroutines for division and remainder, modify g3 and g4. g1 and
g2 are local temporaries.

2
gcc/doc/interface.texi
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@ -57,7 +57,7 @@ compiler for the system. We may implement register argument passing on
certain machines once we have a complete GNU system so that we can
compile the libraries with GCC@.
On some machines (particularly the Sparc), certain types of arguments
On some machines (particularly the SPARC), certain types of arguments
are passed ``by invisible reference''. This means that the value is
stored in memory, and the address of the memory location is passed to
the subroutine.

16
gcc/doc/invoke.texi
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@ -3725,7 +3725,7 @@ in the output file.
Use these options on systems where the linker can perform optimizations
to improve locality of reference in the instruction space. HPPA
processors running HP-UX and Sparc processors running Solaris 2 have
processors running HP-UX and SPARC processors running Solaris 2 have
linkers with such optimizations. Other systems using the ELF object format
as well as AIX may have these optimizations in the future.
@ -5363,7 +5363,7 @@ With @option{-mfaster-structs}, the compiler assumes that structures
should have 8 byte alignment. This enables the use of pairs of
@code{ldd} and @code{std} instructions for copies in structure
assignment, in place of twice as many @code{ld} and @code{st} pairs.
However, the use of this changed alignment directly violates the Sparc
However, the use of this changed alignment directly violates the SPARC
ABI@. Thus, it's intended only for use on targets where the developer
acknowledges that their resulting code will not be directly in line with
the rules of the ABI@.
@ -5395,11 +5395,11 @@ They have been replaced with @option{-mcpu=xxx}.
These two options select the processor for which the code is optimized.
With @option{-mcypress} (the default), the compiler optimizes code for the
Cypress CY7C602 chip, as used in the SparcStation/SparcServer 3xx series.
This is also appropriate for the older SparcStation 1, 2, IPX etc.
Cypress CY7C602 chip, as used in the SPARCStation/SPARCServer 3xx series.
This is also appropriate for the older SPARCStation 1, 2, IPX etc.
With @option{-msupersparc} the compiler optimizes code for the SuperSparc cpu, as
used in the SparcStation 10, 1000 and 2000 series. This flag also enables use
With @option{-msupersparc} the compiler optimizes code for the SuperSPARC cpu, as
used in the SPARCStation 10, 1000 and 2000 series. This flag also enables use
of the full SPARC v8 instruction set.
These options are deprecated and will be deleted in a future GCC release.
@ -10027,7 +10027,7 @@ loader is not part of GCC; it is part of the operating system). If
the GOT size for the linked executable exceeds a machine-specific
maximum size, you get an error message from the linker indicating that
@option{-fpic} does not work; in that case, recompile with @option{-fPIC}
instead. (These maximums are 16k on the m88k, 8k on the Sparc, and 32k
instead. (These maximums are 16k on the m88k, 8k on the SPARC, and 32k
on the m68k and RS/6000. The 386 has no such limit.)
Position-independent code requires special support, and therefore works
@ -10040,7 +10040,7 @@ position-independent.
If supported for the target machine, emit position-independent code,
suitable for dynamic linking and avoiding any limit on the size of the
global offset table. This option makes a difference on the m68k, m88k,
and the Sparc.
and the SPARC.
Position-independent code requires special support, and therefore works
only on certain machines.

8
gcc/doc/md.texi
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@ -3480,7 +3480,7 @@ multiple condition registers, use a pseudo register.
@findex next_cc0_user
On some machines, the type of branch instruction generated may depend on
the way the condition code was produced; for example, on the 68k and
Sparc, setting the condition code directly from an add or subtract
SPARC, setting the condition code directly from an add or subtract
instruction does not clear the overflow bit the way that a test
instruction does, so a different branch instruction must be used for
some conditional branches. For machines that use @code{(cc0)}, the set
@ -3499,7 +3499,7 @@ different formats of the condition code register.
Registers used to store the condition code value should have a mode that
is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
additional modes are required (as for the add example mentioned above in
the Sparc), define the macro @code{EXTRA_CC_MODES} to list the
the SPARC), define the macro @code{EXTRA_CC_MODES} to list the
additional modes required (@pxref{Condition Code}). Also define
@code{SELECT_CC_MODE} to choose a mode given an operand of a compare.
@ -3511,7 +3511,7 @@ be specified at that time.
If the cases that require different modes would be made by instruction
combination, the macro @code{SELECT_CC_MODE} determines which machine
mode should be used for the comparison result. The patterns should be
written using that mode. To support the case of the add on the Sparc
written using that mode. To support the case of the add on the SPARC
discussed above, we have the pattern
@smallexample
@ -3525,7 +3525,7 @@ discussed above, we have the pattern
"@dots{}")
@end smallexample
The @code{SELECT_CC_MODE} macro on the Sparc returns @code{CC_NOOVmode}
The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode}
for comparisons whose argument is a @code{plus}.
@node Looping Patterns

2
gcc/doc/rtl.texi
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@ -1545,7 +1545,7 @@ preferable approach if only a small subset of instructions modify the
condition code. Other machines store condition codes in general
registers; in such cases a pseudo register should be used.
Some machines, such as the Sparc and RS/6000, have two sets of
Some machines, such as the SPARC and RS/6000, have two sets of
arithmetic instructions, one that sets and one that does not set the
condition code. This is best handled by normally generating the
instruction that does not set the condition code, and making a pattern

8
gcc/doc/tm.texi
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@ -2410,7 +2410,7 @@ from memory or even from other types of registers. An example is the
from general registers, but not memory. Some machines allow copying all
registers to and from memory, but require a scratch register for stores
to some memory locations (e.g., those with symbolic address on the RT,
and those with certain symbolic address on the Sparc when compiling
and those with certain symbolic address on the SPARC when compiling
PIC)@. In some cases, both an intermediate and a scratch register are
required.
@ -2790,7 +2790,7 @@ address of the stack word that points to the previous frame.
@item SETUP_FRAME_ADDRESSES
If defined, a C expression that produces the machine-specific code to
setup the stack so that arbitrary frames can be accessed. For example,
on the Sparc, we must flush all of the register windows to the stack
on the SPARC, we must flush all of the register windows to the stack
before we can access arbitrary stack frames. You will seldom need to
define this macro.
@ -5094,7 +5094,7 @@ automatically defined by @command{configure}, with value @samp{1}.
@item SELECT_CC_MODE (@var{op}, @var{x}, @var{y})
Returns a mode from class @code{MODE_CC} to be used when comparison
operation code @var{op} is applied to rtx @var{x} and @var{y}. For
example, on the Sparc, @code{SELECT_CC_MODE} is defined as (see
example, on the SPARC, @code{SELECT_CC_MODE} is defined as (see
@pxref{Jump Patterns} for a description of the reason for this
definition)
@ -5138,7 +5138,7 @@ then @code{REVERSIBLE_CC_MODE (@var{mode})} must be zero.
You need not define this macro if it would always returns zero or if the
floating-point format is anything other than @code{IEEE_FLOAT_FORMAT}.
For example, here is the definition used on the Sparc, where floating-point
For example, here is the definition used on the SPARC, where floating-point
inequality comparisons are always given @code{CCFPEmode}:
@smallexample

6
gcc/doc/trouble.texi
View File

@ -163,7 +163,7 @@ Naturally, this does not happen when you use GCC@.
You must specify all three options explicitly.
@item
On a Sparc, GCC aligns all values of type @code{double} on an 8-byte
On a SPARC, GCC aligns all values of type @code{double} on an 8-byte
boundary, and it expects every @code{double} to be so aligned. The Sun
compiler usually gives @code{double} values 8-byte alignment, with one
exception: function arguments of type @code{double} may not be aligned.
@ -202,7 +202,7 @@ Storing into the pointer can be done likewise with the same union.
@item
On Solaris, the @code{malloc} function in the @file{libmalloc.a} library
may allocate memory that is only 4 byte aligned. Since GCC on the
Sparc assumes that doubles are 8 byte aligned, this may result in a
SPARC assumes that doubles are 8 byte aligned, this may result in a
fatal signal if doubles are stored in memory allocated by the
@file{libmalloc.a} library.
@ -219,7 +219,7 @@ when linking, compile and link against the file
@file{mit/util/misc/dlsym.c} from the MIT version of X windows.
@item
The 128-bit long double format that the Sparc port supports currently
The 128-bit long double format that the SPARC port supports currently
works by using the architecturally defined quad-word floating point
instructions. Since there is no hardware that supports these
instructions they must be emulated by the operating system. Long

2
gcc/dwarfout.c
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@ -43,7 +43,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
The generation of DWARF debugging information by the GNU version 2.x C
compiler has now been tested rather extensively for m88k, i386, i860, and
Sparc targets. The DWARF output of the GNU C compiler appears to inter-
SPARC targets. The DWARF output of the GNU C compiler appears to inter-
operate well with the standard SVR4 SDB debugger on these kinds of target
systems (but of course, there are no guarantees).

2
gcc/ginclude/float.h
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@ -57,7 +57,7 @@ Boston, MA 02111-1307, USA. */
#define DBL_DIG __DBL_DIG__
#define LDBL_DIG __LDBL_DIG__
/* Minimum int x such that FLT_RADIX**(x-1) is a normalised float, emin */
/* Minimum int x such that FLT_RADIX**(x-1) is a normalized float, emin */
#undef FLT_MIN_EXP
#undef DBL_MIN_EXP
#undef LDBL_MIN_EXP

2
gcc/reload1.c
View File

@ -3411,7 +3411,7 @@ set_offsets_for_label (insn)
}
/* See if anything that happened changes which eliminations are valid.
For example, on the Sparc, whether or not the frame pointer can
For example, on the SPARC, whether or not the frame pointer can
be eliminated can depend on what registers have been used. We need
not check some conditions again (such as flag_omit_frame_pointer)
since they can't have changed. */

2
gcc/simplify-rtx.c
View File

@ -2582,7 +2582,7 @@ simplify_subreg (outermode, op, innermode, byte)
/* ??? We do allow it if the current REG is not valid for
its mode. This is a kludge to work around how float/complex
arguments are passed on 32-bit Sparc and should be fixed. */
arguments are passed on 32-bit SPARC and should be fixed. */
if (HARD_REGNO_MODE_OK (final_regno, outermode)
|| ! HARD_REGNO_MODE_OK (REGNO (op), innermode))
{

2
gcc/treelang/treelang.texi
View File

@ -451,7 +451,7 @@ later. The list of keywords follows:
@{ - used to start the statements in a function
@} - used to end the statements in a function
( - start list of function arguments, or to change the precedence of operators in an expression
) - end list or prioritised operators in expression
) - end list or prioritized operators in expression
, - used to separate parameters in a function prototype or in a function call
; - used to end a statement
+ - addition

2
gcc/unwind-sjlj.c
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@ -251,7 +251,7 @@ uw_init_context (struct _Unwind_Context *context)
}
/* ??? There appear to be bugs in integrate.c wrt __builtin_longjmp and
virtual-stack-vars. An inline version of this segfaults on Sparc. */
virtual-stack-vars. An inline version of this segfaults on SPARC. */
#define uw_install_context(CURRENT, TARGET) \
do \
{ \