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200x-xx-xx Julian Brown <julian@codesourcery.com> 

gcc/
200x-xx-xx  Julian Brown  <julian@codesourcery.com>

	* config/m68k/m68k.h (TARGET_ISAB): New macro.
	* config/m68k/m68k.c: Use TARGET_ISAB rather than TARGET_CFV4.
	* config/m68k/m68k.md: Likewise.

From-SVN: r120709
This commit is contained in:
Julian Brown 2007-01-12 09:23:35 +00:00 committed by Richard Sandiford
parent bb5bdf700e
commit 986e74d58e
4 changed files with 27 additions and 16 deletions
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6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2007-01-12 Julian Brown <julian@codesourcery.com>
* config/m68k/m68k.h (TARGET_ISAB): New macro.
* config/m68k/m68k.c: Use TARGET_ISAB rather than TARGET_CFV4.
* config/m68k/m68k.md: Likewise.
2007-01-12 Julian Brown <julian@codesourcery.com>
* config/m68k/m68k.h (LEGITIMATE_INDEX_P, LEGITIMIZE_ADDRESS): Use

4
gcc/config/m68k/m68k.c
View File

@ -1562,7 +1562,7 @@ const_method (rtx constant)
if (USE_MOVQ ((u >> 16) | (u << 16)))
return SWAP;
if (TARGET_CFV4)
if (TARGET_ISAB)
{
/* Try using MVZ/MVS with an immediate value to load constants. */
if (i >= 0 && i <= 65535)
@ -1779,7 +1779,7 @@ valid_mov3q_const (rtx constant)
{
int i;
if (TARGET_CFV4 && GET_CODE (constant) == CONST_INT)
if (TARGET_ISAB && GET_CODE (constant) == CONST_INT)
{
i = INTVAL (constant);
if (i == -1 || (i >= 1 && i <= 7))

2
gcc/config/m68k/m68k.h
View File

@ -126,6 +126,8 @@ Boston, MA 02110-1301, USA. */
/* Size (in bytes) of FPU registers. */
#define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12)
#define TARGET_ISAB TARGET_CFV4
#define TUNE_68000_10 (!TARGET_68020 && !TARGET_COLDFIRE)
#define TUNE_68030 TARGET_68030
#define TUNE_68040 TARGET_68040

31
gcc/config/m68k/m68k.md
View File

@ -682,13 +682,13 @@
(define_insn "*movsi_cf"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U")
(match_operand:SI 1 "general_operand" "g,r<Q>,U"))]
"TARGET_COLDFIRE && !TARGET_CFV4"
"TARGET_COLDFIRE && !TARGET_ISAB"
"* return output_move_simode (operands);")
(define_insn "*movsi_cfv4"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U")
(match_operand:SI 1 "general_operand" "Rg,Rr<Q>,U"))]
"TARGET_CFV4"
"TARGET_ISAB"
"* return output_move_simode (operands);")
;; Special case of fullword move, where we need to get a non-GOT PIC
@ -1389,7 +1389,7 @@
(define_insn "*zero_extendhisi2_cf"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
"TARGET_CFV4"
"TARGET_ISAB"
"mvz%.w %1,%0")
(define_insn "zero_extendhisi2"
@ -1413,7 +1413,7 @@
(define_insn "*zero_extendqisi2_cfv4"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
"TARGET_CFV4"
"TARGET_ISAB"
"mvz%.b %1,%0")
(define_insn "zero_extendqisi2"
@ -1427,7 +1427,9 @@
(define_split
[(set (match_operand 0 "register_operand" "")
(zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
"!TARGET_CFV4 && reload_completed && reg_mentioned_p (operands[0], operands[1])"
"!TARGET_ISAB
&& reload_completed
&& reg_mentioned_p (operands[0], operands[1])"
[(set (strict_low_part (match_dup 2))
(match_dup 1))
(set (match_dup 0)
@ -1441,7 +1443,7 @@
(define_split
[(set (match_operand 0 "register_operand" "")
(zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
"!TARGET_CFV4 && reload_completed"
"!TARGET_ISAB && reload_completed"
[(set (match_dup 0)
(const_int 0))
(set (strict_low_part (match_dup 2))
@ -1459,7 +1461,7 @@
{
CC_STATUS_INIT;
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (TARGET_CFV4)
if (TARGET_ISAB)
return "mvs%.b %1,%2\;smi %0\;extb%.l %0";
if (TARGET_68020 || TARGET_COLDFIRE)
{
@ -1485,7 +1487,7 @@
{
CC_STATUS_INIT;
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
if (TARGET_CFV4)
if (TARGET_ISAB)
return "mvs%.w %1,%2\;smi %0\;extb%.l %0";
if (TARGET_68020 || TARGET_COLDFIRE)
return "move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0";
@ -1549,14 +1551,14 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extend:SI
(match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
"TARGET_CFV4"
"TARGET_ISAB"
"mvs%.w %1,%0")
(define_insn "*68k_extendhisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
(sign_extend:SI
(match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
"!TARGET_CFV4"
"!TARGET_ISAB"
{
if (ADDRESS_REG_P (operands[0]))
return "move%.w %1,%0";
@ -1578,13 +1580,13 @@
(define_insn "*cfv4_extendqisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))]
"TARGET_CFV4"
"TARGET_ISAB"
"mvs%.b %1,%0")
(define_insn "*68k_extendqisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
"TARGET_68020 || (TARGET_COLDFIRE && !TARGET_CFV4)"
"TARGET_68020 || (TARGET_COLDFIRE && !TARGET_ISAB)"
"extb%.l %0")
;; Conversions between float and double.
@ -3094,7 +3096,7 @@
(umod:HI (match_dup 1) (match_dup 2)))]
"!TARGET_COLDFIRE || TARGET_CF_HWDIV"
{
if (TARGET_CFV4)
if (TARGET_ISAB)
output_asm_insn (MOTOROLA ?
"mvz%.w %0,%0\;divu%.w %2,%0" :
"mvz%.w %0,%0\;divu %2,%0",
@ -3218,7 +3220,8 @@
(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
"TARGET_COLDFIRE"
{
if (TARGET_CFV4 && DATA_REG_P (operands[0])
if (TARGET_ISAB
&& DATA_REG_P (operands[0])
&& GET_CODE (operands[2]) == CONST_INT)
{
if (INTVAL (operands[2]) == 0x000000ff)