elf.h: Fix comment formatting.
* config/elf.h: Fix comment formatting. * config/elf64.h: Likewise. * config/iris5.h: Likewise. * config/iris5gas.h: Likewise. * config/iris6.h: Likewise. * config/isa3264.h: Likewise. * config/linux.h: Likewise. * config/mips.c: Likewise. * config/mips.h: Likewise. * config/mips.md: Likewise. * config/mips16.S: Likewise. * config/netbsd.h: Likewise. * config/osfrose.h: Likewise. * config/r3900.h: Likewise. * config/sni-svr4.h: Likewise. * config/svr4-t.h: Likewise. * config/ultrix.h: Likewise. From-SVN: r46670
This commit is contained in:
Kazu Hirata
Kazu Hirata
parent
87a2e7a8a5
commit
987ba558b0
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@ -1,3 +1,23 @@
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2001-10-30 Kazu Hirata <kazu@hxi.com>
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* config/elf.h: Fix comment formatting.
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* config/elf64.h: Likewise.
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* config/iris5.h: Likewise.
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* config/iris5gas.h: Likewise.
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* config/iris6.h: Likewise.
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* config/isa3264.h: Likewise.
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* config/linux.h: Likewise.
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* config/mips.c: Likewise.
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* config/mips.h: Likewise.
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* config/mips.md: Likewise.
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* config/mips16.S: Likewise.
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* config/netbsd.h: Likewise.
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* config/osfrose.h: Likewise.
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* config/r3900.h: Likewise.
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* config/sni-svr4.h: Likewise.
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* config/svr4-t.h: Likewise.
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* config/ultrix.h: Likewise.
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2001-10-30 Daniel Berlin <dan@cgsoftware.com>
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* bitmap.c (bitmap_element_free): Don't forget to update head->indx
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@ -114,7 +114,7 @@ do { \
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specified as the number of bits.
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Try to use function `asm_output_aligned_bss' defined in file
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`varasm.c' when defining this macro. */
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`varasm.c' when defining this macro. */
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#ifndef ASM_OUTPUT_ALIGNED_BSS
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#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
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do { \
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@ -194,7 +194,7 @@ do { \
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mips-elf gas supports .weak, but not .weakext.
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mips-elf gas has been changed to support both .weak and .weakext,
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but until that support is generally available, the 'if' below
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should serve. */
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should serve. */
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#undef ASM_WEAKEN_LABEL
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#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0)
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@ -173,7 +173,7 @@ do { \
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mips-elf gas supports .weak, but not .weakext.
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mips-elf gas has been changed to support both .weak and .weakext,
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but until that support is generally available, the 'if' below
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should serve. */
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should serve. */
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#undef ASM_WEAKEN_LABEL
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#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0)
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@ -114,7 +114,7 @@ Boston, MA 02111-1307, USA. */
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/* We do not want to run mips-tfile! */
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#undef ASM_FINAL_SPEC
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/* The system header files are C++ aware. */
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/* The system header files are C++ aware. */
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/* ??? Unfortunately, most but not all of the headers are C++ aware.
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Specifically, curses.h is not, and as a consequence, defining this
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used to prevent libg++ building. This is no longer the case so
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@ -123,7 +123,7 @@ Boston, MA 02111-1307, USA. */
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fixing. */
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#define NO_IMPLICIT_EXTERN_C 1
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/* We don't support debugging info for now. */
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/* We don't support debugging info for now. */
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#undef DBX_DEBUGGING_INFO
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#undef SDB_DEBUGGING_INFO
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#undef MIPS_DEBUGGING_INFO
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@ -1,4 +1,4 @@
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/* Definitions of target machine for GNU compiler. Irix version 5 with gas. */
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/* Definitions of target machine for GNU compiler. Irix version 5 with gas. */
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/* Enable debugging. */
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#define DBX_DEBUGGING_INFO
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@ -131,7 +131,7 @@ Boston, MA 02111-1307, USA. */
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#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
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/* Force the generation of dwarf .debug_frame sections even if not
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compiling -g. This guarantees that we can unwind the stack. */
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compiling -g. This guarantees that we can unwind the stack. */
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#define DWARF2_FRAME_INFO 1
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/* The size in bytes of a DWARF field indicating an offset or length
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@ -228,7 +228,7 @@ Boston, MA 02111-1307, USA. */
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#define SUBTARGET_ASM_SPEC "%{!mabi*:-n32} %{!mips*: %{!mabi*:-mips3} %{mabi=n32:-mips3} %{mabi=64:-mips4}}"
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/* Must pass -g0 to the assembler, otherwise it may overwrite our
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debug info with its own debug info. */
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debug info with its own debug info. */
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/* Must pass -show instead of -v. */
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/* Must pass -G 0 to the assembler, otherwise we may get warnings about
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GOT overflow. */
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@ -38,7 +38,7 @@ Boston, MA 02111-1307, USA. */
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#include "mips/elf.h"
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/* This must be done after including mips.h so that the
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ABI_{EABI,O64,O32,...} are #defined. */
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ABI_{EABI,O64,O32,...} are #defined. */
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#if MIPS_ABI_DEFAULT == ABI_EABI
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#undef SUBTARGET_CPP_SIZE_SPEC
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@ -110,7 +110,7 @@ Boston, MA 02111-1307, USA. */
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For MEABI the size of longs is always 32bits. If long64 is specified then
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we honor that. The errors for long64 & long32 is because while CC1 can
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handle overriding mlong32 with mlong64 and vise-versa, the specs cannot. */
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handle overriding mlong32 with mlong64 and vise-versa, the specs cannot. */
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#if MIPS_ISA_DEFAULT == 3 || MIPS_ISA_DEFAULT == 4 || MIPS_ISA_DEFAULT == 5 || MIPS_ISA_DEFAULT == 64
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#undef SUBTARGET_CPP_SIZE_SPEC
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@ -47,7 +47,7 @@ Boston, MA 02111-1307, USA. */
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specified as the number of bits.
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Try to use function `asm_output_aligned_bss' defined in file
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`varasm.c' when defining this macro. */
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`varasm.c' when defining this macro. */
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#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
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do { \
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ASM_GLOBALIZE_LABEL (FILE, NAME); \
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@ -149,7 +149,7 @@ void FN () \
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/* Required to keep collect2.c happy */
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#undef OBJECT_FORMAT_COFF
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/* If we don't set MASK_ABICALLS, we can't default to PIC. */
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/* If we don't set MASK_ABICALLS, we can't default to PIC. */
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#undef TARGET_DEFAULT
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#define TARGET_DEFAULT (MASK_ABICALLS|MASK_GAS)
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@ -64,7 +64,7 @@ extern tree lookup_name PARAMS ((tree));
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/* Enumeration for all of the relational tests, so that we can build
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arrays indexed by the test type, and not worry about the order
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of EQ, NE, etc. */
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of EQ, NE, etc. */
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enum internal_test {
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ITEST_EQ,
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@ -145,7 +145,7 @@ int num_source_filenames = 0;
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start and end boundaries). */
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int sdb_label_count = 0;
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/* Next label # for each statement for Silicon Graphics IRIS systems. */
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/* Next label # for each statement for Silicon Graphics IRIS systems. */
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int sym_lineno = 0;
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/* Non-zero if inside of a function, because the stupid MIPS asm can't
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@ -248,7 +248,7 @@ const char *mips_no_mips16_string;
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/* This is only used to determine if an type size setting option was
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explicitly specified (-mlong64, -mint64, -mlong32). The specs
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set this option if such an option is used. */
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set this option if such an option is used. */
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const char *mips_explicit_type_size_string;
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/* Whether we are generating mips16 hard float code. In mips16 mode
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@ -582,7 +582,7 @@ reg_or_0_operand (op, mode)
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}
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/* Return truth value of whether OP is a register or the constant 0,
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even in mips16 mode. */
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even in mips16 mode. */
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int
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true_reg_or_0_operand (op, mode)
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@ -797,7 +797,7 @@ simple_memory_operand (op, mode)
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if (GET_CODE (op) != SYMBOL_REF)
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return 0;
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/* let's be paranoid.... */
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/* let's be paranoid.... */
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if (! SMALL_INT (offset))
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return 0;
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}
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@ -902,7 +902,7 @@ double_memory_operand (op, mode)
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return 1;
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/* Similarly, we accept a case where the memory address is
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itself on the stack, and will be reloaded. */
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itself on the stack, and will be reloaded. */
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if (GET_CODE (addr) == MEM)
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{
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rtx maddr;
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@ -1294,7 +1294,7 @@ mips_legitimate_address_p (mode, xinsn, strict)
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}
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/* Check for constant before stripping off SUBREG, so that we don't
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accept (subreg (const_int)) which will fail to reload. */
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accept (subreg (const_int)) which will fail to reload. */
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if (CONSTANT_ADDRESS_P (xinsn)
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&& ! (mips_split_addresses && mips_check_split (xinsn, mode))
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&& (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
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@ -2729,7 +2729,7 @@ mips_address_cost (addr)
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return 2;
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}
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/* ... fall through ... */
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/* ... fall through ... */
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case SYMBOL_REF:
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return SYMBOL_REF_FLAG (addr) ? 1 : 2;
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@ -3482,7 +3482,7 @@ expand_block_move (operands)
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The block move type can be one of the following:
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BLOCK_MOVE_NORMAL Do all of the block move.
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BLOCK_MOVE_NOT_LAST Do all but the last store.
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BLOCK_MOVE_LAST Do just the last store. */
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BLOCK_MOVE_LAST Do just the last store. */
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const char *
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output_block_move (insn, operands, num_regs, move_type)
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@ -3859,7 +3859,7 @@ init_cumulative_args (cum, fntype, libname)
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/* Determine if this function has variable arguments. This is
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indicated by the last argument being 'void_type_mode' if there
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are no variable arguments. The standard MIPS calling sequence
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passes all arguments in the general purpose registers in this case. */
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passes all arguments in the general purpose registers in this case. */
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for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
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param != 0; param = next_param)
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@ -4288,7 +4288,7 @@ function_arg_partial_nregs (cum, mode, type, named)
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Note that the GPR save area is not constant size, due to optimization
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in the prologue. Hence, we can't use a design with two pointers
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and two offsets, although we could have designed this with two pointers
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and three offsets. */
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and three offsets. */
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tree
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@ -4351,7 +4351,7 @@ mips_va_start (stdarg_p, valist, nextarg)
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if (mips_abi == ABI_EABI)
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{
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int gpr_save_area_size;
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/* Note UNITS_PER_WORD is 4 bytes or 8, depending on TARGET_64BIT. */
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/* Note UNITS_PER_WORD is 4 bytes or 8, depending on TARGET_64BIT. */
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if (int_arg_words < 8 )
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/* Adjust for the prologue's economy measure */
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gpr_save_area_size = (8 - int_arg_words) * UNITS_PER_WORD;
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@ -4387,7 +4387,7 @@ mips_va_start (stdarg_p, valist, nextarg)
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/* Emit code setting a pointer into the overflow (shared-stack) area.
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If there were more than 8 non-float formals, or more than 8
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float formals, then this pointer isn't to the base of the area.
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In that case, it must point to where the first vararg is. */
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In that case, it must point to where the first vararg is. */
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size_excess = 0;
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if (float_formals > floats_passed_in_regs)
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size_excess += (float_formals-floats_passed_in_regs) * 8;
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@ -4401,7 +4401,7 @@ mips_va_start (stdarg_p, valist, nextarg)
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take into account the exact sequence of floats and non-floats
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which make up the excess. That calculation should be rolled
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into the code which sets the current_function_args_info struct.
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The above then reduces to a fetch from that struct. */
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The above then reduces to a fetch from that struct. */
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t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
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@ -4411,7 +4411,7 @@ mips_va_start (stdarg_p, valist, nextarg)
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t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
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expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
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/* Emit code setting a ptr to the base of the overflow area. */
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/* Emit code setting a ptr to the base of the overflow area. */
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t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
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t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
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expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
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@ -4421,7 +4421,7 @@ mips_va_start (stdarg_p, valist, nextarg)
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If mips4, this is gpr_save_area_size below the overflow area.
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If mips2, also round down to an 8-byte boundary, since the FPR
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save area is 8-byte aligned, and GPR is 4-byte-aligned.
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Therefore there can be a 4-byte gap between the save areas. */
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Therefore there can be a 4-byte gap between the save areas. */
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gprv = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
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fpr_save_offset = gpr_save_area_size;
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if (!TARGET_64BIT)
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@ -4463,7 +4463,7 @@ mips_va_start (stdarg_p, valist, nextarg)
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/* TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT */
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/* Everything is in the GPR save area, or in the overflow
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area which is contiguous with it. */
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area which is contiguous with it. */
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int offset = -gpr_save_area_size;
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if (gpr_save_area_size == 0)
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@ -4530,7 +4530,7 @@ mips_va_arg (valist, type)
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if (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT)
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{
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/* Case of all args in a merged stack. No need to check bounds,
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just advance valist along the stack. */
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just advance valist along the stack. */
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tree gpr = valist;
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if (! indirect
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@ -4568,7 +4568,7 @@ mips_va_arg (valist, type)
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return addr_rtx;
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}
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/* Not a simple merged stack. Need ptrs and indexes left by va_start. */
|
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/* Not a simple merged stack. Need ptrs and indexes left by va_start. */
|
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f_ovfl = TYPE_FIELDS (va_list_type_node);
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f_gtop = TREE_CHAIN (f_ovfl);
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|
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@ -4588,7 +4588,7 @@ mips_va_arg (valist, type)
|
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if (TREE_CODE (type) == REAL_TYPE)
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{
|
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/* Emit code to branch if foff == 0. */
|
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/* Emit code to branch if foff == 0. */
|
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r = expand_expr (foff, NULL_RTX, TYPE_MODE (TREE_TYPE (foff)),
|
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EXPAND_NORMAL);
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emit_cmp_and_jump_insns (r, const0_rtx, EQ,
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|
|
@ -4616,7 +4616,7 @@ mips_va_arg (valist, type)
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/* For mips2, the overflow area contains mixed size items.
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If a 4-byte int is followed by an 8-byte float, then
|
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natural alignment causes a 4 byte gap.
|
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So, dynamically adjust ovfl up to a multiple of 8. */
|
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So, dynamically adjust ovfl up to a multiple of 8. */
|
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t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), ovfl,
|
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build_int_2 (7, 0));
|
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t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, t);
|
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|
|
@ -4625,7 +4625,7 @@ mips_va_arg (valist, type)
|
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}
|
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|
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/* Emit code for addr_rtx = the ovfl pointer into overflow area.
|
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Regardless of mips2, postincrement the ovfl pointer by 8. */
|
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Regardless of mips2, postincrement the ovfl pointer by 8. */
|
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t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
|
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size_int (8));
|
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r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
|
||||
|
|
@ -4648,33 +4648,33 @@ mips_va_arg (valist, type)
|
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/* In mips2, int takes 32 bits of the GPR save area, but
|
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longlong takes an aligned 64 bits. So, emit code
|
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to zero the low order bits of goff, thus aligning
|
||||
the later calculation of (gtop-goff) upwards. */
|
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the later calculation of (gtop-goff) upwards. */
|
||||
t = build (BIT_AND_EXPR, TREE_TYPE (goff), goff,
|
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build_int_2 (-8, -1));
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t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
|
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expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
|
||||
}
|
||||
|
||||
/* Emit code to branch if goff == 0. */
|
||||
/* Emit code to branch if goff == 0. */
|
||||
r = expand_expr (goff, NULL_RTX, TYPE_MODE (TREE_TYPE (goff)),
|
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EXPAND_NORMAL);
|
||||
emit_cmp_and_jump_insns (r, const0_rtx, EQ,
|
||||
const1_rtx, GET_MODE (r), 1, 1, lab_false);
|
||||
|
||||
/* Emit code for addr_rtx = gtop - goff. */
|
||||
/* Emit code for addr_rtx = gtop - goff. */
|
||||
t = build (MINUS_EXPR, TREE_TYPE (gtop), gtop, goff);
|
||||
r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
|
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if (r != addr_rtx)
|
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emit_move_insn (addr_rtx, r);
|
||||
|
||||
/* Note that mips2 int is 32 bit, but mips2 longlong is 64. */
|
||||
/* Note that mips2 int is 32 bit, but mips2 longlong is 64. */
|
||||
if (! TARGET_64BIT && TYPE_PRECISION (type) == 64)
|
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step_size = 8;
|
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else
|
||||
step_size = UNITS_PER_WORD;
|
||||
|
||||
/* Emit code for goff = goff - step_size.
|
||||
Advances the offset up GPR save area over the item. */
|
||||
Advances the offset up GPR save area over the item. */
|
||||
t = build (MINUS_EXPR, TREE_TYPE (goff), goff,
|
||||
build_int_2 (step_size, 0));
|
||||
t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
|
||||
|
|
@ -4711,7 +4711,7 @@ mips_va_arg (valist, type)
|
|||
}
|
||||
else
|
||||
{
|
||||
/* Not EABI. */
|
||||
/* Not EABI. */
|
||||
int align;
|
||||
|
||||
/* ??? The original va-mips.h did always align, despite the fact
|
||||
|
|
@ -4769,7 +4769,7 @@ override_options ()
|
|||
/* If both single-float and soft-float are set, then clear the one that
|
||||
was set by TARGET_DEFAULT, leaving the one that was set by the
|
||||
user. We assume here that the specs prevent both being set by the
|
||||
user. */
|
||||
user. */
|
||||
#ifdef TARGET_DEFAULT
|
||||
if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
|
||||
target_flags &= ~((TARGET_DEFAULT) & (MASK_SOFT_FLOAT | MASK_SINGLE_FLOAT));
|
||||
|
|
@ -4815,7 +4815,7 @@ override_options ()
|
|||
}
|
||||
|
||||
#ifdef MIPS_ABI_DEFAULT
|
||||
/* Get the ABI to use. */
|
||||
/* Get the ABI to use. */
|
||||
if (mips_abi_string == (char *) 0)
|
||||
mips_abi = MIPS_ABI_DEFAULT;
|
||||
else if (! strcmp (mips_abi_string, "32"))
|
||||
|
|
@ -7017,7 +7017,7 @@ mips_output_function_prologue (file, size)
|
|||
|
||||
/* Require:
|
||||
OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
|
||||
HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
|
||||
HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
|
||||
}
|
||||
|
||||
if (mips_entry && ! mips_can_use_return_insn ())
|
||||
|
|
@ -7194,7 +7194,7 @@ mips_expand_prologue ()
|
|||
the varargs special argument, and treat it as part of the
|
||||
variable arguments.
|
||||
|
||||
This is only needed if store_args_on_stack is true. */
|
||||
This is only needed if store_args_on_stack is true. */
|
||||
|
||||
INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
|
||||
regno = GP_ARG_FIRST;
|
||||
|
|
@ -7297,7 +7297,7 @@ mips_expand_prologue ()
|
|||
int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
|
||||
rtx ptr = stack_pointer_rtx;
|
||||
|
||||
/* If we are doing svr4-abi, sp has already been decremented by tsize. */
|
||||
/* If we are doing svr4-abi, sp has already been decremented by tsize. */
|
||||
if (TARGET_ABICALLS)
|
||||
offset += tsize;
|
||||
|
||||
|
|
@ -7515,7 +7515,7 @@ mips_expand_prologue ()
|
|||
}
|
||||
|
||||
/* Do any necessary cleanup after a function to restore stack, frame,
|
||||
and regs. */
|
||||
and regs. */
|
||||
|
||||
#define RA_MASK BITMASK_HIGH /* 1 << 31 */
|
||||
#define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
|
||||
|
|
@ -8055,7 +8055,7 @@ function_arg_pass_by_reference (cum, mode, type, named)
|
|||
{
|
||||
/* Don't pass the actual CUM to FUNCTION_ARG, because we would
|
||||
get double copies of any offsets generated for small structs
|
||||
passed in registers. */
|
||||
passed in registers. */
|
||||
CUMULATIVE_ARGS temp;
|
||||
temp = *cum;
|
||||
if (FUNCTION_ARG (temp, mode, type, named) != 0)
|
||||
|
|
@ -8808,7 +8808,7 @@ build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
|
|||
|
||||
/* We build the stub code by hand. That's the only way we can
|
||||
do it, since we can't generate 32 bit code during a 16 bit
|
||||
compilation. */
|
||||
compilation. */
|
||||
|
||||
/* We don't want the assembler to insert any nops here. */
|
||||
fprintf (asm_out_file, "\t.set\tnoreorder\n");
|
||||
|
|
@ -9476,7 +9476,7 @@ machine_dependent_reorg (first)
|
|||
{
|
||||
/* If we haven't had a barrier within 0x8000 bytes of a
|
||||
constant reference or we are at the end of the function,
|
||||
emit a barrier now. */
|
||||
emit a barrier now. */
|
||||
|
||||
rtx label, jump, barrier;
|
||||
|
||||
|
|
@ -9621,7 +9621,7 @@ mips_output_conditional_branch (insn,
|
|||
break;
|
||||
|
||||
case LTU:
|
||||
/* A condition which will always be false. */
|
||||
/* A condition which will always be false. */
|
||||
code = NE;
|
||||
op1 = "%.";
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@ enum processor_type {
|
|||
value at preprocessing time.
|
||||
|
||||
ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
|
||||
defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
|
||||
defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
|
||||
|
||||
#define ABI_32 0
|
||||
#define ABI_N32 1
|
||||
|
|
@ -96,7 +96,7 @@ enum processor_type {
|
|||
Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
|
||||
EABI the legacy EABI. In the end we may end up calling both ABI's
|
||||
EABI but give them different version numbers, but for now I'm going
|
||||
with different names. */
|
||||
with different names. */
|
||||
#define ABI_MEABI 5
|
||||
|
||||
|
||||
|
|
@ -127,7 +127,7 @@ enum block_move_type {
|
|||
BLOCK_MOVE_LAST /* generate just the last store */
|
||||
};
|
||||
|
||||
extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
|
||||
extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
|
||||
extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
|
||||
extern const char *current_function_file; /* filename current function is in */
|
||||
extern int num_source_filenames; /* current .file # */
|
||||
|
|
@ -245,7 +245,7 @@ extern void sbss_section PARAMS ((void));
|
|||
#define MASK_DEBUG 0 /* unused */
|
||||
#define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
|
||||
#define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
|
||||
#define MASK_DEBUG_C 0 /* don't expand seq, etc. */
|
||||
#define MASK_DEBUG_C 0 /* don't expand seq, etc. */
|
||||
#define MASK_DEBUG_D 0 /* don't do define_split's */
|
||||
#define MASK_DEBUG_E 0 /* function_arg debug */
|
||||
#define MASK_DEBUG_F 0 /* ??? */
|
||||
|
|
@ -317,7 +317,7 @@ extern void sbss_section PARAMS ((void));
|
|||
|
||||
/* always store uninitialized const
|
||||
variables in rodata, requires
|
||||
TARGET_EMBEDDED_DATA. */
|
||||
TARGET_EMBEDDED_DATA. */
|
||||
#define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
|
||||
|
||||
/* generate big endian code. */
|
||||
|
|
@ -648,18 +648,18 @@ extern void sbss_section PARAMS ((void));
|
|||
#define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
|
||||
#define HAVE_SQRT_P() (mips_isa != 1)
|
||||
|
||||
/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
|
||||
/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
|
||||
#define ISA_HAS_64BIT_REGS (mips_isa == 3 \
|
||||
|| mips_isa == 4 \
|
||||
|| mips_isa == 64)
|
||||
|
||||
/* ISA has branch likely instructions (eg. mips2). */
|
||||
/* ISA has branch likely instructions (eg. mips2). */
|
||||
/* Disable branchlikely for tx39 until compare rewrite. They haven't
|
||||
been generated up to this point. */
|
||||
#define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
|
||||
/* || TARGET_MIPS3900 */)
|
||||
|
||||
/* ISA has the conditional move instructions introduced in mips4. */
|
||||
/* ISA has the conditional move instructions introduced in mips4. */
|
||||
#define ISA_HAS_CONDMOVE (mips_isa == 4 \
|
||||
|| mips_isa == 32 \
|
||||
|| mips_isa == 64)
|
||||
|
|
@ -670,7 +670,7 @@ extern void sbss_section PARAMS ((void));
|
|||
|
||||
|
||||
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
|
||||
branch on CC, and move (both FP and non-FP) on CC. */
|
||||
branch on CC, and move (both FP and non-FP) on CC. */
|
||||
#define ISA_HAS_8CC (mips_isa == 4 \
|
||||
|| mips_isa == 32 \
|
||||
|| mips_isa == 64)
|
||||
|
|
@ -1005,7 +1005,7 @@ while (0)
|
|||
|
||||
/* Redefinition of libraries used. Mips doesn't support normal
|
||||
UNIX style profiling via calling _mcount. It does offer
|
||||
profiling that samples the PC, so do what we can... */
|
||||
profiling that samples the PC, so do what we can... */
|
||||
|
||||
#ifndef LIB_SPEC
|
||||
#define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
|
||||
|
|
@ -1220,14 +1220,14 @@ while (0)
|
|||
|
||||
/* Local compiler-generated symbols must have a prefix that the assembler
|
||||
understands. By default, this is $, although some targets (e.g.,
|
||||
NetBSD-ELF) need to override this. */
|
||||
NetBSD-ELF) need to override this. */
|
||||
|
||||
#ifndef LOCAL_LABEL_PREFIX
|
||||
#define LOCAL_LABEL_PREFIX "$"
|
||||
#endif
|
||||
|
||||
/* By default on the mips, external symbols do not have an underscore
|
||||
prepended, but some targets (e.g., NetBSD) require this. */
|
||||
prepended, but some targets (e.g., NetBSD) require this. */
|
||||
|
||||
#ifndef USER_LABEL_PREFIX
|
||||
#define USER_LABEL_PREFIX ""
|
||||
|
|
@ -1244,7 +1244,7 @@ while (0)
|
|||
#undef DBX_CONTIN_LENGTH
|
||||
#define DBX_CONTIN_LENGTH 1500
|
||||
|
||||
/* How to renumber registers for dbx and gdb. */
|
||||
/* How to renumber registers for dbx and gdb. */
|
||||
#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
|
||||
|
||||
/* The mapping from gcc register number to DWARF 2 CFA column number.
|
||||
|
|
@ -1443,10 +1443,10 @@ do { \
|
|||
*/
|
||||
#define BITS_BIG_ENDIAN 0
|
||||
|
||||
/* Define this if most significant byte of a word is the lowest numbered. */
|
||||
/* Define this if most significant byte of a word is the lowest numbered. */
|
||||
#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
|
||||
|
||||
/* Define this if most significant word of a multiword number is the lowest. */
|
||||
/* Define this if most significant word of a multiword number is the lowest. */
|
||||
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
|
||||
|
||||
/* Define this to set the endianness to use in libgcc2.c, which can
|
||||
|
|
@ -1621,7 +1621,7 @@ do { \
|
|||
/* Define this macro if an argument declared as `char' or `short' in a
|
||||
prototype should actually be passed as an `int'. In addition to
|
||||
avoiding errors in certain cases of mismatch, it also makes for
|
||||
better code on certain machines. */
|
||||
better code on certain machines. */
|
||||
|
||||
#define PROMOTE_PROTOTYPES 1
|
||||
|
||||
|
|
@ -2015,7 +2015,7 @@ extern const enum reg_class mips_regno_to_class[];
|
|||
/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
|
||||
registers explicitly used in the rtl to be used as spill registers
|
||||
but prevents the compiler from extending the lifetime of these
|
||||
registers. */
|
||||
registers. */
|
||||
|
||||
#define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
|
||||
|
||||
|
|
@ -2678,7 +2678,7 @@ typedef struct mips_args {
|
|||
|
||||
/* For an arg passed partly in registers and partly in memory,
|
||||
this is the number of registers used.
|
||||
For args passed entirely in registers or entirely in memory, zero. */
|
||||
For args passed entirely in registers or entirely in memory, zero. */
|
||||
|
||||
#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
|
||||
function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
|
||||
|
|
@ -3319,7 +3319,7 @@ while (0)
|
|||
/* Define as C expression which evaluates to nonzero if the tablejump
|
||||
instruction expects the table to contain offsets from the address of the
|
||||
table.
|
||||
Do not define this if the table should contain absolute addresses. */
|
||||
Do not define this if the table should contain absolute addresses. */
|
||||
#define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
|
||||
|
||||
/* Specify the tree operation to be used to convert reals to integers. */
|
||||
|
|
@ -3357,7 +3357,7 @@ while (0)
|
|||
#define SLOW_ZERO_EXTEND
|
||||
|
||||
/* Define this to be nonzero if shift instructions ignore all but the low-order
|
||||
few bits. */
|
||||
few bits. */
|
||||
#define SHIFT_COUNT_TRUNCATED 1
|
||||
|
||||
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
|
||||
|
|
@ -3375,7 +3375,7 @@ while (0)
|
|||
After generation of rtl, the compiler makes no further distinction
|
||||
between pointers and any other objects of this machine mode.
|
||||
|
||||
For MIPS we make pointers are the smaller of longs and gp-registers. */
|
||||
For MIPS we make pointers are the smaller of longs and gp-registers. */
|
||||
|
||||
#ifndef Pmode
|
||||
#define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
|
||||
|
|
@ -3494,7 +3494,7 @@ while (0)
|
|||
if (GET_CODE (symref) != SYMBOL_REF) \
|
||||
return COSTS_N_INSNS (4); \
|
||||
\
|
||||
/* let's be paranoid.... */ \
|
||||
/* let's be paranoid.... */ \
|
||||
if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
|
||||
return COSTS_N_INSNS (2); \
|
||||
\
|
||||
|
|
@ -3733,7 +3733,7 @@ while (0)
|
|||
different numbers of registers on machines with lots of registers.
|
||||
|
||||
This macro will normally either not be defined or be defined as
|
||||
a constant. */
|
||||
a constant. */
|
||||
|
||||
#define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
|
||||
|
||||
|
|
@ -3766,7 +3766,7 @@ while (0)
|
|||
all values except -1. We could handle that case by using a signed
|
||||
divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
|
||||
compare/branch to test the input value to see which instruction we
|
||||
need to use. This gets pretty messy, but it is feasible. */
|
||||
need to use. This gets pretty messy, but it is feasible. */
|
||||
|
||||
#define REGISTER_MOVE_COST(MODE, FROM, TO) \
|
||||
((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
|
||||
|
|
@ -4233,7 +4233,7 @@ while (0)
|
|||
$Lb[0-9]+ Begin blocks for MIPS debug support
|
||||
$Lc[0-9]+ Label for use in s<xx> operation.
|
||||
$Le[0-9]+ End blocks for MIPS debug support
|
||||
$Lp\..+ Half-pic labels. */
|
||||
$Lp\..+ Half-pic labels. */
|
||||
|
||||
/* This is how to output the definition of a user-level label named NAME,
|
||||
such as the label on a static function or variable NAME.
|
||||
|
|
@ -4543,7 +4543,7 @@ do { \
|
|||
address with faster (gp) register relative addressing, which can
|
||||
only get at sdata and sbss items (there is no stext !!) However,
|
||||
if the constant is too large for sdata, and it's readonly, it
|
||||
will go into the .rdata section. */
|
||||
will go into the .rdata section. */
|
||||
|
||||
#undef EXTRA_SECTION_FUNCTIONS
|
||||
#define EXTRA_SECTION_FUNCTIONS \
|
||||
|
|
@ -4632,7 +4632,7 @@ while (0)
|
|||
and mips-tdump.c to print them out.
|
||||
|
||||
These must match the corresponding definitions in gdb/mipsread.c.
|
||||
Unfortunately, gcc and gdb do not currently share any directories. */
|
||||
Unfortunately, gcc and gdb do not currently share any directories. */
|
||||
|
||||
#define CODE_MASK 0x8F300
|
||||
#define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
|
||||
|
|
|
|||
|
|
@ -2617,7 +2617,7 @@
|
|||
have_dep_anti = 1;
|
||||
if (! have_dep_anti)
|
||||
{
|
||||
/* No branch delay slots on mips16. */
|
||||
/* No branch delay slots on mips16. */
|
||||
if (which_alternative == 1)
|
||||
return \"%(bnez\\t%0,1f\\n\\tbreak\\t%2\\n%~1:%)\";
|
||||
else
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ Boston, MA 02111-1307, USA. */
|
|||
/* This file contains 32 bit assembly code. */
|
||||
.set nomips16
|
||||
|
||||
/* Start a function. */
|
||||
/* Start a function. */
|
||||
|
||||
#define STARTFN(NAME) .globl NAME; .ent NAME; NAME:
|
||||
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ Boston, MA 02111-1307, USA. */
|
|||
|
||||
#define TARGET_MEM_FUNCTIONS
|
||||
|
||||
/* Define mips-specific netbsd predefines... */
|
||||
/* Define mips-specific netbsd predefines... */
|
||||
#ifndef CPP_PREDEFINES
|
||||
#define CPP_PREDEFINES "-D__ANSI_COMPAT \
|
||||
-DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD -D__NetBSD__ -Dmips \
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ Boston, MA 02111-1307, USA. */
|
|||
|
||||
/* Define this macro meaning that `gcc' should find the library
|
||||
`libgcc.a' by hand, rather than passing the argument `-lgcc' to
|
||||
tell the linker to do the search. */
|
||||
tell the linker to do the search. */
|
||||
|
||||
#define LINK_LIBGCC_SPECIAL 1
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ Boston, MA 02111-1307, USA. */
|
|||
%e-msingle-float and -msoft-float can not both be specified.}}"
|
||||
|
||||
/* The following is needed because -mips3 and -mips4 set gp64 which in
|
||||
combination with abi=eabi, causes long64 to be set. */
|
||||
combination with abi=eabi, causes long64 to be set. */
|
||||
#define SUBTARGET_CPP_SIZE_SPEC "\
|
||||
%{mips3:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
|
||||
%{mips4:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
|
||||
|
|
@ -58,7 +58,7 @@ Boston, MA 02111-1307, USA. */
|
|||
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
|
||||
|
||||
/* For the 'preferred' cases ("gN" and "ggdbN") we need to tell the
|
||||
gnu assembler not to generate debugging information. */
|
||||
gnu assembler not to generate debugging information. */
|
||||
|
||||
#define SUBTARGET_ASM_DEBUGGING_SPEC "\
|
||||
%{!mmips-as: \
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@ Boston, MA 02111-1307, USA. */
|
|||
|
||||
#undef OBJECT_FORMAT_COFF
|
||||
|
||||
/* We don't support debugging info for now. */
|
||||
/* We don't support debugging info for now. */
|
||||
#undef DBX_DEBUGGING_INFO
|
||||
#undef SDB_DEBUGGING_INFO
|
||||
#undef MIPS_DEBUGGING_INFO
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* Definitions of target machine for GNU compiler. Tandem S2 w/ NonStop UX. */
|
||||
/* Definitions of target machine for GNU compiler. Tandem S2 w/ NonStop UX. */
|
||||
|
||||
/* Use the default value for this. */
|
||||
#undef STANDARD_INCLUDE_DIR
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ Boston, MA 02111-1307, USA. */
|
|||
#define TARGET_MEM_FUNCTIONS
|
||||
|
||||
/* Work around assembler forward label references generated in exception
|
||||
handling code. */
|
||||
handling code. */
|
||||
#define DWARF2_UNWIND_INFO 0
|
||||
|
||||
/* INITIALIZE_TRAMPOLINE calls this library function to flush
|
||||
|
|
|
|||
Loading…
Reference in New Issue