[AArch64_be] Fix vec_select hi/lo mask confusions.
gcc/ * config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Vary the generated mask based on BYTES_BIG_ENDIAN. (aarch64_simd_check_vect_par_cnst_half): New. * config/aarch64/aarch64-protos.h (aarch64_simd_check_vect_par_cnst_half): New. * config/aarch64/predicates.md (vect_par_cnst_hi_half): Refactor the check out to aarch64_simd_check_vect_par_cnst_half. (vect_par_cnst_lo_half): Likewise. * config/aarch64/aarch64-simd.md (aarch64_simd_move_hi_quad_<mode>): Always use vec_par_cnst_lo_half. (move_hi_quad_<mode>): Always generate a low mask. From-SVN: r213378
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James Greenhalgh
James Greenhalgh
parent
08938c896f
commit
988fa69392
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@ -1,3 +1,17 @@
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2014-07-31 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Vary
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the generated mask based on BYTES_BIG_ENDIAN.
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(aarch64_simd_check_vect_par_cnst_half): New.
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* config/aarch64/aarch64-protos.h
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(aarch64_simd_check_vect_par_cnst_half): New.
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* config/aarch64/predicates.md (vect_par_cnst_hi_half): Refactor
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the check out to aarch64_simd_check_vect_par_cnst_half.
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(vect_par_cnst_lo_half): Likewise.
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* config/aarch64/aarch64-simd.md
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(aarch64_simd_move_hi_quad_<mode>): Always use vec_par_cnst_lo_half.
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(move_hi_quad_<mode>): Always generate a low mask.
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2014-07-30 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
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* doc/invoke.texi (AVR Options): Add documentation about
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@ -200,6 +200,8 @@ bool aarch64_pad_arg_upward (enum machine_mode, const_tree);
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bool aarch64_pad_reg_upward (enum machine_mode, const_tree, bool);
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bool aarch64_regno_ok_for_base_p (int, bool);
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bool aarch64_regno_ok_for_index_p (int, bool);
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bool aarch64_simd_check_vect_par_cnst_half (rtx op, enum machine_mode mode,
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bool high);
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bool aarch64_simd_imm_scalar_p (rtx x, enum machine_mode mode);
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bool aarch64_simd_imm_zero_p (rtx, enum machine_mode);
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bool aarch64_simd_scalar_immediate_valid_for_move (rtx, enum machine_mode);
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@ -1022,7 +1022,7 @@
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(match_operand:<VHALF> 1 "register_operand" "w,r")
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(vec_select:<VHALF>
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(match_dup 0)
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(match_operand:VQ 2 "vect_par_cnst_hi_half" ""))))]
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(match_operand:VQ 2 "vect_par_cnst_lo_half" ""))))]
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"TARGET_SIMD && BYTES_BIG_ENDIAN"
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"@
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ins\\t%0.d[1], %1.d[0]
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@ -1035,7 +1035,7 @@
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(match_operand:<VHALF> 1 "register_operand" "")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, BYTES_BIG_ENDIAN);
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_aarch64_simd_move_hi_quad_be_<mode> (operands[0],
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operands[1], p));
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@ -7900,23 +7900,81 @@ aarch64_simd_scalar_immediate_valid_for_move (rtx op, enum machine_mode mode)
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return aarch64_simd_valid_immediate (op_v, vmode, false, NULL);
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}
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/* Construct and return a PARALLEL RTX vector. */
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/* Construct and return a PARALLEL RTX vector with elements numbering the
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lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
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the vector - from the perspective of the architecture. This does not
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line up with GCC's perspective on lane numbers, so we end up with
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different masks depending on our target endian-ness. The diagram
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below may help. We must draw the distinction when building masks
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which select one half of the vector. An instruction selecting
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architectural low-lanes for a big-endian target, must be described using
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a mask selecting GCC high-lanes.
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Big-Endian Little-Endian
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GCC 0 1 2 3 3 2 1 0
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| x | x | x | x | | x | x | x | x |
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Architecture 3 2 1 0 3 2 1 0
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Low Mask: { 2, 3 } { 0, 1 }
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High Mask: { 0, 1 } { 2, 3 }
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*/
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rtx
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aarch64_simd_vect_par_cnst_half (enum machine_mode mode, bool high)
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{
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int nunits = GET_MODE_NUNITS (mode);
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rtvec v = rtvec_alloc (nunits / 2);
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int base = high ? nunits / 2 : 0;
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int high_base = nunits / 2;
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int low_base = 0;
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int base;
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rtx t1;
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int i;
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for (i=0; i < nunits / 2; i++)
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if (BYTES_BIG_ENDIAN)
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base = high ? low_base : high_base;
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else
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base = high ? high_base : low_base;
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for (i = 0; i < nunits / 2; i++)
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RTVEC_ELT (v, i) = GEN_INT (base + i);
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t1 = gen_rtx_PARALLEL (mode, v);
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return t1;
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}
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/* Check OP for validity as a PARALLEL RTX vector with elements
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numbering the lanes of either the high (HIGH == TRUE) or low lanes,
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from the perspective of the architecture. See the diagram above
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aarch64_simd_vect_par_cnst_half for more details. */
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bool
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aarch64_simd_check_vect_par_cnst_half (rtx op, enum machine_mode mode,
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bool high)
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{
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rtx ideal = aarch64_simd_vect_par_cnst_half (mode, high);
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HOST_WIDE_INT count_op = XVECLEN (op, 0);
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HOST_WIDE_INT count_ideal = XVECLEN (ideal, 0);
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int i = 0;
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if (!VECTOR_MODE_P (mode))
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return false;
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if (count_op != count_ideal)
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return false;
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for (i = 0; i < count_ideal; i++)
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{
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rtx elt_op = XVECEXP (op, 0, i);
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rtx elt_ideal = XVECEXP (ideal, 0, i);
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if (GET_CODE (elt_op) != CONST_INT
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|| INTVAL (elt_ideal) != INTVAL (elt_op))
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return false;
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}
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return true;
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}
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/* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
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HIGH (exclusive). */
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void
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@ -207,62 +207,15 @@
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(define_special_predicate "vect_par_cnst_hi_half"
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(match_code "parallel")
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{
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HOST_WIDE_INT count = XVECLEN (op, 0);
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int nunits = GET_MODE_NUNITS (mode);
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int i;
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if (count < 1
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|| count != nunits / 2)
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return false;
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if (!VECTOR_MODE_P (mode))
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return false;
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for (i = 0; i < count; i++)
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{
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rtx elt = XVECEXP (op, 0, i);
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int val;
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if (GET_CODE (elt) != CONST_INT)
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return false;
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val = INTVAL (elt);
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if (val != (nunits / 2) + i)
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return false;
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}
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return true;
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return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
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})
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(define_special_predicate "vect_par_cnst_lo_half"
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(match_code "parallel")
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{
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HOST_WIDE_INT count = XVECLEN (op, 0);
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int nunits = GET_MODE_NUNITS (mode);
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int i;
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if (count < 1
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|| count != nunits / 2)
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return false;
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if (!VECTOR_MODE_P (mode))
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return false;
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for (i = 0; i < count; i++)
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{
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rtx elt = XVECEXP (op, 0, i);
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int val;
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if (GET_CODE (elt) != CONST_INT)
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return false;
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val = INTVAL (elt);
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if (val != i)
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return false;
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}
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return true;
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return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
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})
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(define_special_predicate "aarch64_simd_lshift_imm"
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(match_code "const_vector")
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{
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