pa.md (dbra pattern): Use output_dbra.
* pa.md (dbra pattern): Use output_dbra.
(dbra pattern #2): New pattern. Also use output_dbra.
(movb, inverted movb): New patterns.
From-SVN: r4887
This commit is contained in:
Jeff Law
parent
6bd5174eb2
commit
98b2d88783
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@ -2898,7 +2898,6 @@
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return \"depi %3,%2+%1-1,%1,%0\";
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}")
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;; The dbra pattern from hell.
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;; This insn is used for some loop tests, typically loops reversed when
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;; strength reduction is used. It is actually created when the instruction
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;; combination phase combines the special loop test. Since this insn
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@ -2918,72 +2917,7 @@
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(plus:SI (match_dup 0) (match_dup 1)))
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(clobber (match_scratch:SI 4 "=X,r,r"))]
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""
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"*
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{
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if (which_alternative == 0)
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{
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int nullify = INSN_ANNULLED_BRANCH_P (insn);
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int length = get_attr_length (insn);
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/* If this is a long branch with its delay slot unfilled, set `nullify'
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as it can nullify the delay slot and save a nop. */
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if (length == 2 && dbr_sequence_length () == 0)
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nullify = 1;
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/* If this is a short forward conditional branch which did not get
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its delay slot filled, the delay slot can still be nullified. */
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if (! nullify && length == 1 && dbr_sequence_length () == 0)
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nullify = forward_branch_p (insn);
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/* Handle short versions first. */
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if (length == 1 && nullify)
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return \"addib,%C2,n %1,%0,%3\";
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else if (length == 1 && ! nullify)
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return \"addib,%C2 %1,%0,%3\";
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else if (length == 2)
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{
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/* Handle weird backwards branch with a fulled delay slot
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which is nullified. */
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if (dbr_sequence_length () != 0
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&& ! forward_branch_p (insn)
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&& nullify)
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return \"addib,%N2,n %1,%0,.+12\;bl %3,0\";
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/* Handle normal cases. */
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if (nullify)
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return \"addi,%N2 %1,%0,%0\;bl,n %3,0\";
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else
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return \"addi,%N2 %1,%0,%0\;bl %3,0\";
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}
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else
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abort();
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}
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/* Deal with gross reload from FP register case. */
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else if (which_alternative == 1)
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{
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/* Move loop counter from FP register to MEM then into a GR,
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increment the GR, store the GR into MEM, and finally reload
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the FP register from MEM from within the branch's delay slot. */
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output_asm_insn (\"fstws %0,-16(0,%%r30)\;ldw -16(0,%%r30),%4\",operands);
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output_asm_insn (\"ldo %1(%4),%4\;stw %4,-16(0,%%r30)\", operands);
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if (get_attr_length (insn) == 6)
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return \"comb,%S2 0,%4,%3\;fldws -16(0,%%r30),%0\";
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else
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return \"comclr,%B2 0,%4,0\;bl %3,0\;fldws -16(0,%%r30),%0\";
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}
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/* Deal with gross reload from memory case. */
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else
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{
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/* Reload loop counter from memory, the store back to memory
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happens in the branch's delay slot. */
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output_asm_insn (\"ldw %0,%4\", operands);
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if (get_attr_length (insn) == 3)
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return \"addib,%C2 %1,%4,%3;stw %4,%0\";
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else
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return \"addi,%N2 %1,%4,%0\;bl %3,0\;stw %4,%0\";
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}
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}"
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"* output_dbra (operands, insn, which_alternative); "
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;; Do not expect to understand this the first time through.
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[(set_attr "type" "cbranch,multi,multi")
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(set (attr "length")
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@ -3024,6 +2958,153 @@
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(const_int 3)
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(const_int 4))))))])
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;; Simply another variant of the dbra pattern. More restrictive
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;; in testing the comparison operator as it must worry about overflow
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;; problems.
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(define_insn ""
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[(set (pc)
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(if_then_else
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(match_operator 2 "eq_neq_comparison_operator"
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[(match_operand:SI 0 "register_operand" "+!r,!*fx,!*m")
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(match_operand:SI 5 "const_int_operand" "")])
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(label_ref (match_operand 3 "" ""))
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(pc)))
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(set (match_dup 0)
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(plus:SI (match_dup 0) (match_operand:SI 1 "int5_operand" "L,L,L")))
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(clobber (match_scratch:SI 4 "=X,r,r"))]
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"INTVAL (operands[5]) == - INTVAL (operands[1])"
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"* return output_dbra (operands, insn, which_alternative);"
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;; Do not expect to understand this the first time through.
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[(set_attr "type" "cbranch,multi,multi")
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(set (attr "length")
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(if_then_else (eq_attr "alternative" "0")
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;; Loop counter in register case
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;; Short branch has length of 1
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;; Long branch has length of 2
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(if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
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(const_int 2047))
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(const_int 1)
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(const_int 2))
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;; Loop counter in FP reg case.
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;; Extra goo to deal with additional reload insns.
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(if_then_else (eq_attr "alternative" "1")
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(if_then_else (lt (match_dup 3) (pc))
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(if_then_else
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(lt (abs (minus (match_dup 3) (plus (pc) (const_int 6))))
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(const_int 2047))
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(const_int 6)
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(const_int 7))
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(if_then_else
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(lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
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(const_int 2047))
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(const_int 6)
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(const_int 7)))
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;; Loop counter in memory case.
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;; Extra goo to deal with additional reload insns.
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(if_then_else (lt (match_dup 3) (pc))
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(if_then_else
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(lt (abs (minus (match_dup 3) (plus (pc) (const_int 3))))
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(const_int 2047))
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(const_int 3)
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(const_int 4))
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(if_then_else
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(lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
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(const_int 2047))
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(const_int 3)
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(const_int 4))))))])
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(define_insn ""
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[(set (pc)
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(if_then_else
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(match_operator 2 "movb_comparison_operator"
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[(match_operand:SI 1 "register_operand" "r,r,r") (const_int 0)])
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(label_ref (match_operand 3 "" ""))
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(pc)))
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(set (match_operand:SI 0 "register_operand" "=!r,!*fx,!*m")
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(match_dup 1))]
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""
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"* return output_movb (operands, insn, which_alternative, 0); "
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;; Do not expect to understand this the first time through.
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[(set_attr "type" "cbranch,multi,multi")
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(set (attr "length")
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(if_then_else (eq_attr "alternative" "0")
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;; Loop counter in register case
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;; Short branch has length of 1
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;; Long branch has length of 2
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(if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
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(const_int 2047))
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(const_int 1)
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(const_int 2))
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;; Loop counter in FP reg case.
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;; Extra goo to deal with additional reload insns.
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(if_then_else (eq_attr "alternative" "1")
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(if_then_else (lt (match_dup 3) (pc))
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(if_then_else
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(lt (abs (minus (match_dup 3) (plus (pc) (const_int 3))))
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(const_int 2047))
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(const_int 3)
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(const_int 4))
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(if_then_else
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(lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
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(const_int 2047))
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(const_int 3)
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(const_int 4)))
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;; Loop counter in memory case.
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;; Extra goo to deal with additional reload insns.
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(if_then_else
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(lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
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(const_int 2047))
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(const_int 2)
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(const_int 3)))))])
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;; Handle negated branch.
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(define_insn ""
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[(set (pc)
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(if_then_else
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(match_operator 2 "movb_comparison_operator"
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[(match_operand:SI 1 "register_operand" "r,r,r") (const_int 0)])
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(pc)
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(label_ref (match_operand 3 "" ""))))
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(set (match_operand:SI 0 "register_operand" "=!r,!*fx,!*m")
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(match_dup 1))]
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""
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"* return output_movb (operands, insn, which_alternative, 1); "
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;; Do not expect to understand this the first time through.
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[(set_attr "type" "cbranch,multi,multi")
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(set (attr "length")
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(if_then_else (eq_attr "alternative" "0")
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;; Loop counter in register case
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;; Short branch has length of 1
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;; Long branch has length of 2
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(if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
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(const_int 2047))
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(const_int 1)
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(const_int 2))
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;; Loop counter in FP reg case.
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;; Extra goo to deal with additional reload insns.
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(if_then_else (eq_attr "alternative" "1")
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(if_then_else (lt (match_dup 3) (pc))
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(if_then_else
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(lt (abs (minus (match_dup 3) (plus (pc) (const_int 3))))
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(const_int 2047))
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(const_int 3)
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(const_int 4))
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(if_then_else
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(lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
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(const_int 2047))
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(const_int 3)
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(const_int 4)))
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;; Loop counter in memory case.
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;; Extra goo to deal with additional reload insns.
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(if_then_else
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(lt (abs (minus (match_dup 3) (plus (pc) (const_int 2))))
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(const_int 2047))
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(const_int 2)
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(const_int 3)))))])
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;; The next four peepholes take advantage of the new 5 operand
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;; fmpy{add,sub} instructions available on 1.1 CPUS. Basically
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;; fmpyadd performs a multiply and add/sub of independent operands
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