i386.md (and<mode>3): Generate zero-extends for TARGET_ZERO_EXTEND_WITH_AND &&...
* config/i386/i386.md (and<mode>3): Generate zero-extends for TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)) only. (*anddi3_doubleword): Split before reload. Merge with anddi->zext pre-reload splitter. (*andndi3_doubleword): Split before reload. (*<code>di3_doubleword): Ditto. (*one_cmpldi2_doubleword): Ditto. From-SVN: r272323
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
211b7533bf
commit
9919f5fe87
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@ -1,3 +1,14 @@
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2019-06-15 Uroš Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (and<mode>3): Generate zero-extends for
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TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
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only.
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(*anddi3_doubleword): Split before reload. Merge with
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anddi->zext pre-reload splitter.
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(*andndi3_doubleword): Split before reload.
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(*<code>di3_doubleword): Ditto.
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(*one_cmpldi2_doubleword): Ditto.
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2019-06-15 Jakub Jelinek <jakub@redhat.com>
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PR middle-end/90779
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@ -8365,7 +8365,10 @@
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if (<MODE>mode == DImode && !TARGET_64BIT)
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;
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else if (CONST_INT_P (operands[2]) && REG_P (operands[0]))
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else if (const_int_operand (operands[2], <MODE>mode)
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&& register_operand (operands[0], <MODE>mode)
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&& !(TARGET_ZERO_EXTEND_WITH_AND
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&& optimize_function_for_speed_p (cfun)))
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{
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unsigned HOST_WIDE_INT ival = UINTVAL (operands[2]);
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@ -8388,68 +8391,34 @@
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})
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(define_insn_and_split "*anddi3_doubleword"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
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(and:DI
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(match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
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(match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm")))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_64BIT && TARGET_STV && TARGET_SSE2
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&& ix86_binary_operator_ok (AND, DImode, operands)"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);
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if (operands[2] == const0_rtx)
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{
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operands[1] = const0_rtx;
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ix86_expand_move (SImode, &operands[0]);
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}
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else if (operands[2] != constm1_rtx)
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ix86_expand_binary_operator (AND, SImode, &operands[0]);
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else if (operands[5] == constm1_rtx)
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emit_note (NOTE_INSN_DELETED);
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if (operands[5] == const0_rtx)
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{
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operands[4] = const0_rtx;
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ix86_expand_move (SImode, &operands[3]);
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}
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else if (operands[5] != constm1_rtx)
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ix86_expand_binary_operator (AND, SImode, &operands[3]);
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DONE;
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})
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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[(set (match_operand:DI 0 "nonimmediate_operand")
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(and:DI
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(match_operand:DI 1 "nonimmediate_operand")
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(match_operand:DI 2 "const_int_operand")))
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(match_operand:DI 2 "x86_64_szext_general_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_64BIT && TARGET_STV && TARGET_SSE2
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&& ix86_binary_operator_ok (AND, DImode, operands)
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&& can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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unsigned HOST_WIDE_INT ival = UINTVAL (operands[2]);
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machine_mode mode;
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if (ival == GET_MODE_MASK (SImode))
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mode = SImode;
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else if (ival == GET_MODE_MASK (HImode))
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mode = HImode;
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else if (ival == GET_MODE_MASK (QImode))
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mode = QImode;
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else
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FAIL;
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split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);
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if (mode == SImode)
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if (operands[2] == const0_rtx)
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emit_move_insn (operands[0], const0_rtx);
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else if (operands[2] == constm1_rtx)
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emit_move_insn (operands[0], operands[1]);
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else
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emit_insn (gen_extend_insn
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(operands[0], gen_lowpart (mode, operands[1]),
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SImode, mode, 1));
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emit_move_insn (operands[3], const0_rtx);
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emit_insn (gen_andsi3 (operands[0], operands[1], operands[2]));
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if (operands[5] == const0_rtx)
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emit_move_insn (operands[3], const0_rtx);
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else if (operands[5] == constm1_rtx)
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emit_move_insn (operands[3], operands[4]);
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else
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emit_insn (gen_andsi3 (operands[3], operands[4], operands[5]));
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DONE;
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})
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@ -8886,14 +8855,14 @@
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})
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(define_insn "*andndi3_doubleword"
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[(set (match_operand:DI 0 "register_operand" "=&r,r,r,&r")
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[(set (match_operand:DI 0 "register_operand")
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(and:DI
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(not:DI (match_operand:DI 1 "register_operand" "r,0,r,0"))
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(match_operand:DI 2 "nonimmediate_operand" "rm,rm,0,rm")))
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(not:DI (match_operand:DI 1 "register_operand"))
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(match_operand:DI 2 "nonimmediate_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_64BIT && TARGET_STV && TARGET_SSE2"
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"#"
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[(set_attr "isa" "bmi,bmi,bmi,*")])
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"!TARGET_64BIT && TARGET_STV && TARGET_SSE2
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&& can_create_pseudo_p ()"
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"#")
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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@ -8902,7 +8871,7 @@
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(match_operand:DI 2 "nonimmediate_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_64BIT && TARGET_BMI && TARGET_STV && TARGET_SSE2
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&& reload_completed"
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&& can_create_pseudo_p ()"
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[(parallel [(set (match_dup 0)
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(and:SI (not:SI (match_dup 1)) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])
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@ -8914,20 +8883,25 @@
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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(and:DI
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(not:DI (match_dup 0))
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(match_operand:DI 1 "nonimmediate_operand")))
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(not:DI (match_operand:DI 1 "register_operand"))
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(match_operand:DI 2 "nonimmediate_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_64BIT && !TARGET_BMI && TARGET_STV && TARGET_SSE2
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&& reload_completed"
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[(set (match_dup 0) (not:SI (match_dup 0)))
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&& can_create_pseudo_p ()"
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[(set (match_dup 6) (not:SI (match_dup 1)))
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(parallel [(set (match_dup 0)
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(and:SI (match_dup 0) (match_dup 1)))
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(and:SI (match_dup 6) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])
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(set (match_dup 2) (not:SI (match_dup 2)))
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(parallel [(set (match_dup 2)
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(and:SI (match_dup 2) (match_dup 3)))
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(set (match_dup 7) (not:SI (match_dup 4)))
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(parallel [(set (match_dup 3)
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(and:SI (match_dup 7) (match_dup 5)))
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(clobber (reg:CC FLAGS_REG))])]
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"split_double_mode (DImode, &operands[0], 2, &operands[0], &operands[2]);")
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{
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operands[6] = gen_reg_rtx (SImode);
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operands[7] = gen_reg_rtx (SImode);
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split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);
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})
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(define_insn "*andn<mode>_1"
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[(set (match_operand:SWI48 0 "register_operand" "=r,r")
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@ -8980,44 +8954,44 @@
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"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
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(define_insn_and_split "*<code>di3_doubleword"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
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[(set (match_operand:DI 0 "nonimmediate_operand")
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(any_or:DI
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(match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
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(match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm")))
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(match_operand:DI 1 "nonimmediate_operand")
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(match_operand:DI 2 "x86_64_szext_general_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_64BIT && TARGET_STV && TARGET_SSE2
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&& ix86_binary_operator_ok (<CODE>, DImode, operands)"
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&& ix86_binary_operator_ok (<CODE>, DImode, operands)
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&& can_create_pseudo_p ()"
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"#"
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"&& reload_completed"
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"&& 1"
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[(const_int 0)]
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{
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split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);
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if (operands[2] == constm1_rtx)
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if (operands[2] == const0_rtx)
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emit_move_insn (operands[0], operands[1]);
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else if (operands[2] == constm1_rtx)
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{
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if (<CODE> == IOR)
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{
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operands[1] = constm1_rtx;
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ix86_expand_move (SImode, &operands[0]);
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}
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emit_move_insn (operands[0], constm1_rtx);
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else
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ix86_expand_unary_operator (NOT, SImode, &operands[0]);
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}
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else if (operands[2] != const0_rtx)
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else
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ix86_expand_binary_operator (<CODE>, SImode, &operands[0]);
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else if (operands[5] == const0_rtx)
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emit_note (NOTE_INSN_DELETED);
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if (operands[5] == constm1_rtx)
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if (operands[5] == const0_rtx)
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emit_move_insn (operands[3], operands[4]);
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else if (operands[5] == constm1_rtx)
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{
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if (<CODE> == IOR)
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{
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operands[4] = constm1_rtx;
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ix86_expand_move (SImode, &operands[3]);
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}
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emit_move_insn (operands[3], constm1_rtx);
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else
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ix86_expand_unary_operator (NOT, SImode, &operands[3]);
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}
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else if (operands[5] != const0_rtx)
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else
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ix86_expand_binary_operator (<CODE>, SImode, &operands[3]);
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DONE;
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})
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@ -9673,12 +9647,13 @@
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"ix86_expand_unary_operator (NOT, <MODE>mode, operands); DONE;")
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(define_insn_and_split "*one_cmpldi2_doubleword"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
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(not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
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[(set (match_operand:DI 0 "nonimmediate_operand")
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(not:DI (match_operand:DI 1 "nonimmediate_operand")))]
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"!TARGET_64BIT && TARGET_STV && TARGET_SSE2
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&& ix86_unary_operator_ok (NOT, DImode, operands)"
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&& ix86_unary_operator_ok (NOT, DImode, operands)
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&& can_create_pseudo_p ()"
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"#"
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"&& reload_completed"
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"&& 1"
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[(set (match_dup 0)
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(not:SI (match_dup 1)))
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(set (match_dup 2)
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