OpenE2K/gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

re PR target/80123 (libgomp tests pr66199-2.c and pr66199-5.c fail with -mcpu=power9)

Browse Source 
2017-03-21  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>

	PR target/80123
	* doc/md.texi (Constraints): Document wA constraint.
	* config/rs6000/constraints.md (wA): New.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add wA reg_class.
	(rs6000_init_hard_regno_mode_ok): Init wA constraint.
	* config/rs6000/rs6000.h (RS6000_CONSTRAINT_wA): New.
	* config/rs6000/vsx.md (vsx_splat_<mode>): Use wA constraint.

From-SVN: r246394
This commit is contained in:
Aaron Sawdey 2017-03-22 17:47:55 +00:00 committed by Aaron Sawdey
parent 2f029c0898
commit 992113522d
6 changed files with 24 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
gcc/ChangeLog
View File

@ -1,3 +1,13 @@
2017-03-21 Aaron Sawdey <acsawdey@linux.vnet.ibm.com>
PR target/80123
* doc/md.texi (Constraints): Document wA constraint.
* config/rs6000/constraints.md (wA): New.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add wA reg_class.
(rs6000_init_hard_regno_mode_ok): Init wA constraint.
* config/rs6000/rs6000.h (RS6000_CONSTRAINT_wA): New.
* config/rs6000/vsx.md (vsx_splat_<mode>): Use wA constraint.
2017-03-22 Cesar Philippidis <cesar@codesourcery.com>
PR c++/80029

3
gcc/config/rs6000/constraints.md
View File

@ -133,6 +133,9 @@
(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"
"Floating point register if the LFIWZX instruction is enabled or NO_REGS.")
(define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]"
"BASE_REGS if 64-bit instructions are enabled or NO_REGS.")
;; wB needs ISA 2.07 VUPKHSW
(define_constraint "wB"
"Signed 5-bit constant integer that can be loaded into an altivec register."

7
gcc/config/rs6000/rs6000.c
View File

@ -2468,6 +2468,7 @@ rs6000_debug_reg_global (void)
"wx reg_class = %s\n"
"wy reg_class = %s\n"
"wz reg_class = %s\n"
"wA reg_class = %s\n"
"wH reg_class = %s\n"
"wI reg_class = %s\n"
"wJ reg_class = %s\n"
@ -2500,6 +2501,7 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]],
@ -3210,7 +3212,10 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
}
if (TARGET_POWERPC64)
rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
{
rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
}
if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) /* SFmode */
{

1
gcc/config/rs6000/rs6000.h
View File

@ -1612,6 +1612,7 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wy, /* VSX register for SF */
RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */
RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */
RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */

2
gcc/config/rs6000/vsx.md
View File

@ -3072,7 +3072,7 @@
"=<VSa>, <VSa>,we,<VS_64dm>")
(vec_duplicate:VSX_D
(match_operand:<VS_scalar> 1 "splat_input_operand"
"<VS_64reg>,Z, b, wr")))]
"<VS_64reg>,Z, b, wA")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"@
xxpermdi %x0,%x1,%x1,0

3
gcc/doc/md.texi
View File

@ -3122,6 +3122,9 @@ FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
@item wz
Floating point register if the LFIWZX instruction is enabled or NO_REGS.
@item wA
Address base register if 64-bit instructions are enabled or NO_REGS.
@item wB
Signed 5-bit constant integer that can be loaded into an altivec register.