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[AArch64] Improve popcount expansion

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The popcount expansion uses umov to extend the result and move it back
to the integer register file.  If we model ADDV as a zero-extending
operation, fmov can be used to move back to the integer side. This
results in a ~0.5% speedup on deepsjeng on Cortex-A57.

A typical __builtin_popcount expansion is now:

	fmov	s0, w0
	cnt	v0.8b, v0.8b
	addv	b0, v0.8b
	fmov	w0, s0

gcc/
	* config/aarch64/aarch64-simd.md
	(aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>): New pattern.
	* config/aarch64/aarch64.md (popcount<mode>2): Use it instead of
	generating separate ADDV and zero_extend patterns.
	* config/aarch64/iterators.md (VDQV_E): New iterator.

testsuite/
	* gcc.target/aarch64/popcnt2.c: New test.
This commit is contained in:
Wilco Dijkstra 2020-02-12 18:19:25 +00:00
parent e5cc04a73a
commit 9921bbf9b2
6 changed files with 48 additions and 3 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
* config/aarch64/aarch64-simd.md
(aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>): New pattern.
* config/aarch64/aarch64.md (popcount<mode>2): Use it instead of
generating separate ADDV and zero_extend patterns.
* config/aarch64/iterators.md (VDQV_E): New iterator.
2020-02-12 Jeff Law <law@redhat.com>
* config/h8300/h8300.md (cpymemsi, movmd): Remove dead patterns,

11
gcc/config/aarch64/aarch64-simd.md
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@ -2474,6 +2474,17 @@
[(set_attr "type" "neon_reduc_add<q>")]
)
;; ADDV with result zero-extended to SI/DImode (for popcount).
(define_insn "aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>"
[(set (match_operand:GPI 0 "register_operand" "=w")
(zero_extend:GPI
(unspec:<VDQV_E:VEL> [(match_operand:VDQV_E 1 "register_operand" "w")]
UNSPEC_ADDV)))]
"TARGET_SIMD"
"add<VDQV_E:vp>\\t%<VDQV_E:Vetype>0, %1.<VDQV_E:Vtype>"
[(set_attr "type" "neon_reduc_add<VDQV_E:q>")]
)
(define_insn "aarch64_reduc_plus_internalv2si"
[(set (match_operand:V2SI 0 "register_operand" "=w")
(unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")]

4
gcc/config/aarch64/aarch64.md
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@ -4848,7 +4848,6 @@
{
rtx v = gen_reg_rtx (V8QImode);
rtx v1 = gen_reg_rtx (V8QImode);
rtx r = gen_reg_rtx (QImode);
rtx in = operands[1];
rtx out = operands[0];
if(<MODE>mode == SImode)
@ -4862,8 +4861,7 @@
}
emit_move_insn (v, gen_lowpart (V8QImode, in));
emit_insn (gen_popcountv8qi2 (v1, v));
emit_insn (gen_reduc_plus_scal_v8qi (r, v1));
emit_insn (gen_zero_extendqi<mode>2 (out, r));
emit_insn (gen_aarch64_zero_extend<mode>_reduc_plus_v8qi (out, v1));
DONE;
})

3
gcc/config/aarch64/iterators.md
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@ -208,6 +208,9 @@
;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
;; Advanced SIMD modes for Integer reduction across lanes (zero/sign extended).
(define_mode_iterator VDQV_E [V8QI V16QI V4HI V8HI])
;; All double integer narrow-able modes.
(define_mode_iterator VDN [V4HI V2SI DI])

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2020-02-12 Wilco Dijkstra <wdijkstr@arm.com>
* gcc.target/aarch64/popcnt2.c: New test.
2020-02-12 Marek Polacek <polacek@redhat.com>
PR c++/88819

21
gcc/testsuite/gcc.target/aarch64/popcnt2.c Normal file
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@ -0,0 +1,21 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
unsigned
foo (int x)
{
return __builtin_popcount (x);
}
unsigned long
foo1 (int x)
{
return __builtin_popcount (x);
}
/* { dg-final { scan-assembler-not {popcount} } } */
/* { dg-final { scan-assembler-times {cnt\t} 2 } } */
/* { dg-final { scan-assembler-times {fmov} 4 } } */
/* { dg-final { scan-assembler-not {umov} } } */
/* { dg-final { scan-assembler-not {uxtw} } } */
/* { dg-final { scan-assembler-not {sxtw} } } */