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re PR testsuite/36903 (Generic vectorizarion test failures) 

2009-12-21  Andy Hutchinson  <hutchinsonandy@gcc.gnu.org>

	PR testsuite/36903
	* gcc.dg/tree-ssa/gen-vect-11.c : Disable for avr target. It will not vectorize.
	* gcc.dg/tree-ssa/gen-vect-11a.c: Ditto.
	* gcc.dg/tree-ssa/gen-vect-2.c: Ditto.
	* gcc.dg/tree-ssa/gen-vect-25.c: Ditto.
	* gcc.dg/tree-ssa/gen-vect-26.c: Ditto.
	* gcc.dg/tree-ssa/gen-vect-28.c: Ditto.
	* gcc.dg/tree-ssa/gen-vect-32.c: Ditto.
	* gcc.dg/tree-ssa/pr23455.c: Test for 4 eliminations on avr target.
	* gcc.dg/tree-ssa/ssa-fre-26.c: XFAIL test for avr.
	* gcc.dg/tree-ssa/vrp47.c: Skip test for avr target due to low branch cost.

From-SVN: r155382
This commit is contained in:
Andy Hutchinson 2009-12-22 00:00:50 +00:00
parent 8d079e67d8
commit 993948c6da
11 changed files with 36 additions and 18 deletions
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16
gcc/testsuite/ChangeLog
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@ -1,3 +1,19 @@
2009-12-21 Andy Hutchinson <hutchinsonandy@gcc.gnu.org>
PR testsuite/36903
* gcc.dg/tree-ssa/gen-vect-11.c : Disable for avr target. It will
not vectorize.
* gcc.dg/tree-ssa/gen-vect-11a.c: Ditto.
* gcc.dg/tree-ssa/gen-vect-2.c: Ditto.
* gcc.dg/tree-ssa/gen-vect-25.c: Ditto.
* gcc.dg/tree-ssa/gen-vect-26.c: Ditto.
* gcc.dg/tree-ssa/gen-vect-28.c: Ditto.
* gcc.dg/tree-ssa/gen-vect-32.c: Ditto.
* gcc.dg/tree-ssa/pr23455.c: Test for 4 eliminations on avr target.
* gcc.dg/tree-ssa/ssa-fre-26.c: XFAIL test for avr.
* gcc.dg/tree-ssa/vrp47.c: Skip test for avr target due to low
branch cost.
2009-12-21 Thomas Koenig <tkoenig@gcc.gnu.org>
PR libfortran/PR42422

2
gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11.c
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@ -30,5 +30,5 @@ int main ()
}
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! avr-*-* } } } } */
/* { dg-final { cleanup-tree-dump "vect" } } */

2
gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11a.c
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@ -38,5 +38,5 @@ int main ()
}
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! avr-*-* } } } } */
/* { dg-final { cleanup-tree-dump "vect" } } */

4
gcc/testsuite/gcc.dg/tree-ssa/gen-vect-2.c
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@ -36,6 +36,6 @@ int main ()
return 0;
}
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! avr-*-* } } } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target { ! avr-*-* } } } } */
/* { dg-final { cleanup-tree-dump "vect" } } */

4
gcc/testsuite/gcc.dg/tree-ssa/gen-vect-25.c
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@ -54,6 +54,6 @@ int main (void)
return main_1 (n + 2, (int *) &n);
}
/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { ! avr-*-* } } } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target { ! avr-*-* } } } } */
/* { dg-final { cleanup-tree-dump "vect" } } */

6
gcc/testsuite/gcc.dg/tree-ssa/gen-vect-26.c
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@ -29,7 +29,7 @@ int main ()
}
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! avr-*-* } } } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target { ! avr-*-* } } } } */
/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target { ! avr-*-* } } } } */
/* { dg-final { cleanup-tree-dump "vect" } } */

6
gcc/testsuite/gcc.dg/tree-ssa/gen-vect-28.c
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@ -37,7 +37,7 @@ int main (void)
}
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! avr-*-* } } } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target { ! avr-*-* } } } } */
/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target { ! avr-*-* } } } } */
/* { dg-final { cleanup-tree-dump "vect" } } */

4
gcc/testsuite/gcc.dg/tree-ssa/gen-vect-32.c
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@ -29,6 +29,6 @@ int main ()
}
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! avr-*-* } } } } */
/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target { ! avr-*-* } } } } */
/* { dg-final { cleanup-tree-dump "vect" } } */

3
gcc/testsuite/gcc.dg/tree-ssa/pr23455.c
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@ -19,5 +19,6 @@ bi_windup(unsigned int *outbuf, unsigned int bi_buf)
/* We should eliminate one load of outcnt, which will in turn let us eliminate
one multiply of outcnt which will in turn let us eliminate
one add involving outcnt and outbuf. */
/* { dg-final { scan-tree-dump-times "Eliminated: 3" 1 "pre"} } */
/* { dg-final { scan-tree-dump-times "Eliminated: 3" 1 "pre" {target { ! avr-*-* } } } } */
/* { dg-final { scan-tree-dump-times "Eliminated: 4" 1 "pre" {target { avr-*-* } } } } */
/* { dg-final { cleanup-tree-dump "pre" } } */

3
gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-26.c
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@ -14,5 +14,6 @@ int foo (union U *p)
return u.i;
}
/* { dg-final { scan-tree-dump "Replaced u.i with 0 in" "fre" } } */
/* avr has 16 bit int and 32 bit float */
/* { dg-final { scan-tree-dump "Replaced u.i with 0 in" "fre" {xfail avr-*-* } } } */
/* { dg-final { cleanup-tree-dump "fre" } } */

4
gcc/testsuite/gcc.dg/tree-ssa/vrp47.c
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@ -1,9 +1,9 @@
/* Skip on MIPS, where LOGICAL_OP_NON_SHORT_CIRCUIT inhibits the setcc
optimizations that expose the VRP opportunity. */
/* Skip on S/390. Lower values in BRANCH_COST lead to two conditional
/* Skip on S/390 and avr. Lower values in BRANCH_COST lead to two conditional
jumps when evaluating an && condition. VRP is not able to optimize
this. */
/* { dg-do compile { target { { ! mips*-*-* } && { ! s390*-*-* } } } } */
/* { dg-do compile { target { ! "mips*-*-* s390*-*-* avr-*-*" } } } */
/* { dg-options "-O2 -fdump-tree-vrp -fdump-tree-dom" } */
int h(int x, int y)