invoke.texi (RS/6000 and PowerPC Options): Document -mspe option.
2003-04-06 Aldy Hernandez <aldyh@redhat.com> * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mspe option. * config/rs6000/eabispe.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Set rs6000_spe. * config/rs6000/eabi.h (TARGET_E500): Define. * config/rs6000/rs6000.h (TARGET_E500): Define. (TARGET_OPTIONS): Add spe= option. Declare rs6000_spe and rs6000_spe_string extern. * config/rs6000/rs6000.c (branch_positive_comparison_operator): Change TARGET_SPE to TARGET_E500. (ccr_bit): Change TARGET_SPE to TARGET_E500. Check for !TARGET_FPRS. (print_operand): Same. (rs6000_generate_compare): Same. (output_cbranch): Same. (rs6000_spe): Declare. (rs6000_spe_string): Declare. (rs6000_override_options): Call rs6000_parse_spe_option. (rs6000_parse_spe_option): New. From-SVN: r65319
This commit is contained in:
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@ -1,3 +1,29 @@
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2003-04-06 Aldy Hernandez <aldyh@redhat.com>
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* doc/invoke.texi (RS/6000 and PowerPC Options): Document -mspe
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option.
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* config/rs6000/eabispe.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Set
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rs6000_spe.
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* config/rs6000/eabi.h (TARGET_E500): Define.
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* config/rs6000/rs6000.h (TARGET_E500): Define.
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(TARGET_OPTIONS): Add spe= option.
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Declare rs6000_spe and rs6000_spe_string extern.
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* config/rs6000/rs6000.c (branch_positive_comparison_operator):
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Change TARGET_SPE to TARGET_E500.
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(ccr_bit): Change TARGET_SPE to TARGET_E500. Check for
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!TARGET_FPRS.
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(print_operand): Same.
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(rs6000_generate_compare): Same.
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(output_cbranch): Same.
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(rs6000_spe): Declare.
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(rs6000_spe_string): Declare.
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(rs6000_override_options): Call rs6000_parse_spe_option.
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(rs6000_parse_spe_option): New.
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2003-04-06 Steven Bosscher <steven@gcc.gnu.org>
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2003-04-06 Steven Bosscher <steven@gcc.gnu.org>
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* hashtable.c (gcc_obstack_init): Delete this function
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* hashtable.c (gcc_obstack_init): Delete this function
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@ -45,10 +45,12 @@ Boston, MA 02111-1307, USA. */
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#undef TARGET_SPE_ABI
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#undef TARGET_SPE_ABI
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#undef TARGET_SPE
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#undef TARGET_SPE
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#undef TARGET_E500
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#undef TARGET_ISEL
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#undef TARGET_ISEL
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#undef TARGET_FPRS
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#undef TARGET_FPRS
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#define TARGET_SPE_ABI rs6000_spe_abi
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#define TARGET_SPE_ABI rs6000_spe_abi
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#define TARGET_SPE (rs6000_cpu == PROCESSOR_PPC8540)
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#define TARGET_SPE rs6000_spe
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#define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540)
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#define TARGET_ISEL rs6000_isel
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#define TARGET_ISEL rs6000_isel
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#define TARGET_FPRS rs6000_fprs
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#define TARGET_FPRS rs6000_fprs
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@ -36,6 +36,8 @@ Boston, MA 02111-1307, USA. */
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/* See note below. */ \
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/* See note below. */ \
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/*if (rs6000_long_double_size_string == NULL)*/ \
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/*if (rs6000_long_double_size_string == NULL)*/ \
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/* rs6000_long_double_type_size = 128;*/ \
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/* rs6000_long_double_type_size = 128;*/ \
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if (rs6000_spe_string == NULL) \
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rs6000_spe = 1; \
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if (rs6000_isel_string == NULL) \
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if (rs6000_isel_string == NULL) \
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rs6000_isel = 1
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rs6000_isel = 1
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@ -95,12 +95,18 @@ int rs6000_spe_abi;
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/* Whether isel instructions should be generated. */
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/* Whether isel instructions should be generated. */
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int rs6000_isel;
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int rs6000_isel;
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/* Whether SPE simd instructions should be generated. */
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int rs6000_spe;
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/* Nonzero if we have FPRs. */
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/* Nonzero if we have FPRs. */
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int rs6000_fprs = 1;
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int rs6000_fprs = 1;
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/* String from -misel=. */
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/* String from -misel=. */
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const char *rs6000_isel_string;
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const char *rs6000_isel_string;
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/* String from -mspe=. */
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const char *rs6000_spe_string;
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/* Set to nonzero once AIX common-mode calls have been defined. */
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/* Set to nonzero once AIX common-mode calls have been defined. */
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static GTY(()) int common_mode_defined;
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static GTY(()) int common_mode_defined;
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@ -270,6 +276,7 @@ static rtx altivec_expand_stv_builtin PARAMS ((enum insn_code, tree));
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static void rs6000_parse_abi_options PARAMS ((void));
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static void rs6000_parse_abi_options PARAMS ((void));
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static void rs6000_parse_vrsave_option PARAMS ((void));
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static void rs6000_parse_vrsave_option PARAMS ((void));
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static void rs6000_parse_isel_option PARAMS ((void));
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static void rs6000_parse_isel_option PARAMS ((void));
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static void rs6000_parse_spe_option (void);
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static int first_altivec_reg_to_save PARAMS ((void));
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static int first_altivec_reg_to_save PARAMS ((void));
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static unsigned int compute_vrsave_mask PARAMS ((void));
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static unsigned int compute_vrsave_mask PARAMS ((void));
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static void is_altivec_return_reg PARAMS ((rtx, void *));
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static void is_altivec_return_reg PARAMS ((rtx, void *));
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@ -612,7 +619,7 @@ rs6000_override_options (default_cpu)
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}
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}
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}
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}
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if (rs6000_cpu == PROCESSOR_PPC8540)
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if (TARGET_E500)
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rs6000_isel = 1;
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rs6000_isel = 1;
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/* If we are optimizing big endian systems for space, use the load/store
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/* If we are optimizing big endian systems for space, use the load/store
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@ -701,6 +708,9 @@ rs6000_override_options (default_cpu)
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/* Handle -misel= option. */
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/* Handle -misel= option. */
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rs6000_parse_isel_option ();
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rs6000_parse_isel_option ();
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/* Handle -mspe= option. */
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rs6000_parse_spe_option ();
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#ifdef SUBTARGET_OVERRIDE_OPTIONS
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#ifdef SUBTARGET_OVERRIDE_OPTIONS
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SUBTARGET_OVERRIDE_OPTIONS;
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SUBTARGET_OVERRIDE_OPTIONS;
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#endif
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#endif
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@ -788,6 +798,20 @@ rs6000_parse_isel_option ()
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rs6000_isel_string);
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rs6000_isel_string);
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}
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}
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/* Handle -mspe= option. */
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static void
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rs6000_parse_spe_option (void)
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{
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if (rs6000_spe_string == 0)
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return;
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else if (!strcmp (rs6000_spe_string, "yes"))
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rs6000_spe = 1;
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else if (!strcmp (rs6000_spe_string, "no"))
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rs6000_spe = 0;
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else
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error ("unknown -mspe= option specified: '%s'", rs6000_spe_string);
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}
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/* Handle -mvrsave= options. */
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/* Handle -mvrsave= options. */
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static void
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static void
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rs6000_parse_vrsave_option ()
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rs6000_parse_vrsave_option ()
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@ -7009,7 +7033,7 @@ branch_positive_comparison_operator (op, mode)
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code = GET_CODE (op);
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code = GET_CODE (op);
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return (code == EQ || code == LT || code == GT
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return (code == EQ || code == LT || code == GT
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|| (TARGET_SPE && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE)
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|| (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE)
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|| code == LTU || code == GTU
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|| code == LTU || code == GTU
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|| code == UNORDERED);
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|| code == UNORDERED);
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}
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}
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@ -7469,11 +7493,13 @@ ccr_bit (op, scc_p)
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switch (code)
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switch (code)
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{
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{
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case NE:
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case NE:
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if (TARGET_SPE && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
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if (TARGET_E500 && !TARGET_FPRS
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&& TARGET_HARD_FLOAT && cc_mode == CCFPmode)
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return base_bit + 1;
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return base_bit + 1;
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return scc_p ? base_bit + 3 : base_bit + 2;
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return scc_p ? base_bit + 3 : base_bit + 2;
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case EQ:
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case EQ:
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if (TARGET_SPE && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
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if (TARGET_E500 && !TARGET_FPRS
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&& TARGET_HARD_FLOAT && cc_mode == CCFPmode)
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return base_bit + 1;
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return base_bit + 1;
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return base_bit + 2;
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return base_bit + 2;
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case GT: case GTU: case UNLE:
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case GT: case GTU: case UNLE:
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@ -7685,7 +7711,7 @@ print_operand (file, x, code)
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fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
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fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
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base_bit + 2, base_bit + 2);
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base_bit + 2, base_bit + 2);
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}
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}
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else if (TARGET_SPE && TARGET_HARD_FLOAT
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else if (TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT
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&& GET_CODE (x) == EQ
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&& GET_CODE (x) == EQ
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&& GET_MODE (XEXP (x, 0)) == CCFPmode)
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&& GET_MODE (XEXP (x, 0)) == CCFPmode)
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{
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{
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@ -8192,7 +8218,7 @@ print_operand (file, x, code)
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tmp = XEXP (x, 0);
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tmp = XEXP (x, 0);
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if (TARGET_SPE)
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if (TARGET_E500)
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{
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{
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/* Handle [reg]. */
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/* Handle [reg]. */
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if (GET_CODE (tmp) == REG)
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if (GET_CODE (tmp) == REG)
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@ -8477,7 +8503,8 @@ rs6000_generate_compare (code)
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compare_result = gen_reg_rtx (comp_mode);
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compare_result = gen_reg_rtx (comp_mode);
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/* SPE FP compare instructions on the GPRs. Yuck! */
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/* SPE FP compare instructions on the GPRs. Yuck! */
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if ((TARGET_SPE && TARGET_HARD_FLOAT) && rs6000_compare_fp_p)
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if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
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&& rs6000_compare_fp_p)
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{
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{
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rtx cmp, or1, or2, or_result, compare_result2;
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rtx cmp, or1, or2, or_result, compare_result2;
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@ -8602,7 +8629,7 @@ rs6000_generate_compare (code)
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except for flag_unsafe_math_optimizations we don't bother. */
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except for flag_unsafe_math_optimizations we don't bother. */
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if (rs6000_compare_fp_p
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if (rs6000_compare_fp_p
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&& ! flag_unsafe_math_optimizations
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&& ! flag_unsafe_math_optimizations
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&& ! (TARGET_HARD_FLOAT && TARGET_SPE)
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&& ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
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&& (code == LE || code == GE
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&& (code == LE || code == GE
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|| code == UNEQ || code == LTGT
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|| code == UNEQ || code == LTGT
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|| code == UNGT || code == UNLT))
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|| code == UNGT || code == UNLT))
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@ -8730,7 +8757,7 @@ output_cbranch (op, label, reversed, insn)
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code = reverse_condition (code);
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code = reverse_condition (code);
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}
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}
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if ((TARGET_SPE && TARGET_HARD_FLOAT) && mode == CCFPmode)
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if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
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{
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{
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/* The efscmp/tst* instructions twiddle bit 2, which maps nicely
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/* The efscmp/tst* instructions twiddle bit 2, which maps nicely
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to the GT bit. */
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to the GT bit. */
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@ -388,6 +388,8 @@ extern enum processor_type rs6000_cpu;
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N_("Specify size of long double (64 or 128 bits)") }, \
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N_("Specify size of long double (64 or 128 bits)") }, \
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{"isel=", &rs6000_isel_string, \
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{"isel=", &rs6000_isel_string, \
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N_("Specify yes/no if isel instructions should be generated") }, \
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N_("Specify yes/no if isel instructions should be generated") }, \
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{"spe=", &rs6000_spe_string, \
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N_("Specify yes/no if SPE SIMD instructions should be generated") },\
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{"vrsave=", &rs6000_altivec_vrsave_string, \
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{"vrsave=", &rs6000_altivec_vrsave_string, \
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N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec") }, \
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N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec") }, \
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{"longcall", &rs6000_longcall_switch, \
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{"longcall", &rs6000_longcall_switch, \
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extern int rs6000_altivec_abi;
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extern int rs6000_altivec_abi;
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extern int rs6000_spe_abi;
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extern int rs6000_spe_abi;
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extern int rs6000_isel;
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extern int rs6000_isel;
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extern int rs6000_spe;
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extern int rs6000_fprs;
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extern int rs6000_fprs;
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extern const char *rs6000_isel_string;
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extern const char *rs6000_isel_string;
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extern const char *rs6000_spe_string;
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extern const char *rs6000_altivec_vrsave_string;
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extern const char *rs6000_altivec_vrsave_string;
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extern int rs6000_altivec_vrsave;
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extern int rs6000_altivec_vrsave;
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extern const char *rs6000_longcall_switch;
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extern const char *rs6000_longcall_switch;
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#define TARGET_SPE_ABI 0
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#define TARGET_SPE_ABI 0
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#define TARGET_SPE 0
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#define TARGET_SPE 0
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#define TARGET_E500 0
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#define TARGET_ISEL 0
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#define TARGET_ISEL 0
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#define TARGET_FPRS 1
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#define TARGET_FPRS 1
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@ -447,6 +447,7 @@ in the following sections.
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-mabi=altivec -mabi=no-altivec @gol
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-mabi=altivec -mabi=no-altivec @gol
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-mabi=spe -mabi=no-spe @gol
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-mabi=spe -mabi=no-spe @gol
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-misel=yes -misel=no @gol
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-misel=yes -misel=no @gol
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-mspe=yes -mspe=no @gol
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-mprototype -mno-prototype @gol
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-mprototype -mno-prototype @gol
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-msim -mmvme -mads -myellowknife -memb -msdata @gol
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-msim -mmvme -mads -myellowknife -memb -msdata @gol
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-msdata=@var{opt} -mvxworks -mwindiss -G @var{num} -pthread}
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-msdata=@var{opt} -mvxworks -mwindiss -G @var{num} -pthread}
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@opindex misel
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@opindex misel
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This switch enables or disables the generation of ISEL instructions.
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This switch enables or disables the generation of ISEL instructions.
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@item -mspe=@var{yes/no}
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@itemx -mspe
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@opindex mspe
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This switch enables or disables the generation of SPE simd
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instructions.
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@item -mfull-toc
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@item -mfull-toc
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@itemx -mno-fp-in-toc
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@itemx -mno-fp-in-toc
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@itemx -mno-sum-in-toc
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@itemx -mno-sum-in-toc
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