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i386.c (x86_partial_flag_reg_stall): New. 

2006-09-07  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.c (x86_partial_flag_reg_stall): New.

	* config/i386/i386.h (x86_partial_flag_reg_stall): New.
	(TARGET_PARTIAL_FLAG_REG_STALL): New.

	* config/i386/i386.md (*ashldi3_cmp_rex64): Disabled for
	TARGET_PARTIAL_FLAG_REG_STALL.
	(*ashldi3_cconly_rex64): Likewise.
	(*ashlsi3_cmp): Likewise.
	(*ashlsi3_cconly): Likewise.
	(*ashlsi3_cmp_zext): Likewise.
	(*ashlhi3_cmp): Likewise.
	(*ashlhi3_cconly): Likewise.
	(*ashlqi3_cmp): Likewise.
	(*ashlqi3_cconly): Likewise.
	(*ashrdi3_cmp_rex64): Likewise.
	(*ashrdi3_cconly_rex64): Likewise.
	(*ashrsi3_cmp): Likewise.
	(*ashrsi3_cconly): Likewise.
	(*ashrsi3_cmp_zext): Likewise.
	(*ashrhi3_cmp): Likewise.
	(*ashrhi3_cconly): Likewise.
	(*ashrqi3_cmp): Likewise.
	(*ashrqi3_cconly): Likewise.
	(*lshrdi3_cmp_rex64): Likewise.
	(*lshrdi3_cconly_rex64): Likewise.
	(*lshrsi3_cmp): Likewise.
	(*lshrsi3_cconly): Likewise.
	(*lshrsi3_cmp_zext): Likewise.
	(*lshrhi3_cmp): Likewise.
	(*lshrhi3_cconly): Likewise.
	(*lshrqi2_cmp): Likewise.
	(*lshrqi2_cconly): Likewise.

From-SVN: r116757
This commit is contained in:
H.J. Lu 2006-09-07 17:53:18 +00:00 committed by H.J. Lu
parent f42684d5c9
commit 995cc36911
4 changed files with 147 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
gcc/ChangeLog
View File

@ -1,3 +1,39 @@
2006-09-07 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/i386.c (x86_partial_flag_reg_stall): New.
* config/i386/i386.h (x86_partial_flag_reg_stall): New.
(TARGET_PARTIAL_FLAG_REG_STALL): New.
* config/i386/i386.md (*ashldi3_cmp_rex64): Disabled for
TARGET_PARTIAL_FLAG_REG_STALL.
(*ashldi3_cconly_rex64): Likewise.
(*ashlsi3_cmp): Likewise.
(*ashlsi3_cconly): Likewise.
(*ashlsi3_cmp_zext): Likewise.
(*ashlhi3_cmp): Likewise.
(*ashlhi3_cconly): Likewise.
(*ashlqi3_cmp): Likewise.
(*ashlqi3_cconly): Likewise.
(*ashrdi3_cmp_rex64): Likewise.
(*ashrdi3_cconly_rex64): Likewise.
(*ashrsi3_cmp): Likewise.
(*ashrsi3_cconly): Likewise.
(*ashrsi3_cmp_zext): Likewise.
(*ashrhi3_cmp): Likewise.
(*ashrhi3_cconly): Likewise.
(*ashrqi3_cmp): Likewise.
(*ashrqi3_cconly): Likewise.
(*lshrdi3_cmp_rex64): Likewise.
(*lshrdi3_cconly_rex64): Likewise.
(*lshrsi3_cmp): Likewise.
(*lshrsi3_cconly): Likewise.
(*lshrsi3_cmp_zext): Likewise.
(*lshrhi3_cmp): Likewise.
(*lshrhi3_cconly): Likewise.
(*lshrqi2_cmp): Likewise.
(*lshrqi2_cconly): Likewise.
2006-09-07 Uros Bizjak <uros@kss-loka.si>
PR target/28946

1
gcc/config/i386/i386.c
View File

@ -761,6 +761,7 @@ const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_G
with partial reg. dependencies used by Athlon/P4 based chips, it is better
to leave it off for generic32 for now. */
const int x86_partial_reg_stall = m_PPRO;
const int x86_partial_flag_reg_stall = m_GENERIC;
const int x86_use_himode_fiop = m_386 | m_486 | m_K6;
const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_GENERIC);
const int x86_use_mov0 = m_K6;

2
gcc/config/i386/i386.h
View File

@ -164,6 +164,7 @@ extern const int x86_use_bt;
extern const int x86_cmpxchg, x86_cmpxchg8b, x86_cmpxchg16b, x86_xadd;
extern const int x86_use_incdec;
extern const int x86_pad_returns;
extern const int x86_partial_flag_reg_stall;
extern int x86_prefetch_sse;
#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
@ -182,6 +183,7 @@ extern int x86_prefetch_sse;
#define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
#define TARGET_MOVX (x86_movx & TUNEMASK)
#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
#define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK)
#define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK)
#define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK)
#define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)

135
gcc/config/i386/i386.md
View File

@ -10396,7 +10396,12 @@
(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(ashift:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, DImode, operands)"
&& ix86_binary_operator_ok (ASHIFT, DImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
|| (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))"
{
switch (get_attr_type (insn))
{
@ -10432,7 +10437,12 @@
(const_int 0)))
(clobber (match_scratch:DI 0 "=r"))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, DImode, operands)"
&& ix86_binary_operator_ok (ASHIFT, DImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
|| TARGET_DOUBLE_WITH_ADD)))"
{
switch (get_attr_type (insn))
{
@ -10713,7 +10723,12 @@
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashift:SI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, SImode, operands)"
&& ix86_binary_operator_ok (ASHIFT, SImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
|| (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))"
{
switch (get_attr_type (insn))
{
@ -10749,7 +10764,12 @@
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, SImode, operands)"
&& ix86_binary_operator_ok (ASHIFT, SImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
|| TARGET_DOUBLE_WITH_ADD)))"
{
switch (get_attr_type (insn))
{
@ -10786,7 +10806,12 @@
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, SImode, operands)"
&& ix86_binary_operator_ok (ASHIFT, SImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
|| TARGET_DOUBLE_WITH_ADD)))"
{
switch (get_attr_type (insn))
{
@ -10905,7 +10930,12 @@
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashift:HI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, HImode, operands)"
&& ix86_binary_operator_ok (ASHIFT, HImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
|| (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))"
{
switch (get_attr_type (insn))
{
@ -10941,7 +10971,12 @@
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, HImode, operands)"
&& ix86_binary_operator_ok (ASHIFT, HImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
|| TARGET_DOUBLE_WITH_ADD)))"
{
switch (get_attr_type (insn))
{
@ -11099,7 +11134,12 @@
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(ashift:QI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, QImode, operands)"
&& ix86_binary_operator_ok (ASHIFT, QImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
|| (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))"
{
switch (get_attr_type (insn))
{
@ -11135,7 +11175,12 @@
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFT, QImode, operands)"
&& ix86_binary_operator_ok (ASHIFT, QImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL
|| (operands[2] == const1_rtx
&& (TARGET_SHIFT1
|| TARGET_DOUBLE_WITH_ADD)))"
{
switch (get_attr_type (insn))
{
@ -11332,7 +11377,9 @@
(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"sar{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
@ -11345,7 +11392,9 @@
(const_int 0)))
(clobber (match_scratch:DI 0 "=r"))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
&& ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"sar{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
@ -11579,7 +11628,9 @@
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"sar{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
@ -11592,7 +11643,9 @@
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"sar{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
@ -11606,7 +11659,9 @@
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
&& ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"sar{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
@ -11692,7 +11747,9 @@
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashiftrt:HI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
&& ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"sar{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "HI")])
@ -11705,7 +11762,9 @@
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
&& ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"sar{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "HI")])
@ -11819,7 +11878,9 @@
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(ashiftrt:QI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"sar{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])
@ -11832,7 +11893,9 @@
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
&& ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"sar{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])
@ -11976,7 +12039,9 @@
(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
(lshiftrt:DI (match_dup 1) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"shr{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
@ -11989,7 +12054,9 @@
(const_int 0)))
(clobber (match_scratch:DI 0 "=r"))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"shr{q}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "DI")])
@ -12147,7 +12214,9 @@
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"shr{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
@ -12160,7 +12229,9 @@
(const_int 0)))
(clobber (match_scratch:SI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"shr{l}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
@ -12174,7 +12245,9 @@
(set (match_operand:DI 0 "register_operand" "=r")
(lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"shr{l}\t{%2, %k0|%k0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "SI")])
@ -12260,7 +12333,9 @@
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(lshiftrt:HI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"shr{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "HI")])
@ -12273,7 +12348,9 @@
(const_int 0)))
(clobber (match_scratch:HI 0 "=r"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
&& ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"shr{w}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "HI")])
@ -12386,7 +12463,9 @@
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(lshiftrt:QI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
&& ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"shr{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])
@ -12399,7 +12478,9 @@
(const_int 0)))
(clobber (match_scratch:QI 0 "=q"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
&& ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
&& (optimize_size
|| !TARGET_PARTIAL_FLAG_REG_STALL)"
"shr{b}\t{%2, %0|%0, %2}"
[(set_attr "type" "ishift")
(set_attr "mode" "QI")])